DSDT - Vanilla Speedstep - Generic Scope (_PR)

mm67 · November 23, 2009

i used pstate changer to find fid and vid values and applelpc is loading with dsdt fix i edited dsdt in a strange way here my dsdt and i don't see error on boot dsdt.dsl.zip

if you have time can you take a look at my dsdt ?

Your CST tables are messed up, try like this to get C1:

            Name (_CST, Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,)
                   }, 
                   One, 
                   One, 
                   0x03E8
               }
           })

italy4ever · November 23, 2009

Your CST tables are messed up, try like this to get C1:

            Name (_CST, Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,)
                   }, 
                   One, 
                   One, 
                   0x03E8
               }
           })

where do i need to add this code ? in which part of Scope?

edit:

i alredy have name_cst i my scope but it's different from yours i will try to change with that later thanks for advice

mm67 · November 23, 2009

where do i need to add this code ? in which part of Scope?

Replace CST tables with this one

These must be replaced:

            Name (_CST, Package (0x04)
           {
               0x02, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x00,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   0x14, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (SystemIO, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   0x28, 
                   0x02EE
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (SystemIO, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x3C, 
                   0x01F4
               }
           })

dabla · November 24, 2009

Thanks for the information Dave, didn't know you've OC your cpu that's why I copy/pasted it. Seems to be working know, still there is some contradictory information being show between MSR tools, VoodooMonitor, CPU-X and PStateChanger. The last 2 seem to show that it is working, is this normal behaviour? In attachment you'll find a screenshot + latest dsdt as reference. Many thanks once again :thumbsup_anim:

dsdt.dsl.zip

mastershredder · November 24, 2009

hello to all fellow Haxors i have been following this post very carfully and have already tried to do this manual editing of DSDT.dsl about 6 months ago that was part of another post on the forums i gave up in the end because i could not for the life of me get this to work. First off i understand from reading the detailed guide on the first page how to edit the table to include the tables. i have successfully patched the PX40 device as i have that in my DSDT as i am also using a gigabyte motherboard and i can now load the appleLPC.kext. My problem is that my DSDT.table does not have any inforation regarding the CST information my DSDT is patched to include various other fixes that arent related to this post however i am dying to get this working and hate asking anyone to fix things for me but i am at my wits ends and have tried all options with my limited knowledge.

my DSDT.aml starts like this

DefinitionBlock ("dsdt.aml", "DSDT", 1, "GBT ", "GBTUACPI", 0x00001000)

{

Scope (_PR)

{

Processor (CPU0, 0x00, 0x00000410, 0x06) {}

Processor (CPU1, 0x01, 0x00000410, 0x06) {}

Processor (CPU2, 0x02, 0x00000410, 0x06) {}

Processor (CPU3, 0x03, 0x00000410, 0x06) {}

}

Name (_S0, Package (0x04)

{

Zero,

Zero

})

Name (_S1, Package (0x04)

{

One,

Zero,

Zero

})

Name (_S3, Package (0x04) etc....

the following section below is completely missing from my dsdt.dsl i have tried adding it from the reference dsdt from the first post.

Scope (_PR.CPU0)

{

Method (_PSS, 0, NotSerialized)

{

Return (Package (0x03)

{

Package (0x06)

{

Zero,

0x0A,

0x0820,

Zero

}, etc....

the code goes on for a while before this section appears which is in my DSDT however like i said this obviously has important information such as cst and pst etc .

Name (_S0, Package (0x04)

{

Zero,

Zero

})

i feel such a noob for not being able to fix this myself i have tried using all the code from the reference dsdt from the sections i am missing but obviously FormerlyKnownAs has a different Cpu to me as when using voodoopstate.kext it show i have 4 pstates.

dsdt.dsl.zip

italy4ever · November 24, 2009

where do i need to add this code ? in which part of Scope?

edit:

i alredy have name_cst i my scope but it's different from yours i will try to change with that later thanks for advice

how can i thank you mm67?? speedstep is now working and temperature are lower than before speedstep_and_temp.tiff

A special thank also goes to FormerlyKnowAs for the entire guide and the patience to explain all the secrets of vanilla speedstep!!

FKA · November 24, 2009

Thanks for the information Dave, didn't know you've OC your cpu that's why I copy/pasted it. Seems to be working know, still there is some contradictory information being show between MSR tools, VoodooMonitor, CPU-X and PStateChanger. The last 2 seem to show that it is working, is this normal behaviour? In attachment you'll find a screenshot + latest dsdt as reference. Many thanks once again

You have remembred to remove voodoopstate.kext haven't you?

Remember pstatechanger only works with voodoopstate.kext (at least it does for me.).

D.

the code goes on for a while before this section appears which is in my DSDT however like i said this obviously has important information such as cst and pst etc .

DefinitionBlock ("dsdt.aml", "DSDT", 1, "GBT ", "GBTUACPI", 0x00001000)
{
Scope (_PR)
{
Processor (CPU0, 0x00, 0x00000410, 0x06) {}
Processor (CPU1, 0x01, 0x00000410, 0x06) {}
Processor (CPU2, 0x02, 0x00000410, 0x06) {}
Processor (CPU3, 0x03, 0x00000410, 0x06) {}
}

[b][color="#ff0000"]//modify the generic scope _pr from post 1 and insert the 
//code here
//
[/color][/b]

Name (_S0, Package (0x04)
{
Zero,
Zero,
Zero,
Zero
})
Name (_S1, Package (0x04)
{
One,
Zero,
Zero,
Zero
})
Name (_S3, Package (0x04) etc....

Hope this helps

D.

emp_% · November 24, 2009

Hi, someone can explain this values to me and how to get them right, please? I tried looking at the acpi.pdf but I cannot find any way to extract them. They look very different from the ones taken from FormerlyKnownAs's last dsdt.

Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, <----------
                   0x0A, <----------
                   0x0928, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, <---------- 
                   0x10, <----------
                   0x0828, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, <---------- 
                   0x10, <----------
                   0x0728, 
                   0x02
               },

	Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, <---------- 
                   0x10, <----------
                   0x0628, 
                   0x02
               }
           })
       }

Strange thing voltage for my processor doesn't change for the pstates:

Sorry for my bad english.

My dsdt attached(not modded for speedstepping).

dsdt.zip

snackole · November 24, 2009

I got speedstep working with your method, but now streaming video playback on Hulu is very choppy. Could someone take a look at my dsdt? Any help would be greatly appreciated.DSDT.dsl.zip

I'm using an EP35-DS3R with an E6550 overclocked to 3.0 ghz.

swede420 · November 24, 2009

I have got my ssdt table and other information from linux running acpidump and implemented them into my dsdt.

Running SMR Tools it says that speedstep is on as in the pic.

Is my speedstep working as it should? And have i done this wright?

{
	Processor (CPU0, 0x00, 0x00000410, 0x06) {}
	Processor (CPU1, 0x01, 0x00000410, 0x06) {}
	Processor (CPU2, 0x02, 0x00000410, 0x06) {}
	Processor (CPU3, 0x03, 0x00000410, 0x06) {}
}

Scope (\)
{
	Name (SSDT, Package (0x18)
	{
		"CPU0IST ", 
		0xDFEE7F00, 
		0x022A, 
		"CPU1IST ", 
		0xDFEE83C0, 
		0x0152, 
		"CPU0CST ", 
		Zero, 
		0xF000E816, 
		"CPU1CST ", 
		Zero, 
		0xF000E816, 
		"CPU2IST ", 
		Zero, 
		0xF000E816, 
		"CPU3IST ", 
		Zero, 
		0xF000E816, 
		"CPU2CST ", 
		Zero, 
		0xF000E816, 
		"CPU3CST ", 
		Zero, 
		0xF000E816
	})
	Name (CFGD, 0x02030302)
	Name (PDC0, 0x80000000)
	Name (PDC1, 0x80000000)
	Name (PDC2, 0x80000000)
	Name (PDC3, 0x80000000)
}

Scope (\_PR.CPU0)
{
	Method (_PPC, 0, NotSerialized)
	{
		Return (0x00)
	}

	Method (_PCT, 0, NotSerialized)
	{
		If (LEqual (And (CFGD, 0x00060000), 0x00020000))
		{
			Return (Package (0x02)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x10,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000880, // Address
						,)
				}, 

				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x10,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000882, // Address
						,)
				}
			})
		}

		If (LEqual (And (CFGD, 0x00060000), 0x00040000))
		{
			Return (Package (0x02)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}
			})
		}

		If (LOr (And (CFGD, 0x4000), And (CFGD, 0x00010000)))
		{
			Return (Package (0x02)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}
			})
		}

		Return (Package (0x02)
		{
			ResourceTemplate ()
			{
				Register (SystemIO, 
					0x10,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000880, // Address
					,)
			}, 

			ResourceTemplate ()
			{
				Register (SystemIO, 
					0x10,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000882, // Address
					,)
			}
		})
	}

	Method (_PSS, 0, NotSerialized)
	{
		If (LEqual (And (CFGD, 0x00060000), 0x00020000))
		{
			Return (SPSS)
		}

		If (LEqual (And (CFGD, 0x00060000), 0x00040000))
		{
			Return (NPSS)
		}

		If (LOr (And (CFGD, 0x4000), And (CFGD, 0x00010000)))
		{
			Return (NPSS)
		}

		Return (SPSS)
	}

	Name (SPSS, Package (0x02)
	{
		Package (0x06)
		{
			0x00000BB8, 
			0x000157C0, 
			0x000000A0, 
			0x0000000A, 
			0x00000036, 
			0x00000000
		}, 

		Package (0x06)
		{
			0x000007D0, 
			0x0000D6D8, 
			0x000000A0, 
			0x0000000A, 
			0x00000136, 
			0x00000001
		}
	})
	Name (NPSS, Package (0x02)
	{
		Package (0x06)
		{
			0x00000BB8, 
			0x000157C0, 
			0x0000000A, 
			0x0000000A, 
			0x0000092A, 
			0x0000092A
		}, 

		Package (0x06)
		{
			0x000007D0, 
			0x0000D6D8, 
			0x0000000A, 
			0x0000000A, 
			0x0000061C, 
			0x0000061C
		}
	})
}

Scope (\_PR.CPU1)
{
	Method (_PPC, 0, NotSerialized)
	{
		Return (0x00)
	}

	Method (_PCT, 0, NotSerialized)
	{
		If (LEqual (And (CFGD, 0x00060000), 0x00020000))
		{
			Return (Package (0x02)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x10,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000880, // Address
						,)
				}, 

				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x10,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000882, // Address
						,)
				}
			})
		}

		If (LEqual (And (CFGD, 0x00060000), 0x00040000))
		{
			Return (Package (0x02)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}
			})
		}

		If (LOr (And (CFGD, 0x4000), And (CFGD, 0x00010000)))
		{
			Return (Package (0x02)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}
			})
		}

		Return (Package (0x02)
		{
			ResourceTemplate ()
			{
				Register (SystemIO, 
					0x10,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000880, // Address
					,)
			}, 

			ResourceTemplate ()
			{
				Register (SystemIO, 
					0x10,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000882, // Address
					,)
			}
		})
	}

	Method (_PSS, 0, NotSerialized)
	{
		Return (\_PR.CPU0._PSS)
	}
}

Scope (\_PR.CPU2)
{
	Name (HI2, 0x00)
	Name (HC2, 0x00)
	Name (TLD2, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP2)
		Store (CAP2, PDC2)
		If (LEqual (TLD2, 0x00))
		{
			If (LEqual (And (PDC2, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST2, SystemMemory, DerefOf (Index (SSDT, 0x0D)), DerefOf (Index (SSDT, 0x0E
						)))
					Load (IST2, HI2)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST2, SystemMemory, DerefOf (Index (SSDT, 0x13)), DerefOf (Index (SSDT, 0x14
						)))
					Load (CST2, HC2)
				}

				Store (0x01, TLD2)
			}
		}
	}
}

Scope (\_PR.CPU3)
{
	Name (HI3, 0x00)
	Name (HC3, 0x00)
	Name (TLD3, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP3)
		Store (CAP3, PDC3)
		If (LEqual (TLD3, 0x00))
		{
			If (LEqual (And (PDC3, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST3, SystemMemory, DerefOf (Index (SSDT, 0x10)), DerefOf (Index (SSDT, 0x11
						)))
					Load (IST3, HI3)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST3, SystemMemory, DerefOf (Index (SSDT, 0x16)), DerefOf (Index (SSDT, 0x17
						)))
					Load (CST3, HC3)
				}

				Store (0x01, TLD3)
			}
		}
	}
}

FKA · November 24, 2009

Hi, someone can explain this values to me and how to get them right, please? I tried looking at the acpi.pdf but I cannot find any way to extract them. They look very different from the ones taken from FormerlyKnownAs's last dsdt.

Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, <----------
                   0x0A, <----------
                   0x0928, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, <---------- 
                   0x10, <----------
                   0x0828, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, <---------- 
                   0x10, <----------
                   0x0728, 
                   0x02
               },

	Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, <---------- 
                   0x10, <----------
                   0x0628, 
                   0x02
               }
           })
       }

Strange thing voltage for my processor doesn't change for the pstates:

Sorry for my bad english.

My dsdt attached(not modded for speedstepping).

dsdt.zip

Those values should all be 0x10 and it is latency.

Your vCore does not change because you have entered the same VId value (28) for each p-state.

Please follow the guide an find your correct FID and VID vaues with voodoopstates.kext and pstatechanger.

Dont forget to remove the kext once you have written down the FID VID vaues.

EDIT ... you need to run voodoopstates and pstatechanger BEFORE you make any DSDT edits to Scope (_PR)

I got speedstep working with your method, but now streaming video playback on Hulu is very choppy. Could someone take a look at my dsdt? Any help would be greatly appreciated.DSDT.dsl.zip
I'm using an EP35-DS3R with an E6550 overclocked to 3.0 ghz.

Sounds like the old IRQ problem.

The IRQ's - below - need removing:

                0x01,               // Alignment
                           0x02,               // Length
                           )
                       IRQNoFlags ()
                           {2}
                   })
               }

This is covered in more detail earlyer on in the thread.

I have got my ssdt table and other information from linux running acpidump and implemented them into my dsdt.
Running SMR Tools it says that speedstep is on as in the pic.

Is my speedstep working as it should? And have i done this wright?

Please read updated post 1. and try using the generic Scope (_PR) code I've posted there.

Cheers

D.

snackole · November 24, 2009

You are pure genius my friend. Thank you very much!

emp_% · November 24, 2009

Those values should all be 0x10 and it is latency.

Your vCore does not change because you have entered the same VId value (28) for each p-state.

Please follow the guide an find your correct FID and VID vaues with voodoopstates.kext and pstatechanger.

Dont forget to remove the kext once you have written down the FID VID vaues.

EDIT ... you need to run voodoopstates and pstatechanger BEFORE you make any DSDT edits to Scope (_PR)

I did not enter any change in Scope(_PR) except remove cpu aliases. May I need to run snow without NullCpuPM.kext?

Thanks very much for the speed answer.

swede420 · November 25, 2009

Please read updated post 1. and try using the generic Scope (_PR) code I've posted there.

You mean like this? Or should i change some other values too?

Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

   Scope (\)
   {
       Name (SSDT, Package (0x18)
       {
           "CPU0IST ", 
           0xDFEE7F00, 
           0x022A, 
           "CPU1IST ", 
           0xDFEE83C0, 
           0x0152, 
           "CPU0CST ", 
           Zero, 
           0xF000E816, 
           "CPU1CST ", 
           Zero, 
           0xF000E816, 
           "CPU2IST ", 
           Zero, 
           0xF000E816, 
           "CPU3IST ", 
           Zero, 
           0xF000E816, 
           "CPU2CST ", 
           Zero, 
           0xF000E816, 
           "CPU3CST ", 
           Zero, 
           0xF000E816
       })
       Name (CFGD, 0x02030302)
       Name (PDC0, 0x80000000)
       Name (PDC1, 0x80000000)
       Name (PDC2, 0x80000000)
       Name (PDC3, 0x80000000)
   }

   Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x092A, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x082A, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0729, 
                   0x02
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0628, 
                   0x03
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

FKA · November 25, 2009

I did not enter any change in Scope(_PR) except remove cpu aliases. May I need to run snow without NullCpuPM.kext?

Thanks very much for the speed answer.

If you want vanilla speedstep you need to add the generic Scope (_PR) code - making sure you have edited the relevant FID and VID values that you have got from pstateschanger.

ONLY then you can remove NUllCPUPM kext.

You mean like this? Or should i change some other values too?

No more like this: - if you have quad core CPU and I'm assuming you mhave correct FID/VID for your 4 p-states?!:

   Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

   Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x092A, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x082A, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0729, 
                   0x02
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0628, 
                   0x03
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

   Scope (_PR.CPU2)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

}

swede420 · November 25, 2009

No more like this: - if you have quad core CPU and I'm assuming you mhave correct FID/VID for your 4 p-states?!:

   Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

   Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x092A, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x082A, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0729, 
                   0x02
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0628, 
                   0x03
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

   Scope (_PR.CPU2)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

}

Thank you for your patients with a N00B like me.

I have dual core! Am i done then, or what?

MacUser2525 · November 25, 2009

Thank you for your patients with a N00B like me.
I have dual core! Am i done then, or what?

If the settings work and you have speed step then yes your done although since you have dual core you may want to remove the CPU2 and CPU3 parts if you want. If speed step still is not working with these settings and you have your model set to iMac then you may want to change to MacPro, it would not work on my testing dual core machine until I did this. Thanks to all who worked on this it works great on both my machines.

swede420 · November 25, 2009

If the settings work and you have speed step then yes your done although since you have dual core you may want to remove the CPU2 and CPU3 parts if you want. If speed step still is not working with these settings and you have your model set to iMac then you may want to change to MacPro, it would not work on my testing dual core machine until I did this. Thanks to all who worked on this it works great on both my machines.

I already have removed the cp2,3 part and added dvid to LPCB, and my appleLPC kext is loading.

How can i absolutely be sure that speed step is on in my system? Thanks to all who worked with this.

MacUser2525 · November 25, 2009

I already have removed the cp2,3 part and added dvid to LPCB, and my appleLPC kext is loading.
How can i absolutely be sure that speed step is on in my system? Thanks to all who worked with this.

Install Voodoo Monitor when looking at it you will see your P-States in its section and then in the Status you will see the voltages and multiplier changes if it is working. You want to remove the Voodoopstate, VoodooPower, NullCPU, or Disabler.kext if it has the IntelCPUManagement in its blacklist basically anything that interferes with it to make sure you get true readings.

swede420 · November 25, 2009

Install Voodoo Monitor when looking at it you will see your P-States in its section and then in the Status you will see the voltages and multiplier changes if it is working. You want to remove the Voodoopstate, VoodooPower, NullCPU, or Disabler.kext if it has the IntelCPUManagement in its blacklist basically anything that interferes with it to make sure you get true readings.

Thank you very much man. I went on and installed the kext of the monitor and restarted. As i have already removed NULLCPUP kext and dont have the others you named it could not fail to read.

As you mentioned both Voltage and Multiplier changed, even frequency changed.

The strange is that SleepEnabler gives me panic upon boot now!!!

I have a question fo you

which one should i trust now?

mitch_de · November 25, 2009

Both mVolts shown are in real the same mVolts!

Only the way (formula) they compute VID(1E,...) to mVolts is different - so different mVolts shown for same VID(=real mVolts).

If both shows same VID , and the VID is correct its OK!. PstateChanger mVolts conputing should be the real mVolts.

Bansaku · November 25, 2009

I am having trouble getting PStateChanger to work on my i7 860. I have VoodooPState.kext loaded (AppleLPC.kext loads by default as my Mobo ID is listed in the plist) yet PStateChanger crashes when I get info, the other options are all blank. Any suggestions? Is there anything I need to remove that may conflict with the kext? Does anyone have the values for i7 860 by chance? :rolleyes:

mastershredder · November 25, 2009

Thanks for the quick reply FormerlyKnownAs i have spent another sleepless night over this speedstepping i am giving up for today i have made the cst errors dissapear and voodoo monitor shows that my cpu which is a q6600 is running on its lowest multiplier however when running a few cpu intensive apps i cannot see this multiplier going up. also alarmingly is the fact when it bootups on the apple logo the grey loading wheel starts lagging about 10 secs into boot until it fully boots and the dock and other things seem less fluid in terms of frames per second rendering. Audio seems to slow down slightly unless mouse is rapidly shaken. the methods iv used in DSDT are the included applelpc fix using device px40. This is confirmed that the AppleLPC.kext is loading. The first table at the begging of my DSDT is IntelPm the second is ist01 then ist02 both these tables have the cst methods added and ist01 has the FID and VID info for all four of my pStates added these tables were dumped from windows and ist01 orignally only had 2 pStates which were full throttle x9 multiplier and x6 Multiplier so was a bit sceptical about seeing 4 with voodoopstate.kext however i have added the in between multipliers x7 and x8 with the values shown in PStateChanger. I would like to know what the following highlighted values are with repsect to the pStates and their importance as for the missing two pstates i added these values have just been replaced with Zero,.

Name (NPSS, Package (0x02)

{

Package (0x06)

{

0x00000BB8, < What are these values and how to calculate for different pStates that

0x000157C0, < were not included in cpu0Ist .

0x0000000A,

0x00000925,

0x00000925

},

Also is there any values that need to be altered from the CST methods that relate to specific hardware from your original template as i have just copied the method as a whole?

again thanks for everyones input in this thread if it werent for the tireless efforts of various people we wouldnt have our custom rigs to the vanilla state they are today. Peace Out

attached is my current DSDT with the problems mentioned above.

dsdt.dsl.zip

MacKonsti · November 25, 2009

Good afternoon to all thread members and gurus, I was trying to read the whole thread to find a reply to this generic question, but nothing clear was said:

1. What is the difference between the CPU scopes in all DSDT.aml found? Mine originally had zeros...

originally in BIOS/DSDT
Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) {} etc.
changed to:
Processor (\_PR.CPU0, 0x00([i]to03[/i]), 0x00000[b]410[/b], 0x06) {} etc.
[i]or[/i]
Processor (\_PR.CPU0, 0x00([i]to03[/i]), 0x00000[b]810[/b], 0x06) {} etc.

For Speedstepping code, some have 0410 and others 0810. Are they copied from dumps from original Macs?

What is served if I place the numbers instead of zero's? Are these CPU-model-related?

I have a QuadCore Q9550 processor at 2.83MHz, in a Shuttle XPC SG31G2)

2. Also, in the sample code provided in the first post (to be completed with our CPU's proper P-State values) there's an entry in Method _PSS:

Return (Package (0x06)  // Processor Q9550 has 6 P-states
{
Package (0x06)
{
	[i]0x00,[/i]
	[i]0x00,[/i]
	[b]0x10,[/b]
	[b]0x10,[/b]
	0x4824,  // My Q9550 State #1 is 0x4824
	0x00
},
}

where you say that 0x10 is a value for latency but I see others using values instead of zeros in the first two entries.

3. Finally, I see that for the next 2 cores CPU2 and CPU3, your 'Scope' code has reference to both CPU0 and CPU1. Is this done on purpose?

Scope (\_PR.CPU2)
{
Method (_PSS, 0, NotSerialized)
{
	Return (^^[b]CPU0[/b]._PSS ())
}
Method (_PSD, 0, NotSerialized)
{
	Return (^^[b]CPU0[/b]._PSD ())
}
Method (_CST, 0, NotSerialized)
{
	Return (^^[b]CPU1[/b]._CST ())
}
}

Thanks in advance.

FKA · November 25, 2009

Name (NPSS, Package (0x02)
{

Package (0x06)

{

0x00000BB8, < What are these values and how to calculate for different pStates that

0x000157C0, < were not included in cpu0Ist .

0x0000000A,

0x0000000A,

0x00000925,

0x00000925

},

Also is there any values that need to be altered from the CST methods that relate to specific hardware from your original template as i have just copied the method as a whole?

again thanks for everyones input in this thread if it werent for the tireless efforts of various people we wouldnt have our custom rigs to the vanilla state they are today. Peace Out

attached is my current DSDT with the problems mentioned above.

The values you've highlighted are power mW and FSB. These can be left at 0 as the OS does not use them.

Please try the generic code. It's proved to work on many Gigabyte and Asus MB's.

The CST code is also generic .. no need to change it - just add FID + VID to PSS!

D

Good afternoon to all thread members and gurus, I was trying to read the whole thread to find a reply to this generic question, but nothing clear was said:

1. What is the difference between the CPU scopes in all DSDT.aml found? Mine originally had zeros...
originally in BIOS/DSDT
Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) {} etc.
changed to:
Processor (\_PR.CPU0, 0x00([i]to03[/i]), 0x00000[b]410[/b], 0x06) {} etc.
[i]or[/i]
Processor (\_PR.CPU0, 0x00([i]to03[/i]), 0x00000[b]810[/b], 0x06) {} etc.
For Speedstepping code, some have 0410 and others 0810. Are they copied from dumps from original Macs?

That's odd!

I think we discovered that 410 was for quad core and 810 for dual (please someone correct if wrong.)

Try with your native values of zero. if that doesn't work try with 410 and 810.

They are not dumps from Mac they are from PC DSDT.

2. Also, in the sample code provided in the first post (to be completed with our CPU's proper P-State values) there's an entry in Method _PSS:
Return (Package (0x06)  // Processor Q9550 has 6 P-states
{
Package (0x06)
{
	[i]0x00,[/i]
	[i]0x00,[/i]
	[b]0x10,[/b]
	[b]0x10,[/b]
	0x4824,  // My Q9550 State #1 is 0x4824
	0x00
},
}
where you say that 0x10 is a value for latency but I see others using values instead of zeros in the first two entries.

First two values are freq FSb and power mW - not used - you can put anything there - best leave as zero.

3. Finally, I see that for the next 2 cores CPU2 and CPU3, your 'Scope' code has reference to both CPU0 and CPU1. Is this done on purpose?
Scope (\_PR.CPU2)
{
Method (_PSS, 0, NotSerialized)
{
	Return (^^[b]CPU0[/b]._PSS ())
}
Method (_PSD, 0, NotSerialized)
{
	Return (^^[b]CPU0[/b]._PSD ())
}
Method (_CST, 0, NotSerialized)
{
	Return (^^[b]CPU1[/b]._CST ())
}
}
Thanks in advance.

It is!

D

DSDT - Vanilla Speedstep - Generic Scope (_PR)

Recommended Posts

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites