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DSDT - Vanilla Speedstep - Generic Scope (_PR)

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This guide assumes you are already experienced in editing DSDT files.

Please DO NOT post full DSDT files in a code box. Please Post DSDT.dsl.zip files

You will firstly have to have extracted your DSDT.aml. This can be done with fassl's DSDT patcher or koalala's ACPI patcher.

 

Once you have extracted your DSDT.aml file you must decompile the file using IASLME. mitch_de has the most up to date version available here.

 

Now looking at your DSDT.dsl file we're going to edit the CPU part of 'Scope (PR)' which, unedited should look something like:

 

{
   Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000[color="#000000"]410[/color], 0x06) {}
       Processor (CPU1, 0x01, 0x00000[color="#000000"]410[/color], 0x06) {}
       Processor (CPU2, 0x02, 0x00000[color="#000000"]410[/color], 0x06) {}
       Processor (CPU3, 0x03, 0x00000[color="#000000"]410[/color], 0x06) {}
   }

/////// below removed 

 

Note this is not a simple cut and paste job you are going to have to spend some time working out some of the data that's to be includeded in the P and C state code.

 

Ok - to the above code we will add this:

Note: Do Not copy and paste from the code box. This code is attached as a text file at the end of the post.

 

    Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x0[b][color="#ff0000"]R[/color][/b])
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x[b][color="#ff0000"]SSSS[/color][/b], //FId/VID of p-state 0 (HIGHEST P-state)
                   Zero     //  p-state 0
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x[b][color="#ff0000"]SSSS[/color][/b],  // FID/VID for p-state 1
                   One        // p-state 1
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x[b][color="#ff0000"]SSSS[/color][/b], // FID/VID 
                   0x02     //p-state 2
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

   [color="#00ff00"]Scope (_PR.CPU2)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }[/color]

 

Obviously the above is for a quad core CPU with 3 p-states defined.

For a Dual core CPu you would need to remove the section highlighted in green.

 

You may also have to define more than 3 p-states but we'll get to that shortly.

 

You will see there are various values highlighted in red.

Firstly - R

 

R needs to be replaced with the number of p-states you have defined so in this case 3 p-states are defined so R would be replaced with 3, with 4 p-states defined R is repaced with 4 and so on.

 

The values represented above by S are a combination of FID and VID. There is a good explanation of FID and VID values here .

For ease we'll find these values using voodoopstate.kext and pstatechanger both linked at the end of this post.

Install the kext reboot and run pstatechanger,

post-275122-1258561690_thumb.png

You can see I have 3 p-states, you may have more. So from this you can see for my 0 p-state I should have a FID of 08 and a VID of 20.

Adding this to the Mehtod _PSS partf of the code like so:

    Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x03)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0820, 
                   Zero
               }, 

 

Repeat for each p-state, so again in my case I end up with:

    Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x03)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0820, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x071B, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0616, 
                   0x02
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

   Scope (_PR.CPU2)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

 

This code can now be added to your DSDT.dsl file, placed under your CPU part of Scope (_PR) like so:

 *     Compiler Version 0x20091112 (537465106)
*/
DefinitionBlock ("/Users/Dave/Desktop/DSDT.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000)
{
   Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

   Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x03)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0820, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x071B, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x0616, 
                   0x02
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

   Scope (_PR.CPU2)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

   Name (_S0, Package (0x04)
   {
       Zero, 
       Zero, 
       Zero, 
       Zero
   })
   Name (SS1, Package (0x04)
// rest of DSDT removed

 

Now if in ioreg you DO NOT see AppleLPC then you will nedd to also patch this decive.

Run lspci Tools and look for ISA device - something like:

00:1f.0 ISA bridge [0601]: Intel Corporation Unknown device [8086:3a16]

 

You can see in red the memory address in this case (and I think most cases.) is 001F0000.

Search your DSDT for 001F0000 to find the device. For my GigaByte MB this is a device PX40. For ease I have renamed the device LPCB - remember to change all instances of PX40 to LPCB.

 

So using zhell's DSDT device id trick you can add any device id that exists in the AppleLPC.kext plist. Probably best to go for an id closest to you actual device id. (in this case MB device id is [8086:3a16] so form the AppleLPC.kext there is device id 3A18 so my Device (LPCB) formerly PX40 now looks like this:

            Device (LPCB)
           {
               Name (_ADR, 0x001F0000)
               Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x18, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               OperationRegion (PREV, PCI_Config, 0x08, One)
               Scope (\)
               {
                   Field (\_SB.PCI0.LPCB.PREV, ByteAcc, NoLock, Preserve)
                   {
                       REV0,   8
                   }
               }

               OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
               Scope (\)
               {
// remainder removed

 

Recomplile the DSDT.dsl to DSDT.aml using IASLME - fingers crossed no errors - and your done!

 

Please NOTE: AppleLPC.kext will give you the 'Automatic restart after power failure' option in power savings. This option needs to be checked for sleep!

This works for me with the model identifyer set to MacPro3,1 and MacPro4,1. If you want to use a none native model identifyer then you'll need to use Master Chiefs Legacy SMC kext that can be found in post #381 here You will need to edit the plist adding your custom model identifyer.

 

You DO NOT need to add dropSSDT=y as boot argument and or change acpi_smc_platformplugin.kext

 

No need for disabler and don't forget to remove the voodoopstate.kext.

This will give vanilla stepping and remove any _cst evaluation errors at boot. and may (if you're lucky.) enable c-states

 

Here is the generic Scope (_PR) GenericScopePR.zip

And here is my DSDT17_11_09.zip for reference.

 

PStateChangerv1.0.3__1_.zip

voodoopstate.v4.zip

Voodoomonitor

 

Further reading:

zhell's DSDT Trick

mackerintel chameleon with DSDT override

fassl DSDT patcher

koalala ACPI patcher

ab__73's chameleon bootloader SSDT and DSDT override

EVO's DSDT - Very useful nOOb DSDT tool !

www.acpi.info/DOWNLOADS/ACPIspec40.pdf

 

Credit to mm67 and Master Chief for the generic Scope (_PR)

bcc9 and hnak for Voodoopstate.kext

and to kdawg, beerkex'd, keeza, THe KiNG ... ALL who've help out on this in one way or another - too many to mention.

 

Enjoy :P

 

D.

P_States_Calculator.zip

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Wow this looks great, a bit complicated but I think it's worth the challenge. I'll try this later.

Great guide FormerlyKnownAs :D

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Yeah, thanks for posting this. I'll see what I can come up with for my "iMac9,1" and post here when I'm done.

 

I thought I read somewhere that Chameleon can load SSDT.aml already..? Maybe I'm confusing things.

 

/EDIT

Here's another way to extract your SSDT under OSX plus loads of other related and useful info:

http://www.insanelym...howtopic=145792

The provided script did not extract all the required tables on my system though.

 

Here's a May 2009 build of iasl for OSX courtesy of zhell.

iasl_20090521.zip

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Thanks for the interest

 

here are a couple of tools for calculating p-states

here

 

Thanks to kdawg for the link.

 

D.

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I thought I read somewhere that Chameleon can load SSDT.aml already..? Maybe I'm confusing things.

 

Do you mean current chameleon 2 or ab__73's chameleon 2 bootloader (which i forgot to link to in the guide :whistle: )

 

To be honest it's wasn't too much work for me to add the SSDT to DSDT but loading SSDT.dat would be really useful if you where struggling to compile.

 

D.

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Which part of the plist do you have to edit to macpro3,1?

 

Hi Cheezmen

 

I spent nearly an hour drafting a PM about this to you last week. You haven't the manners to offer a simple thankyou.

 

Maybe somebody else will answer your question.

 

D.

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Good question... i have the same CPU and _CST error in log of boot system :/

My MoBo have only one SSDT table, look under, what u think about it? can i fix that problem?

 

Try to write some Step By Step to get working system without _CST errors.

 

*
* Intel ACPI Component Architecture
* AML Disassembler version 20090730
*
* Disassembly of ./dsdt.aml, Wed Aug 26 19:28:11 2009
*
*
* Original Table Header:
*	 Signature		"SSDT"
*	 Length		   0x000003AB (939)
*	 Revision		 0x01
*	 Checksum		 0x57
*	 OEM ID		   "PmRef"
*	 OEM Table ID	 "CpuPm"
*	 OEM Revision	 0x00003000 (12288)
*	 Compiler ID	  "INTL"
*	 Compiler Version 0x20040311 (537133841)
*/
DefinitionBlock ("./dsdt.aml", "SSDT", 1, "PmRef", "CpuPm", 0x00003000)
{
External (\_PR_.CPU3, DeviceObj)
External (\_PR_.CPU2, DeviceObj)
External (\_PR_.CPU1, DeviceObj)
External (\_PR_.CPU0, DeviceObj)

Scope (\)
{
	Name (SSDT, Package (0x18)
	{
		"CPU0IST ", 
		0x7FEE6D40, 
		0x0000022A, 
		"CPU1IST ", 
		0x7FEE7200, 
		0x00000152, 
		"CPU0CST ", 
		0x00000000, 
		0xF000E816, 
		"CPU1CST ", 
		0x00000000, 
		0xF000E816, 
		"CPU2IST ", 
		0x7FEE7360, 
		0x00000152, 
		"CPU3IST ", 
		0x7FEE74C0, 
		0x00000152, 
		"CPU2CST ", 
		0x00000000, 
		0xF000E816, 
		"CPU3CST ", 
		0x00000000, 
		0xF000E816
	})
	Name (CFGD, 0x04030302)
	Name (\PDC0, 0x80000000)
	Name (\PDC1, 0x80000000)
	Name (\PDC2, 0x80000000)
	Name (\PDC3, 0x80000000)
}

Scope (\_PR.CPU0)
{
	Name (HI0, 0x00)
	Name (HC0, 0x00)
	Name (TLD0, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP0)
		Store (CAP0, PDC0)
		If (LEqual (TLD0, 0x00))
		{
			If (LEqual (And (PDC0, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02
						)))
					Load (IST0, HI0)
				}

				Store (0x01, TLD0)
			}
		}
	}
}

Scope (\_PR.CPU1)
{
	Name (HI1, 0x00)
	Name (HC1, 0x00)
	Name (TLD1, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP1)
		Store (CAP1, PDC1)
		If (LEqual (TLD1, 0x00))
		{
			If (LEqual (And (PDC1, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05
						)))
					Load (IST1, HI1)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST1, SystemMemory, DerefOf (Index (SSDT, 0x0A)), DerefOf (Index (SSDT, 0x0B
						)))
					Load (CST1, HC1)
				}

				Store (0x01, TLD1)
			}
		}
	}
}

Scope (\_PR.CPU2)
{
	Name (HI2, 0x00)
	Name (HC2, 0x00)
	Name (TLD2, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP2)
		Store (CAP2, PDC2)
		If (LEqual (TLD2, 0x00))
		{
			If (LEqual (And (PDC2, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST2, SystemMemory, DerefOf (Index (SSDT, 0x0D)), DerefOf (Index (SSDT, 0x0E
						)))
					Load (IST2, HI2)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST2, SystemMemory, DerefOf (Index (SSDT, 0x13)), DerefOf (Index (SSDT, 0x14
						)))
					Load (CST2, HC2)
				}

				Store (0x01, TLD2)
			}
		}
	}
}

Scope (\_PR.CPU3)
{
	Name (HI3, 0x00)
	Name (HC3, 0x00)
	Name (TLD3, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP3)
		Store (CAP3, PDC3)
		If (LEqual (TLD3, 0x00))
		{
			If (LEqual (And (PDC3, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST3, SystemMemory, DerefOf (Index (SSDT, 0x10)), DerefOf (Index (SSDT, 0x11
						)))
					Load (IST3, HI3)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST3, SystemMemory, DerefOf (Index (SSDT, 0x16)), DerefOf (Index (SSDT, 0x17
						)))
					Load (CST3, HC3)
				}

				Store (0x01, TLD3)
			}
		}
	}
}
}

 

 

Thx, Arrow :thumbsup_anim:

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Good question... i have the same CPU and _CST error in log of boot system :/

My MoBo have only one SSDT table, look under, what u think about it? can i fix that problem?

 

Hi Majki

 

Which method did you use to extract your SSDT. If you've extracted in OS X some tables may well be missing.

 

D.

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for Q6600 you can use this

 

   Scope (_PR)
{
	Processor (CPU1, 0x01, 0x00000410, 0x06)
	{
		Name (_CST, Package (0x04)
		{
			0x02, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				One, 
				0x14, 
				0x03E8
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000414, // Address
						,)
				}, 

				0x02, 
				0x28, 
				0x02EE
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000415, // Address
						,)
				}, 

				0x03, 
				0x3C, 
				0x01F4
			}
		})
		Name (_PCT, Package (0x02)
		{
			ResourceTemplate ()
			{
				Register (FFixedHW, 
					0x00,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000000, // Address
					,)
			}, 

			ResourceTemplate ()
			{
				Register (FFixedHW, 
					0x00,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000000, // Address
					,)
			}
		})
		Name (_PSS, Package (0x05)
		{
			Package (0x06)
			{
				0x0A6B, 
				0x00015BA8, 
				0xA0, 
				0x0A, 
				0x0A27, 
				0x0A27
			}, 

			Package (0x06)
			{
				0x0960, 
				0x00013498, 
				0xA0, 
				0x0A, 
				0x0924, 
				0x0924
			}, 

			Package (0x06)
			{
				0x0855, 
				0x00011558, 
				0xA0, 
				0x0A, 
				0x0821, 
				0x0821
			}, 

			Package (0x06)
			{
				0x074B, 
				0xF618, 
				0xA0, 
				0x0A, 
				0x071E, 
				0x071E
			}, 

			Package (0x06)
			{
				0x0640, 
				0xD6D8, 
				0xA0, 
				0x0A, 
				0x061B, 
				0x061B
			}
		})
		Method (_PPC, 0, NotSerialized)
		{
			Return (Zero)
		}
	}

 

or use this as well

 

..........
...........
Name (_PSS, Package ()
{
Package (0x06) { 2403, 64260, 32, 32, 0x928, 0x000 },
Package (0x06) { 2136, 55669, 32, 32, 0x826, 0x001 },
Package (0x06) { 1869, 46806, 32, 32, 0x722, 0x002 },
Package (0x06) { 1602, 38488, 32, 32, 0x61E, 0x003 }
})
}

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Hi Majki

 

Which method did you use to extract your SSDT. If you've extracted in OS X some tables may well be missing.

 

D.

 

I dont think so coz its old mobo P31 chipset :) and yes i extracted it under osx with console script.

 

 

for Q6600 you can use this

 

   Scope (_PR)
{
	Processor (CPU1, 0x01, 0x00000410, 0x06)
	{
		Name (_CST, Package (0x04)
		{
			0x02, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				One, 
				0x14, 
				0x03E8
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000414, // Address
						,)
				}, 

				0x02, 
				0x28, 
				0x02EE
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000415, // Address
						,)
				}, 

				0x03, 
				0x3C, 
				0x01F4
			}
		})
		Name (_PCT, Package (0x02)
		{
			ResourceTemplate ()
			{
				Register (FFixedHW, 
					0x00,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000000, // Address
					,)
			}, 

			ResourceTemplate ()
			{
				Register (FFixedHW, 
					0x00,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000000, // Address
					,)
			}
		})
		Name (_PSS, Package (0x05)
		{
			Package (0x06)
			{
				0x0A6B, 
				0x00015BA8, 
				0xA0, 
				0x0A, 
				0x0A27, 
				0x0A27
			}, 

			Package (0x06)
			{
				0x0960, 
				0x00013498, 
				0xA0, 
				0x0A, 
				0x0924, 
				0x0924
			}, 

			Package (0x06)
			{
				0x0855, 
				0x00011558, 
				0xA0, 
				0x0A, 
				0x0821, 
				0x0821
			}, 

			Package (0x06)
			{
				0x074B, 
				0xF618, 
				0xA0, 
				0x0A, 
				0x071E, 
				0x071E
			}, 

			Package (0x06)
			{
				0x0640, 
				0xD6D8, 
				0xA0, 
				0x0A, 
				0x061B, 
				0x061B
			}
		})
		Method (_PPC, 0, NotSerialized)
		{
			Return (Zero)
		}
	}

 

or use this as well

 

..........
...........
Name (_PSS, Package ()
{
Package (0x06) { 2403, 64260, 32, 32, 0x928, 0x000 },
Package (0x06) { 2136, 55669, 32, 32, 0x826, 0x001 },
Package (0x06) { 1869, 46806, 32, 32, 0x722, 0x002 },
Package (0x06) { 1602, 38488, 32, 32, 0x61E, 0x003 }
})
}

 

k, all methods made error when compiling, look under ;> Any ideas?

 

SSDT.txt   255:	 Method (_WAK, 1, NotSerialized)
Warning  1080 -				^ Reserved method must return a value (_WAK)

SSDT.txt  4606: Scope
Error	4095 -	 ^ syntax error, unexpected PARSEOP_SCOPE, expecting $end

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I dont think so coz its old mobo P31 chipset :) and yes i extracted it under osx with console script.

 

 

 

 

k, all methods made error when compiling, look under ;> Any ideas?

 

SSDT.txt   255:	 Method (_WAK, 1, NotSerialized)
Warning  1080 -				^ Reserved method must return a value (_WAK)

SSDT.txt  4606: Scope
Error	4095 -	 ^ syntax error, unexpected PARSEOP_SCOPE, expecting $end

 

Hi Majki

 

Firstly I only get the one SSDT table when I run ab__73's script under OS X, the same CPUPM table you get. I have 4 other tables CPUIST when extracted in Linux or Windows.

 

Secondly where have you added the code roisoft has posted in your DSDT? This needs to go under the Scope _PR of DSDT and you will need an entry for each CPU core.

 

D.

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Hello,

 

I used my own SSDT dumps (SSDT, CPUxCST and CPUxIST) from Linux and integrated CST and PST tables into the DSDT, booting with DropSSDT and AICPUPM getting initialized but still getting this error. (not getting evaluation failed)

ACPI_SMC_PlatformPlugin::registerLPCDriver - WARNING - LPC device initialization failed: C-state power management not initialized

 

Do I still need to edit the ACPI_SMC_PlatformPlugin Info.plist? Can you be more clear on which part needs to be edited please?

 

Here is the DSDT and SSDT...

 

Thanks.

 

M1530_DSDT.dsl.zip

 

Scope (\)
{
Name (SSDT, Package (0x0C)
{
	"CPU0IST ", 
	0xDFE72CB4, 
	0x02C8, 
	"CPU1IST ", 
	0xDFE72F7C, 
	0xC4, 
	"CPU0CST ", 
	0xDFE7264A, 
	0x05E5, 
	"CPU1CST ", 
	0xDFE72C2F, 
	0x85
})
Name (CFGD, 0x013369F7)
Name (PDC0, 0x80000000)
Name (PDC1, 0x80000000)
Name (SDTL, Zero)
}

Scope (_PR.CPU0)
{
Name (HI0, 0x00)
Name (HC0, 0x00)
Method (_PDC, 1, NotSerialized)
{
CreateDWordField (Arg0, 0x00, REVS)
CreateDWordField (Arg0, 0x04, SIZE)
Store (SizeOf (Arg0), Local0)
Store (Subtract (Local0, 0x08), Local1)
CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
Name (STS0, Buffer (0x04)
{
	0x00, 0x00, 0x00, 0x00
})
Concatenate (STS0, TEMP, Local2)
_OSC (Buffer (0x10)
	{
		/* 0000 */	0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47, 
		/* 0008 */	0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
	}, REVS, SIZE, Local2)
}

Method (_OSC, 4, NotSerialized)
{
CreateDWordField (Arg3, 0x00, STS0)
CreateDWordField (Arg3, 0x04, CAP0)
CreateDWordField (Arg0, 0x00, IID0)
CreateDWordField (Arg0, 0x04, IID1)
CreateDWordField (Arg0, 0x08, IID2)
CreateDWordField (Arg0, 0x0C, IID3)
Name (UID0, Buffer (0x10)
{
	/* 0000 */	0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47, 
	/* 0008 */	0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
})
CreateDWordField (UID0, 0x00, EID0)
CreateDWordField (UID0, 0x04, EID1)
CreateDWordField (UID0, 0x08, EID2)
CreateDWordField (UID0, 0x0C, EID3)
If (LNot (LAnd (LAnd (LEqual (IID0, EID0), LEqual (IID1, EID1)), 
	LAnd (LEqual (IID2, EID2), LEqual (IID3, EID3)))))
{
	Store (0x06, STS0)
	Return (Arg3)
}

If (LNotEqual (Arg1, 0x01))
{
	Store (0x0A, STS0)
	Return (Arg3)
}

Or (And (PDC0, 0x7FFFFFFF), CAP0, PDC0)
If (And (CFGD, 0x01))
{
	If (LAnd (LAnd (And (CFGD, 0x01000000), LEqual (And (PDC0, 
		0x09), 0x09)), LNot (And (SDTL, 0x01))))
	{
		Or (SDTL, 0x01, SDTL)
		OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02
			)))
		Load (IST0, HI0)
	}
}

If (And (CFGD, 0xF0))
{
	If (LAnd (LAnd (And (CFGD, 0x01000000), And (PDC0, 0x18
		)), LNot (And (SDTL, 0x02))))
	{
		Or (SDTL, 0x02, SDTL)
		OperationRegion (CST0, SystemMemory, DerefOf (Index (SSDT, 0x07)), DerefOf (Index (SSDT, 0x08
			)))
		Load (CST0, HC0)
	}
}

Return (Arg3)
}
}

Scope (_PR.CPU1)
{
Name (HI1, 0x00)
Name (HC1, 0x00)
Method (_PDC, 1, NotSerialized)
{
	CreateDWordField (Arg0, 0x00, REVS)
	CreateDWordField (Arg0, 0x04, SIZE)
	Store (SizeOf (Arg0), Local0)
	Store (Subtract (Local0, 0x08), Local1)
	CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
	Name (STS1, Buffer (0x04)
	{
		0x00, 0x00, 0x00, 0x00
	})
	Concatenate (STS1, TEMP, Local2)
	_OSC (Buffer (0x10)
		{
			/* 0000 */	0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47, 
			/* 0008 */	0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
		}, REVS, SIZE, Local2)
}

Method (_OSC, 4, NotSerialized)
{
	CreateDWordField (Arg3, 0x00, STS1)
	CreateDWordField (Arg3, 0x04, CAP1)
	CreateDWordField (Arg0, 0x00, IID0)
	CreateDWordField (Arg0, 0x04, IID1)
	CreateDWordField (Arg0, 0x08, IID2)
	CreateDWordField (Arg0, 0x0C, IID3)
	Name (UID1, Buffer (0x10)
	{
		/* 0000 */	0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47, 
		/* 0008 */	0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
	})
	CreateDWordField (UID1, 0x00, EID0)
	CreateDWordField (UID1, 0x04, EID1)
	CreateDWordField (UID1, 0x08, EID2)
	CreateDWordField (UID1, 0x0C, EID3)
	If (LNot (LAnd (LAnd (LEqual (IID0, EID0), LEqual (IID1, EID1)), 
		LAnd (LEqual (IID2, EID2), LEqual (IID3, EID3)))))
	{
		Store (0x06, STS1)
		Return (Arg3)
	}

	If (LNotEqual (Arg1, 0x01))
	{
		Store (0x0A, STS1)
		Return (Arg3)
	}

	Or (And (PDC1, 0x7FFFFFFF), CAP1, PDC1)
	If (And (CFGD, 0x01))
	{
		If (LAnd (LAnd (And (CFGD, 0x01000000), LEqual (And (PDC1, 
			0x09), 0x09)), LNot (And (SDTL, 0x10))))
		{
			Or (SDTL, 0x10, SDTL)
			OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05
				)))
			Load (IST1, HI1)
		}
	}

	If (And (CFGD, 0xF0))
	{
		If (LAnd (LAnd (And (CFGD, 0x01000000), And (PDC1, 0x18
			)), LNot (And (SDTL, 0x20))))
		{
			Or (SDTL, 0x20, SDTL)
			OperationRegion (CST1, SystemMemory, DerefOf (Index (SSDT, 0x0A)), DerefOf (Index (SSDT, 0x0B
				)))
			Load (CST1, HC1)
		}
	}

	Return (Arg3)
}
}

Scope (_PR.CPU0)
{
Method (_CST, 0, NotSerialized)
{
	If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
		))))
	{
		Return (Package (0x02)
		{
			0x01, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				0x01, 
				0x9D, 
				0x03E8
			}
		})
	}

	If (LAnd (And (CFGD, 0x00200000), And (PDC0, 0x0200)))
	{
		If (And (CFGD, 0x0200))
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000010, // Address
							0x01,			   // Access Size
							)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000050, // Address
							0x03,			   // Access Size
							)
					}, 

					0x03, 
					0xA2, 
					0x64
				}
			})
		}

		If (And (CFGD, 0x80))
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000010, // Address
							0x01,			   // Access Size
							)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000030, // Address
							0x03,			   // Access Size
							)
					}, 

					0x03, 
					0x39, 
					0x64
				}
			})
		}

		If (And (CFGD, 0x40))
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000010, // Address
							0x01,			   // Access Size
							)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000020, // Address
							0x03,			   // Access Size
							)
					}, 

					0x03, 
					0x11, 
					0xFA
				}
			})
		}

		If (And (CFGD, 0x20))
		{
			Return (Package (0x03)
			{
				0x02, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000010, // Address
							0x01,			   // Access Size
							)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}
			})
		}

		Return (Package (0x02)
		{
			0x01, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x01,			   // Bit Width
						0x02,			   // Bit Offset
						0x0000000000000000, // Address
						0x01,			   // Access Size
						)
				}, 

				0x01, 
				0x01, 
				0x03E8
			}
		})
	}

	If (LAnd (And (CFGD, 0x00200000), And (PDC0, 0x0100)))
	{
		If (And (CFGD, 0x0200))
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (SystemIO, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000001014, // Address
							,)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (SystemIO, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000001018, // Address
							,)
					}, 

					0x03, 
					0xA2, 
					0x64
				}
			})
		}

		If (And (CFGD, 0x80))
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (SystemIO, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000001014, // Address
							,)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (SystemIO, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000001016, // Address
							,)
					}, 

					0x03, 
					0x39, 
					0x64
				}
			})
		}

		If (And (CFGD, 0x40))
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (SystemIO, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000001014, // Address
							,)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (SystemIO, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000001015, // Address
							,)
					}, 

					0x03, 
					0x11, 
					0xFA
				}
			})
		}

		If (And (CFGD, 0x20))
		{
			Return (Package (0x03)
			{
				0x02, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							0x01,			   // Access Size
							)
					}, 

					0x01, 
					0x01, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (SystemIO, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000001014, // Address
							,)
					}, 

					0x02, 
					0x01, 
					0x01F4
				}
			})
		}

		Return (Package (0x02)
		{
			0x01, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x01,			   // Bit Width
						0x02,			   // Bit Offset
						0x0000000000000000, // Address
						0x01,			   // Access Size
						)
				}, 

				0x01, 
				0x01, 
				0x03E8
			}
		})
	}

	If (And (CFGD, 0x0200))
	{
		Return (Package (0x04)
		{
			0x03, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				0x01, 
				0x01, 
				0x03E8
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000001014, // Address
						,)
				}, 

				0x02, 
				0x01, 
				0x01F4
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000001018, // Address
						,)
				}, 

				0x03, 
				0xA2, 
				0x64
			}
		})
	}

	If (And (CFGD, 0x80))
	{
		Return (Package (0x04)
		{
			0x03, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				0x01, 
				0x01, 
				0x03E8
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000001014, // Address
						,)
				}, 

				0x02, 
				0x01, 
				0x01F4
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000001016, // Address
						,)
				}, 

				0x03, 
				0x39, 
				0x64
			}
		})
	}

	If (And (CFGD, 0x40))
	{
		Return (Package (0x04)
		{
			0x03, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				0x01, 
				0x01, 
				0x03E8
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000001014, // Address
						,)
				}, 

				0x02, 
				0x01, 
				0x01F4
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000001015, // Address
						,)
				}, 

				0x03, 
				0x11, 
				0xFA
			}
		})
	}

	If (And (CFGD, 0x20))
	{
		Return (Package (0x03)
		{
			0x02, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				0x01, 
				0x01, 
				0x03E8
			}, 

			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (SystemIO, 
						0x08,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000001014, // Address
						,)
				}, 

				0x02, 
				0x01, 
				0x01F4
			}
		})
	}

	Return (Package (0x02)
	{
		0x01, 
		Package (0x04)
		{
			ResourceTemplate ()
			{
				Register (FFixedHW, 
					0x00,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000000, // Address
					,)
			}, 

			0x01, 
			0x01, 
			0x03E8
		}
	})
}

Method (_PPC, 0, NotSerialized)
{
	Store (SMI (0xAD, 0x00), Local0)
	Return (Local0)
}

Method (_PCT, 0, NotSerialized)
{
	If (LAnd (And (CFGD, 0x01), And (PDC0, 0x01)))
	{
		Return (Package (0x02)
		{
			ResourceTemplate ()
			{
				Register (FFixedHW, 
					0x00,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000000, // Address
					,)
			}, 

			ResourceTemplate ()
			{
				Register (FFixedHW, 
					0x00,			   // Bit Width
					0x00,			   // Bit Offset
					0x0000000000000000, // Address
					,)
			}
		})
	}

	Return (Package (0x02)
	{
		ResourceTemplate ()
		{
			Register (SystemIO, 
				0x10,			   // Bit Width
				0x00,			   // Bit Offset
				0x00000000000000B2, // Address
				,)
		}, 

		ResourceTemplate ()
		{
			Register (SystemIO, 
				0x08,			   // Bit Width
				0x00,			   // Bit Offset
				0x00000000000000B3, // Address
				,)
		}
	})
}

Method (XPSS, 0, NotSerialized)
{
	If (And (PDC0, 0x01))
	{
		Return (_PSS)
	}

	Return (SPSS)
}

Name (SPSS, Package (0x06)
{
	Package (0x06)
	{
		0x00000961, 
		0x00007D00, 
		0x0000006E, 
		0x0000000A, 
		0x00000083, 
		0x00000000
	}, 

	Package (0x06)
	{
		0x00000960, 
		0x00007918, 
		0x0000006E, 
		0x0000000A, 
		0x00000183, 
		0x00000001
	}, 

	Package (0x06)
	{
		0x000007D0, 
		0x000061A8, 
		0x0000006E, 
		0x0000000A, 
		0x00000283, 
		0x00000002
	}, 

	Package (0x06)
	{
		0x00000640, 
		0x00004A38, 
		0x0000006E, 
		0x0000000A, 
		0x00000383, 
		0x00000003
	}, 

	Package (0x06)
	{
		0x000004B0, 
		0x000032C8, 
		0x0000006E, 
		0x0000000A, 
		0x00000483, 
		0x00000004
	}, 

	Package (0x06)
	{
		0x00000320, 
		0x00002710, 
		0x0000006E, 
		0x0000000A, 
		0x00000583, 
		0x00000005
	}
})
Name (_PSS, Package (0x06)
{
	Package (0x06)
	{
		0x00000961, 
		0x00007D00, 
		0x0000000A, 
		0x0000000A, 
		0x00000D28, 
		0x00000D28
	}, 

	Package (0x06)
	{
		0x00000960, 
		0x00007918, 
		0x0000000A, 
		0x0000000A, 
		0x00000C22, 
		0x00000C22
	}, 

	Package (0x06)
	{
		0x000007D0, 
		0x000061A8, 
		0x0000000A, 
		0x0000000A, 
		0x00000A1F, 
		0x00000A1F
	}, 

	Package (0x06)
	{
		0x00000640, 
		0x00004A38, 
		0x0000000A, 
		0x0000000A, 
		0x0000081B, 
		0x0000081B
	}, 

	Package (0x06)
	{
		0x000004B0, 
		0x000032C8, 
		0x0000000A, 
		0x0000000A, 
		0x00000617, 
		0x00000617
	}, 

	Package (0x06)
	{
		0x00000320, 
		0x00002710, 
		0x0000000A, 
		0x0000000A, 
		0x00008813, 
		0x00008813
	}
})

Method (_PSD, 0, NotSerialized)
{
	If (And (CFGD, 0x01000000))
	{
		If (And (PDC0, 0x0800))
		{
			Return (Package (0x01)
			{
				Package (0x05)
				{
					0x05, 
					0x00, 
					0x00, 
					0xFE, 
					0x02
				}
			})
		}

		Return (Package (0x01)
		{
			Package (0x05)
			{
				0x05, 
				0x00, 
				0x00, 
				0xFC, 
				0x02
			}
		})
	}

	Return (Package (0x01)
	{
		Package (0x05)
		{
			0x05, 
			0x00, 
			0x00, 
			0xFC, 
			0x01
		}
	})
}
}

Scope (_PR.CPU1)
{
Method (_CST, 0, NotSerialized)
{
	If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC1, 0x10
		))))
	{
		Return (Package (0x02)
		{
			0x01, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x00,			   // Bit Width
						0x00,			   // Bit Offset
						0x0000000000000000, // Address
						,)
				}, 

				0x01, 
				0x9D, 
				0x03E8
			}
		})
	}

	Return (\_PR.CPU0._CST)
}

Method (_PPC, 0, NotSerialized)
{
	Store (SMI (0xAD, 0x00), Local0)
	Return (Local0)
}

Method (_PCT, 0, NotSerialized)
{
	Return (Package (0x02)
	{
		ResourceTemplate ()
		{
			Register (FFixedHW, 
				0x00,			   // Bit Width
				0x00,			   // Bit Offset
				0x0000000000000000, // Address
				,)
		}, 

		ResourceTemplate ()
		{
			Register (FFixedHW, 
				0x00,			   // Bit Width
				0x00,			   // Bit Offset
				0x0000000000000000, // Address
				,)
		}
	})
}

Method (_PSS, 0, NotSerialized)
{
	Return (\_PR.CPU0._PSS)
}

Method (_PSD, 0, NotSerialized)
{
	If (And (PDC1, 0x0800))
	{
		Return (Package (0x01)
		{
			Package (0x05)
			{
				0x05, 
				0x00, 
				0x00, 
				0xFE, 
				0x02
			}
		})
	}

	Return (Package (0x01)
	{
		Package (0x05)
		{
			0x05, 
			0x00, 
			0x00, 
			0xFC, 
			0x02
		}
	})
}
}

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Hi Chrysaor

 

I don't have a Mac to hand at the mo' so please excuse if this is a tad vague

 

Open the info.plist of ACPI_SMC kext that can be found in System/Library/Extensions/IOPlatformPluginFamily.kext/Contents/PlugIns/ACPI_SMC_PlatformPlugin.kext

 

In the plist under "CStateDemotionDict" change the model to whichever Mac Model you have taken the c-states from ie MacPro3,1

 

Now as you have used your own _cst tables I'm not sure what you should set this as.(maybe somebody else can help?)

Try setting to the same model you have set in SMBIOS .

 

~~EDIT~~ also you may need to do some work with voodoo kernel to decipher correct c-state memory address see post #71 here

 

D.

 

 

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It seems i got vanilla Speedstepping working (all needed infos where gathered by reading SSDT Tables). How can i check at which State the CPU is running under Snowleopard? MSR Tools don't work anymore, CPU-X always shows max State, which i can't believe as Temp sank by around 4 Degrees C.

 

Thanks!

 

Another thing: I guess C-State Control is possible, but where do i get the needed Infos for my C2D 6750? The SSDT Tables don't provide _CST Methods :(

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It seems i got vanilla Speedstepping working (all needed infos where gathered by reading SSDT Tables). How can i check at which State the CPU is running under Snowleopard? MSR Tools don't work anymore, CPU-X always shows max State, which i can't believe as Temp sank by around 4 Degrees C.

 

Thanks!

 

Another thing: I guess C-State Control is possible, but where do i get the needed Infos for my C2D 6750? The SSDT Tables don't provide _CST Methods :(

 

Hi ApexDE

 

I'm not tuned into SL just yet but try CPU-i, give's me the best results in Leo.

here's the link

 

I presume you have found a SSDT table that looks similar to this:

 

        Scope (\)
    {
        Name (SSDT, Package (0x18)
        {
            "CPU0IST ", 
            0xDFEE7F00, 
            0x022A, 
            "CPU1IST ", 
            0xDFEE83C0, 
            0x0152, 
            "CPU0CST ", 
            Zero, 
            0xF000E816, 
            "CPU1CST ", 
            Zero, 
            0xF000E816, 
            "CPU2IST ", 
            0xDFEE8520, 
            0x0152, 
            "CPU3IST ", 
            0xDFEE8680, 
            0x0152, 
            "CPU2CST ", 
            Zero, 
            0xF000E816, 
            "CPU3CST ", 
            Zero, 
            0xF000E816
        })


 

If you have 0x00000000 listed as the memory address for _CST then I believe there are no _cst tables.

Let us know how it goes with SL.

 

Cheers

D.

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Thanks! CPU-I is working and showing that Speedstepping is working :) CPU-I is showing the lowest p-state under "status" (x6 multiplier). Strange thing is, it doesn't update once i have high cpu load. Is that normal? It should be showing x7 or even x8 once CPU gets hit.

 

It seems my C-State memory adresses are in fact missing in the SSDT:

		Name (SSDT, Package (0x18)
	{
		"CPU0IST ", 
		0xDFEE8000, 
		0x0000022A, 
		"CPU1IST ", 
		0xDFEE84C0, 
		0x00000152, 
		"CPU0CST ", 
		0x00000000, 
		0xF000E816, 
		"CPU1CST ", 
		0x00000000, 
		0xF000E816, 
		"CPU2IST ", 
		0x00000000, 
		0xF000E816, 
		"CPU3IST ", 
		0x00000000, 
		0xF000E816, 
		"CPU2CST ", 
		0x00000000, 
		0xF000E816, 
		"CPU3CST ", 
		0x00000000, 
		0xF000E816
	})

 

 

There must be a way to find out the correct addresses if even Windows Vista can use them ;)

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Thanks! CPU-I is working and showing that Speedstepping is working ;) CPU-I is showing the lowest p-state under "status" (x6 multiplier). Strange thing is, it doesn't update once i have high cpu load. Is that normal? It should be showing x7 or even x8 once CPU gets hit.

 

It seems my C-State memory adresses are in fact missing in the SSDT:

 

 

There must be a way to find out the correct addresses if even Windows Vista can use them :mellow:

 

No that is not normal with CPU-i.

Is this method proved to be working for you under Leopard - i.e does CPU-i show the multi increase under load?

 

Do you notice a change in your X-bench score under Snow Leo with and without Vanilla stepping?

 

Have you calculated correctly your Fid and Vid values for your CPU and added to DSDT - this is very important !

 

I don't think the c-states exist but if you find a method that extracts the tables please share :)

 

D.

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I don't have Leopard anymore... Odd thing is, there are only 2 P-States in my SSDT, CPU-I reports three. I guess these tools need to be adapted to Snow Leopard.

Do you know other Tools than CPU-I, CPU-X or MSR which report the ACTUAL CPU frequency?

 

EDIT: I tried to recompile CPU-I under SL, but it is not possible ATM. I guess SL has too many changes.

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I don't have Leopard anymore... Odd thing is, there are only 2 P-States in my SSDT, CPU-I reports three. I guess these tools need to be adapted to Snow Leopard.

Do you know other Tools than CPU-I, CPU-X or MSR which report the ACTUAL CPU frequency?

 

I think you have the sum total of CPU tools (bar coolbook but that didn't work at all for me.)

 

Have you edited the PSS values found in your SSDT table - This is where you need to do some research!

 

You need to find how many p-states your CPU supports, you then have to calculate or work out by trail and error suitable vCore vlaues for each multi setting. This way you can then calculate you fid and vid values. These values then need to be converted into Hex and added to the tables

 

Read my first post - read the links in the post!

 

D.

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You are right. I had two Sets of PSS Tables. One named SPSS and another named NPSS. One had the right Values in the last two lines, the other one didn't. The Two sets NPSS and SPSS differ in busmaster latency.

After adapting the last two lines, CPU-I is showing frequency switching depending on CPU load.

 

Thanks, dumb error. But after reading so many assembler code, your eyes fool you :->

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You are right. I had two Sets of PSS Tables. One named SPSS and another named NPSS. One had the right Values in the last two lines, the other one didn't. The Two sets NPSS and SPSS differ in busmaster latency.

After adapting the last two lines, CPU-I is showing frequency switching depending on CPU load.

 

Thanks, dumb error. But after reading so many assembler code, your eyes fool you :->

 

Tell me about it!

And yes the Npss and SPSS got me at first too.

 

Glad you got it sorted ;)

D

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Yes, vanilla speedstepping at last :)

 

What about that Windows Tool Everest? Maybe we can get the CST Memory Values using that Tool? I'll try that out later this evening.

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Yes, vanilla speedstepping at last :)

 

What about that Windows Tool Everest? Maybe we can get the CST Memory Values using that Tool? I'll try that out later this evening.

 

I get the same tables with Everest as I do with Ubuntu Live and acpidump but let me know how you go.

 

Tip - If you are going to add more p-states remember to increase the 'package' value accordingly.

0x03, ...0x04 etc etc ..

 

D.

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