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DSDT - Vanilla Speedstep - Generic Scope (_PR)


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#141
Superhai

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There are a few things about C-states that makes issues. Crackled sound is an indication that you are in fact putting the CPU in a lower powered C-state (usually from C2 and lower), as the TSC stops counting. You need HPET or some other timing to be precise, and be sure that TSC is updated when returning to C0.

You also need to make the difference between SystemIO and FFixedHW (and other values).
SystemIO
Is related to the x86 I/O ports, and are defined by your chipset setup (which means that different m/b will have different values)
FFixedHW
That is some fixed hardware, for x86 CPU's it is often used for MSR's. And as you have seen for P-states, the MSR used are the 0x0198 (IA32_PERF_STATUS) and 0x0199 (IA32_PERF_CTL) (on AMD other MSR's are used)
SystemMemory
This is the system memory.
EmbeddedControl, SMBus, PCI_Config
Other devices that OSPM will communicate with. And very dependant on your particular m/b.


I tried changing CPU1 to CPU0 earlier today but then I couldn't boot, it halted with at a CPU error message right at the beginning.
I didn't try changing the rest though, I will try later - do you know what the 410/810 value means?


If you change CPU name you have to do it in every instance in your ACPI tables. port 0x410 or 0x810 is the cpu I/O port block and the number after is its length (so "0x410, 6" means a block of 6 ports from 0x410 to 0x416)

#142
ivik

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Thanks for looking, it is much appreciated. My ears aren't bleeding from the skipping sound, it's my brain turning to mush from looking at ACPI tables and reading, reading and reading..



It's a Core 2 Duo E8500. The CPUs in Scope (\PR) were always like this (except I changed P00x to CPUx):

Scope (_PR)
{
Processor (CPU1, 0x01, 0x00000810, 0x06) {}
Processor (CPU2, 0x02, 0x00000000, 0x00) {}
Processor (CPU3, 0x03, 0x00000000, 0x00) {}
Processor (CPU4, 0x04, 0x00000000, 0x00) {}
}

In the DSDT tables I've looked at from real Macs both cores are declared in Scope (_PR) with 410 and 0x06.

Should I do the same thing FormerlyKnownAs did (cp'd from his DSDT in the first post):

Scope (_PR)
{
Processor (CPU0, 0x00, 0x00000410, 0x06) {}
Processor (CPU1, 0x01, 0x00000410, 0x06) {}
Processor (CPU2, 0x02, 0x00000410, 0x06) {}
Processor (CPU3, 0x03, 0x00000410, 0x06) {}

I tried changing CPU1 to CPU0 earlier today but then I couldn't boot, it halted with at a CPU error message right at the beginning.
I didn't try changing the rest though, I will try later - do you know what the 410/810 value means?

The "Name (NPCP, 0x00000001)" is already in the DSDT I posted but the compiler has changed 0x00000001 to "One".
Should changed it to 0x00000002? Or what did you mean...I'm just barely on my way to enlightenment with a melting brain so this stuff is difficult to follow. :P
When the DSDT was loaded both cores were showing in IORegistryExplorer (that is to say, the second one had an "AppleACPICPU" attached as usual). I didn't check Activity Monitor at the time.
I'm using iMac9,1 as model identifier - does that mean that I have to use CStates from an iMac9,1?

Try this dsdt and drop ssdt tables.

Attached Files

  • Attached File  dsdt.txt   329.51KB   102 downloads


#143
Master Chief

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Thanks for looking, it is much appreciated. My ears aren't bleeding from the skipping sound, it's my brain turning to mush from looking at ACPI tables and reading, reading and reading.

No problem. I hear you. And yes it does indeed require a lot of reading, but that's just a fun part of hacking isn't it ;)

It's a Core 2 Duo E8500. The CPUs in Scope (\PR) were always like this (except I changed P00x to CPUx):

Scope (_PR)
{
Processor (CPU1, 0x01, 0x00000810, 0x06) {}
Processor (CPU2, 0x02, 0x00000000, 0x00) {}
Processor (CPU3, 0x03, 0x00000000, 0x00) {}
Processor (CPU4, 0x04, 0x00000000, 0x00) {}
}

Which is fine. And the way these processor blocks are declared is 100% valid. The question now is if this will work with the ACPI_SMC_PlatformPlugin.kext My gut feeling might be wrong, but it says nope, since all DSDT files I have seen thus far declare it like this:
Scope (_PR)
	{
		Processor (CPU1, 0x01, 0x00000810, 0x06) {}
		Processor (CPU2, 0x02, 0x00000810, 0x06) {}
	}
Note that I copied the PBlockAddres from your first and only (boot) CPU which is the correct address for your MB, otherwise it won't even boot (hangs at Apple logo).

In the DSDT tables I've looked at from real Macs both cores are declared in Scope (_PR) with 410 and 0x06.

Should I do the same thing FormerlyKnownAs did (cp'd from his DSDT in the first post):

Scope (_PR)
{
Processor (CPU0, 0x00, 0x00000410, 0x06) {}
Processor (CPU1, 0x01, 0x00000410, 0x06) {}
Processor (CPU2, 0x02, 0x00000410, 0x06) {}
Processor (CPU3, 0x03, 0x00000410, 0x06) {}

No. You must use the proper PBlockAddress. Don't use anything else.

I tried changing CPU1 to CPU0 earlier today but then I couldn't boot, it halted with at a CPU error message right at the beginning.

The first argument of a Processor declaration opens a name scope with that name, so like Superhai already said: You have to change it everywhere when you change it. There is however no need for it.

I didn't try changing the rest though, I will try later - do you know what the 410/810 value means?

From the ACPI specification:

"Syntax
Processor (ProcessorName, ProcessorID, PBlockAddress, PblockLength)
{ObjectList}
Arguments
Declares a named processor object named ProcessorName. Processor opens a name scope. Each processor
is required to have a unique ProcessorID value that is unique from any other ProcessorID value.

For each processor in the system, the ACPI BIOS declares one processor object in the namespace anywhere
within the \_SB scope. For compatibility with operating systems implementing ACPI 1.0, the processor
object may also be declared under the \_PR scope. An ACPI-compatible namespace may define Processor
objects in either the \_SB or \_PR scope but not both.

PBlockAddress provides the system I/O address for the processors register block. Each processor can
supply a different such address. PBlockLength is the length of the processor register block, in bytes and is
either 0 (for no P_BLK) or 6. With one exception, all processors are required to have the same
PBlockLength. The exception is that the boot processor can have a non-zero PBlockLength when all other
processors have a zero PBlockLength. It is valid for every processor to have a PBlockLength of 0.
"

The "Name (NPCP, 0x00000001)" is already in the DSDT I posted but the compiler has changed 0x00000001 to "One".
Should changed it to 0x00000002? Or what did you mean...I'm just barely on my way to enlightenment with a melting brain so this stuff is difficult to follow. :wacko:

Yes, change it to 0x02 when you've changed the Processor declarations. And hang in.... we're slowly getting somewhere.

When the DSDT was loaded both cores were showing in IORegistryExplorer (that is to say, the second one had an "AppleACPICPU" attached as usual). I didn't check Activity Monitor at the time.

Just AppleACPICPU? That would mean that P-State stepping isn't even working for you. Is it?

For you info: I also have ACPI_SMC_PlatformPlugin, AGPMEnabler and AGPMController (See attachments: BTW how do I move attachments to this spot?)

I'm using iMac9,1 as model identifier - does that mean that I have to use CStates from an iMac9,1?

I don't think so, but I thought of having seen evidence in the ACPI_SMC_PlatformPlugin.kext (Info.plist) that (certain) iMac's have limited PM capabilities.

Attached Files



#144
Master Chief

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O.k, I'm attaching the following files

1. A zip with the SSDTs I extracted from ubuntu.
2. A zip with a few DSDTs
a. The DSDT before i started playing with HPET and SSDTs
b. Modified DSDTs i've tried with stages of just merging the SSDTs,
trying to fix the SPSS, and trying to fix the register addresses to 199 and 198.

I really thank you for having the time to look at my files and help.

Thanks in advance,
Jonathan

The original files appear to be fine. You might want to add a change _PSS object – one with more P-States – but that's apparently all you need.

1) Did you enable C States in your BIOS? And if that's a yes, then which one(s)? Edit: Already answered in post #125
2) What model do you see in System Profiler? Edit: Already answered in post #135
3) Can you please add a FACP dump for me?
4) Open IORegistryExplorer (part of Xcode) and check for the items in my two screen shots, do you see the same items there?

n.b. If you don't see the items listed in my screen shots (in post #143) then your changes in Info.plist aren't working.

p.s. Feel free to attach your modified Info.plist to see if I can spot the error ;)

#145
Beerkex'd

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Master Chief, thanks, I will try what you said and see what happens.

I do have the ACPI_SMC_PlatformPlugin, AGPMEnabler and AGPMController as well but they only appear under CPU1. CPU2 only has the AppleACPICPU. I don't, however have "CSTInfo" like you..hmm

I have P-state switching and proper shutdown when using VoodooPowerMini.kext (thanks Superhai). Without VoodooPower it runs at full throttle and doesn't shut down completely (the classic "lights go off but CPU fan keeps running").

Try this dsdt and drop ssdt tables.


Did you make it? What CPU is installed on the P5Q-E it was taken from, and does AppleLPC.kext load on it?
You have to change a device ID in the kext, or you can patch it in the DSDT (excerpt from mine below).
I thought AppleLPC.kext needed to be loaded for C-state switching to work at all?

Device (LPCB)
			{
				Name (_ADR, 0x001F0000)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", 
							Buffer (0x04)
							{
								0x18, 0x3A, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}

				Device (IELK)
				{ (....)
The main difference I can see from your method and mine is that you inserted the whole thing inside Scope _PR instead of at the end of the DSDT.
I copied your entire Scope _PR and also your HPET device to my DSDT (it is very different from mine).

I don't get the evaluation errors on boot (with or without DropSSDT=y) and there is no break-up in the sound, but there is no state changing either, it's running at full throttle. CPU temps went up by 4-5 degrees Celsius.

Your HPET (SBRG changed to LPCB for AppleLPC.kext):
Device (HPET)
				{
					Name (_HID, EisaId ("PNP0103"))
					Name (CRS, ResourceTemplate ()
					{
						IRQNoFlags ()
							{0}
						IRQNoFlags ()
							{8}
						Memory32Fixed (ReadOnly,
							0xFED00000,		 // Address Base
							0x00000400,		 // Address Length
							_Y0D)
					})
					OperationRegion (^LPCR, SystemMemory, 0xFED1F404, 0x04)
					Field (LPCR, AnyAcc, NoLock, Preserve)
					{
						HPTS,   2, 
							,   5, 
						HPTE,   1, 
								Offset (0x04)
					}

					Method (_STA, 0, NotSerialized)
					{
						If (LEqual (OSFL (), Zero))
						{
							If (HPTE)
							{
								Return (0x0F)
							}
						}
						Else
						{
							If (HPTE)
							{
								Return (0x0B)
							}
						}

						Return (Zero)
					}

					Method (_CRS, 0, NotSerialized)
					{
						CreateDWordField (CRS, \_SB.PCI0.LPCB.HPET._Y0D._BAS, HPT)
						Multiply (HPTS, 0x1000, Local0)
						Add (Local0, 0xFED00000, HPT)
						Return (CRS)
					}
				}

My old HPET:
Device (HPET)
				{
					Name (_HID, EisaId ("PNP0103"))
					Name (ATT3, ResourceTemplate ()
					{
						IRQNoFlags ()
							{0}
						IRQNoFlags ()
							{8}
						Memory32Fixed (ReadWrite,
							0xFED00000,		 // Address Base
							0x00000400,		 // Address Length
							)
					})
					Name (ATT4, ResourceTemplate ()
					{
					})
					Method (_STA, 0, NotSerialized)
					{
						Return (0x0F)
					}

					Method (_CRS, 0, NotSerialized)
					{
						Return (ATT3)
					}
				}

I think I will keep trying with my previous method but use your HPET, seeing as it talks to the LPC.

Here's my DSDT with your HPET and Scope _PR:
Attached File  ivik_beer_mashup.zip   29.85KB   27 downloads

#146
yonika

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The original files appear to be fine. You might want to add a change _PSS object – one with more P-States – but that's apparently all you need.

1) Did you enable C States in your BIOS? And if that's a yes, then which one(s)? Edit: Already answered in post #125
2) What model do you see in System Profiler? Edit: Already answered in post #135
3) Can you please add a FACP dump for me?
4) Open IORegistryExplorer (part of Xcode) and check for the items in my two screen shots, do you see the same items there?

n.b. If you don't see the items listed in my screen shots (in post #143) then your changes in Info.plist aren't working.

p.s. Feel free to attach your modified Info.plist to see if I can spot the error ;)


O.k O.k, I think I am now the happiest man in the entire region, or as happy as one can be from seeing numbers jump from x6 to x9 and vice versa :)

Well, first I'll say what happened, then I'll ask more questions :)

I noticed in your message that you said I answered your question about system profiler in post #135, then I said to myself, Hey, I don't remember checking in the system profiler, so I did, and I saw it was on MacPro2,1.
Then I checked my smbios.plist and saw that it was really on 2,1 and not 3,1 (it turns out, I changed the file on the wrong partition) I changed it to 3,1 and Bam, it started jumping with multipliers and voltage.
Then I said to myself, are all the changes I tried really necessary to make it work ? and tried removing changes one by one.
I ended with the following:
smbios.plist with MacPro3,1.
No change at all in AppleSMC plugin
CPUPM SSDT in DSDT (although I did not try to remove that one yet)
CPUISTx2 SSDTs in DSDT with an SPSS fix to look almost like NPSS (fixed last two values for each step, without this it did not work).
No CST method in the DSDT at all (still no CST evaluation error on boot)
No dropSSDT=yes flag on boot or com.apple.Boot.plist

Now for the questions:
1. where do I find more p-states for my E8400 CPU ? is there any intel's official place it is written in ? any kind of database ?
2. How come it works without all the stuff I mentioned ? the SMC plugin change, the dropSSDT flag ? are all these actually unnecessary ?
3. How do I know if C-states work besides not having the error on boot ? is there an application that shows that ?
4. Before the success, I dumped the FACP (attached) and saw that it says "_cst support: 0" what does this mean ?
Do i have c-states or not ??? :)
5. I read that deep sleep works when using the AppleIntelCPUPowerManagement.kext, how do I enable or go into it ?
6. Last question, what is AppleLPC.kext ? I saw it here, and asked myself if i'm missing something important ?


Anyway, here are my files attached if someone wants to take a look,

Thanks in advance,
Jonathan

Attached Files



#147
ivik

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Beerkex'd,

DSDT and SSDT are your's, patched with dsdt patcher and added _CST and _PSS. I have done the same thing with my dsdt, and it is cool like in windows/linux.

Do you have CPUPLimit set to 0 in your ioreg? Do you have PerformanceStateArray and stepper data in ioreg?
You could try replacing NPSS with SPSS.

Also try deleting in HPET Method (_STA, 0, NotSerialized) all, and leave just:
[codebox] Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}[/codebox]

Also try reduce number of CPU's. I have core solo, and i don't know how core duos / C2d are handled.

#148
William Parker

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Have you made any progress using just p-states alone, if so how did you get the values for the fractional multiplier?

@formerlyknownas Great thread, but is there another app besides p-state calculator that will allow fractional multipliers? The Q9550 has six p-states. with multipliers of 6, 6.5, 7, 7.5, 8 and 8.5.

Without any editing of the dsdt and with nullcpupm in my extra folder CPU-i is showing a change from 6x at idle to 8.5 under load. The multiplier/freq is changing but the voltage always remains at the highest p-state.

@william parker
I am just delving into the speedstep myself. Also with the Q9550 processor. Since p-state setting are processor dependent... Please keep posted if you make any progress.




#149
Master Chief

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Have you made any progress using just p-states alone, if so how did you get the values for the fractional multiplier?

I think that I already explained that in post #118

O.k O.k, I think I am now the happiest man in the entire region, or as happy as one can be from seeing numbers jump from x6 to x9 and vice versa :thumbsup_anim:

...

Now for the questions:
1. where do I find more p-states for my E8400 CPU ? is there any intel's official place it is written in ? any kind of database ?
2. How come it works without all the stuff I mentioned ? the SMC plugin change, the dropSSDT flag ? are all these actually unnecessary ?
3. How do I know if C-states work besides not having the error on boot ? is there an application that shows that ?
4. Before the success, I dumped the FACP (attached) and saw that it says "_cst support: 0" what does this mean ?
Do i have c-states or not ??? :thumbsdown_anim:
5. I read that deep sleep works when using the AppleIntelCPUPowerManagement.kext, how do I enable or go into it ?
6. Last question, what is AppleLPC.kext ? I saw it here, and asked myself if i'm missing something important ?
...

1) You'll either have to use the P-State Calculator (link in post #1) or use a calculator.
2) You MB/BIOS supports C1/C2 and C3 (check the latency in the FACP and post #46) so you don't need it.
3) The power should drop to either 1.000 (C2) or 0.500 (C3) in CPU-i.
4) Probably that CST is natively supported, but there's no documentation about this value.
5) You can check it with pmset -g | grep hibernatemode and change it with sudo pmset -a hibernatemode n* or use the Deep Sleep Widget.
6) This appears to be something that lowers the temperature a little, but I don't know, yet, what it really does or is used for.

*Here are the values (from deepsleep.pdf) and the meaning of it:

• 0 (quick): Default sleep behavior on most Apple computers. RAM is still powered on while sleeping. Wake up is fast. Safe sleep is disabled.
• 1 (deep): Hibernation behavior. System is totally shut down while sleeping. RAM contents are dumped to disk. Wake up is slow.
• 3 (safe): Default behavior on Powerbook HD and later computers. RAM is still powered on while sleeping. Wake up is fast. Safe sleep is enabled, so RAM contents are also dumped to disk before going to sleep.
• 5 (deep): Same as mode 1 for systems with encrypted virtual memory.
• 7 (safe): Same as mode 3 for systems with encrypted virtual memory.

Master Chief, thanks, I will try what you said and see what happens.

I do have the ACPI_SMC_PlatformPlugin, AGPMEnabler and AGPMController as well but they only appear under CPU1. CPU2 only has the AppleACPICPU. I don't, however have "CSTInfo" like you..hmm

I have not found any information about CSTInfo as of yet i.e. I don't know exactly what it does/means.

I have P-state switching and proper shutdown when using VoodooPowerMini.kext (thanks Superhai). Without VoodooPower it runs at full throttle and doesn't shut down completely (the classic "lights go off but CPU fan keeps running"). Also when using VoodooPower (and DSDT.aml with no SSDT data) I don't get the CST evaluation error messages on boot.

I have used VoodooPower in the past (thanks Superhai) and I think that it injects data to prevent errors, and to make it work. Superhai?

p.s. I see (uphuck) that you changed some device names in your DSDT (for the uninformed: to match a Mac):

PIC -> IPIC
DMAD > DMAC
TMR -> TIMR
RTC0 -> RTC
COPR -> MATH
OMSC -> LDRC

#150
yonika

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I think that I already explained that in post #118


1) You'll either have to use the P-State Calculator (link in post #1) or use a calculator.
2) You MB/BIOS supports C1/C2 and C3 (check the latency in the FACP) so you don't need it.
3) The power should drop to either1.000 or 0.500 in CPU-i.
4) Probably that CST is natively supported, but there's no documentation about this value.
5) You can check it with pmset -g | grep hibernatemode and change it with sudo pmset -a hibernatemode n* or use the Deep Sleep Widget.
6) This appears to be something that lowers the temperature a little, but I don't know, yet, what it really does or is used for.

*Here are the values (from deepsleep.pdf) and the meaning of it:

• 0 (quick): Default sleep behavior on most Apple computers. RAM is still powered on while sleeping. Wake up is fast. Safe sleep is disabled.
• 1 (deep): Hibernation behavior. System is totally shut down while sleeping. RAM contents are dumped to disk. Wake up is slow.
• 3 (safe): Default behavior on Powerbook HD and later computers. RAM is still powered on while sleeping. Wake up is fast. Safe sleep is enabled, so RAM contents are also dumped to disk before going to sleep.
• 5 (deep): Same as mode 1 for systems with encrypted virtual memory.
• 7 (safe): Same as mode 3 for systems with encrypted virtual memory.

I have not found any information about CSTInfo as of yet i.e. I don't know exactly what it does.


I have used VoodooPower in the past (thanks Superhai) and I think that it injects data to prevent errors, and to make it work. Superhai?


Hey, thanks for replying,

I still don't understand somethings though,

About p-states calculator ? All it does is convert from specific values I set to hex values for the PSS table,
How do i know what power in [mW] or voltages to enter in the first place ? multiplier and speed is easy, though I'm not sure if there are more than just 6,7,8,9 ?

About c-states in cpu-i ? where do i see that ? I can see only speed, multiplier and voltage, am I missing a column ?

About deep sleep ? I tried Smartsleep prefPane (deep sleep widget has a bug in SL) which sets these values of hibernation mode, then I put my hackintosh to sleep, before sleep it gave me the gray screen of deep sleep, and went to sleep, but when I powered it up, it just booted normally, not from the sleep image, then I checked and saw that there was a saved sleep image on disk, I don't understand, how does Chameleon (I'm using RC1) knows if there is a sleep image or not ? and how to boot ? or maybe OS X needs to tell the bios it is not a regular boot ?

Sorry for all these question on questions, and thank you for taking the time and patience to answer, It's just that it always looks close to solving these issues and something else comes up :thumbsup_anim: but now it feels like it's getting somewhere :)

Thanks again,
Jonathan

#151
Master Chief

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Hey, thanks for replying,

I still don't understand somethings though,

About p-states calculator ? All it does is convert from specific values I set to hex values for the PSS table,
How do i know what power in [mW] or voltages to enter in the first place ? multiplier and speed is easy, though I'm not sure if there are more than just 6,7,8,9 ?

You can easily verify all this with help of CPU-i (P-States) which works for me here.

About c-states in cpu-i ? where do i see that ? I can see only speed, multiplier and voltage, am I missing a column ?

No, and like I said; it should drop power. That's a pretty clear indicator.

About deep sleep ? I tried Smartsleep prefPane (deep sleep widget has a bug in SL) which sets these values of hibernation mode, then I put my hackintosh to sleep, before sleep it gave me the gray screen of deep sleep, and went to sleep, but when I powered it up, it just booted normally, not from the sleep image, then I checked and saw that there was a saved sleep image on disk, I don't understand, how does Chameleon (I'm using RC1) knows if there is a sleep image or not ? and how to boot ? or maybe OS X needs to tell the bios it is not a regular boot ?

I can't answer all your questions here, since they are unrelated to the matter at hand. But about that bug; Why don't you e-mail Matthieu Beaumel – the author of this widget – and tell him about the bug :thanks_speechbubble:

#152
William Parker

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As appears you do have a clear insight into this issue of pstate values for fractional multiplers as used in the Q9550. But since I do not quite understand coding like you, I will appreciate if you explain how to obtain values for the pstate entries in DSDT for the 8.5, 7.5, and 6.5 multipliers which I am unable to obtain from the p-states calculator app.Another thing I notice is that the calculator does not take vcore values I specify, instead snapping onto values built in. I plan on sticking to values presented by the CPU-i tool p-states tab. As of now I have 3 stepping states integrated into the DSDT which are working as indicated by CPU-i tool. It sure is a relief to see the temps go back to normal - 12 degrees c. lower, sure bring on a sigh of relief. Initially I had problems getting AppleIntelCPU... To load. I enabled all EIST related items in BIOS & it worked. I have no errors of any kind in my logs, at least none related to Cpu or stepping like _cst & the like.Any ideas?

Seems like bit 14 (0x4000/16384) is set for all fractional multipliers i.e. add a 4 in front of the values supplied by the P-States Calculator (0x4720 is working here for 7.5).

Update: I checked the source code of CPU-i and that appears to be correct. Have a look:

#define FID(ctl) (((ctl) & 0xff00) >> 8)
#define VID(ctl) ((ctl) & 0x00ff)
   
columnIdentifier = [NSString stringWithFormat:@"x %d%s", fid & 0x1F, fid & 0x40 ? ".5" : ".0" ];
   
PStatesArray[i].Multiplier =  (fid & 0x0f) + (fid & 0x1F, fid & 0x40 ? 0.5 : 0.0);
But the error checking is... well there is none so I don't know what the API returns.



#153
cyberface

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.....
Once you have SSDT tables they are appended to your DSDT using this method here.
.....


Link does't work

#154
yonika

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You can easily verify all this with help of CPU-i (P-States) which works for me here.


No, and like I said; it should drop power. That's a pretty clear indicator.


I can't answer all your questions here, since they are unrelated to the matter at hand. But about that bug; Why don't you e-mail Matthieu Beaumel – the author of this widget – and tell him about the bug :hysterical:


Well, Just to make sure i'm not hallucinating, I attached 2 screen shots of my CPU-i application,

I can't see any power indicator, and there is no help for cpu-i, maybe i'm using the wrong app ?
Attached File  Screen_shot_2009_09_14_at_11.50.32_PM.png   12.22KB   36 downloads
Attached File  Screen_shot_2009_09_14_at_11.50.44_PM.png   22.62KB   142 downloads
Attached File  Screen_shot_2009_09_14_at_11.51.36_PM.png   11.11KB   33 downloads

10x,
Jonathan

#155
xopher

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Anyone here with a Q8400? I'm trying to figure out the right p-states for it.

I have three active, and working now, the ones I got from CPU-i (post) but I believe it should support more than that. So if anyone has a Q8400 working with all the supported p-states, let me know!

Thanks for the guide(s) guys! :)

Edit: The frequency, mW, and Control of the first (p-state 0) and last p-state (2), were in the _PSS I extracted. Would this suggest that they are the min and max values? [2000mhz and 2667mhz]

The third one I added from the CPU-i output [2333mhz], but I changed P to something in between that of states 0 and 2. Is there a way of calculating this?

#156
Superhai

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About p-states calculator ? All it does is convert from specific values I set to hex values for the PSS table,
How do i know what power in [mW] or voltages to enter in the first place ? multiplier and speed is easy, though I'm not sure if there are more than just 6,7,8,9 ?


I can tell you a bit about P-states and how you can create them. This tutorial require terminal, so if it scares you look away now.

We start by running Reggie SE from terminal:

reggie_se -r -i0 -a 0x198 -B 64

Which should give you something like this (if it doesn't try to add -D Yonah after)

Address 0x00000198 0x0927092706000721 |0 0 0 0|1 0 0 1|0 0 1 0|0 1 1 1|0 0 0 0|1 0 0 1|0 0 1 0|0 1 1 1|0 0 0 0|0 1 1 0|0 0 0 0|0 0 0 0|0 0 0 0|0 1 1 1|0 0 1 0|0 0 0 1|

This is the IA32_PERF_STATUS MSR.

I will break it down for you the most important parts:

0x0927092706000721
This is the current hardware "P-state", as I see you have mentioned elsewhere here it is part FID (0x07) and VID (0x021) I will tell a bit about calculations of those later.
0x0927092706000721
This part is a couple of flags. I will not go in details here (ask if interested, in short if some are set they tell you that you are in a EST transistion or there is a THERM event.
0x0927092706000721
This is the lowest bus ratio (multiplier) supported by the CPU. It is almost always 0x06 (if it is 0x00 it is pre-core type cpu and is reserved)
0x0927092706000721
This is max hardware "P-state"
0x0927092706000721
And this is system boot hardware "P-state", this is usually the same as max on desktop/server cpus and the minimum supported on mobile cpus.

Hardware "P-state"
As you may know this already it resolve to a frequency and voltage id. It is a 16 bit value, and has changed somewhat from technology changes at Intel. We use the above current "p-state" as an example.

The first 6 bits (0 to 5) is the VID value and here it is 0x27. There are a bit of myths about these ID's as Intel refuse to publish these to the public, but only to chosen fews among the BIOS devs. They do however correlate to the hardware VID's as published in the processor datasheets. And to make this clear once and for all, the VID stepping for Core class (Core 2 Duo, Core Solo/Duo, Atom etc.) are 12.5 mV. Only the Pentium M class CPU uses 16.0 mV. On this CPU here I used in the example a E6600 dekstop CPU the EST VID table starts at 825.0 mV, on mobile and newer core cpu's the table starts at 712.5 mV. Pentium M class CPU's has a table that starts at 700.0 mV. Netburst uses a bit akward table and i7 have a finer graded one. If you need more info I can take it later. In this case the cpu runs at 1237.5 mV. The next 2 bits are reserved.

Bits from position 8 to 12 is the bus ratio. In this case 0x7 means a bus ratio of 7. Most of you know that the cpu frequency is the product of bus ratio and bus frequency, I have a 266 MHz bus frequency so it is running at ~1866 MHz now. The next bit (13) is the non-integer-bus-ratio or half-multiplier bit, setting it will "add" half bus frequncy to the final running CPU frequency or in other words add half a multiplier so you could use 7.5x. The next bit (14) is the Dynamic FSB or SLFM mode bit (support is found in IA32_EXT_CONFIG MSR) and is usually used to get frequencies below the normal 6x multiplier (usually to get the CPU down to 600MHz or 800MHz).

So as you see you now know enough to find max hw "p-state". So how to find the lowest? FID is easy as you know the multiplier, and you can find out if your cpu supports SLFM - you add its bit to it. VID is a bit tricky, you can check the intel datasheets, but it is not always clear. If you have a laptop it is usually booted in the lowest "p-state" and you can therefore use it. For desktops it is more a guess, but if you are lucky your m/b producer have added a low p-state to your _PSS already. In other cases you will need to try and test. To make intermediate p-states, you just find some values that are between max and min. Commonly is to use one extra which is somewhat in the middle, or one p-state for each full multiplier, but you are really free to experiment. Also using lower vid values are possible (i.e. undervolt), but on higher fids it might cause issues, so try and test is the mantra.

If you want to set a specific hardware "P-state" you use MSR 0x199. You may use reggie_se to do this, an example:

reggie_se -w 0x0927 -i0 -a 0x199 -B 64

This will set it to the max P-state as you see from above, you can try other values, but be aware that setting values with too high fid and too low vid could cause a freeze of your system. You cannot set a value higher than max. (-i0 is CPU0, -i1 is CPU1, -ia could be used for all CPU's) For IDA (Intel Dynamic Acceleration) it will engage automatically and needs bit 32 set to 1 to disengage.

To find Power output for the _PSS value you should check the cpu datasheet, you need some basic electrical background to know what to look for, and usually is of minor interest as most boards are designed to provide enough juice to the CPU. Using after-market CPU upgrades on laptops might be another issue. But laptops usually have defined _PSS, so use the values there, and to create something in between just calculate.

Is this helpful for you?

#157
yeehaa

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@cyberface: from google cache
http://74.125.95.132...lient=firefox-a


@Master Chief: can you please help me with integrating my ssdt into dsdt?
I have my pstates in dsdt already and working. now decided to transfer all the ssdt tables so that i have working cstates too. but then i get this error "operation region" referring to the ssdt table address (you solved this in post #71). Being a newbie have no idea how to solve this. i am attaching all my tables here. please have a look when u can!

ACPIDump: acpi dump from Ubuntu. contains the facp table and all the 6 ssdt tables.
Attached File  ACPIDump.zip   57.27KB   8 downloads

mine.dsl: my dsdt with various fixes and additions. i have inserted all the ssdt tables and it gives me 8 errors (in 4 locations) where it refers to the IST and CST from SSDT. (one thing i dont understand here is, i dont see an IST1 or CST1 memory reference anywhere! another thing is NPSS. that too is missing)
Attached File  mine.dsl.zip   42.95KB   10 downloads

thanks in advance

@Super hai: patiently waiting for your voodoopower and voodoobattery for Snowleopard 64!

#158
Brett Whinnen

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Hmm all I get is:

bash-3.2# reggie_se -r -i0 -a 0x198 -B 64
WARNING: Could not determine processor information.
WARNING: Could not determine memory controller information.
WARNING: Could not determine Operating System information.
ERROR: unknown processor type

bash-3.2# reggie_se -r -i0 -a 0x198 -B 64 -D Yonah
WARNING: Could not determine processor information.
WARNING: Could not determine memory controller information.
WARNING: Could not determine Operating System information.
. 4.7.1 (260)
CPU0 - Yonah (MANUALLY SELECTED)
ERROR: unable to read register

So I guess it is having issues recognizing the T9300 properly. Coolbook (32 and 64bit) shows the pstate transitioning working as does MSR Tools (32bit). IO Reg explorer shows all the Penryn bits loaded...


@cyberface: from google cache
http://74.125.95.132...lient=firefox-a


@Master Chief: can you please help me with integrating my ssdt into dsdt?
I have my pstates in dsdt already and working. now decided to transfer all the ssdt tables so that i have working cstates too. but then i get this error "operation region" referring to the ssdt table address (you solved this in post #71). Being a newbie have no idea how to solve this. i am attaching all my tables here. please have a look when u can!

ACPIDump: acpi dump from Ubuntu. contains the facp table and all the 6 ssdt tables.
Attached File  ACPIDump.zip   57.27KB   8 downloads

mine.dsl: my dsdt with various fixes and additions. i have inserted all the ssdt tables and it gives me 8 errors (in 4 locations) where it refers to the IST and CST from SSDT. (one thing i dont understand here is, i dont see an IST1 or CST1 memory reference anywhere! another thing is NPSS. that too is missing)
Attached File  mine.dsl.zip   42.95KB   10 downloads

thanks in advance

@Super hai: patiently waiting for your voodoopower and voodoobattery for Snowleopard 64!


You can get away with defining NPSS as external.

External (NPSS, IntObj)

Just do it under which ever CPU is needing it. This seems to work fine. The sad thing is I don't know where it is defined *sigh* I have my DSDT and 6 SSDT tables dumped and cannot find any reference to it.

Errors:

1 - 8. SSDT unknown reference, you need to get the SSDT table from SSDT0 and insert this into your DSDT before your _SB statement where your Processor definitions are e.g. before your block:

Name (CFGD, 0x053969F1)
Name (\PDC0, 0x80000000)
Name (\PDC1, 0x80000000)
Name (\PDC2, 0x80000000)
Name (\PDC3, 0x80000000)
Name (\SDTL, Zero)

The code would look similar to:


Scope (\)
{
Name (SSDT, Package (0x0C)
{
"CPU0IST ",
0xDFE72CB4,
0x02C8,
"CPU1IST ",
0xDFE72F7C,
0xC4,
"CPU0CST ",
0xDFE7264A,
0x05E5,
"CPU1CST ",
0xDFE72C2F,
0x85
})
Name (CFGD, 0x013369F7)
Name (PDC0, 0x80000000)
Name (PDC1, 0x80000000)
Name (SDTL, Zero)
}

Which is from my DSDT.dsl.

Hope that helps.

Does anyone have a copy of a Voodoo kernel I could use to load with kprintf=1 that would work with SL, or would I need to go back to Leo for this?

Cheers
Brett

#159
yonika

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I can tell you a bit about P-states and how you can create them. This tutorial require terminal, so if it scares you look away now.
...They do however correlate to the hardware VID's as published in the processor datasheets. And to make this clear once and for all, the VID stepping for Core class (Core 2 Duo, Core Solo/Duo, Atom etc.) are 12.5 mV.....

....To find Power output for the _PSS value you should check the cpu datasheet, you need some basic electrical background to know what to look for, and usually is of minor interest as most boards are designed to provide enough juice to the CPU. ....

Is this helpful for you?


10x man for the great explanation, I knew some of the details but was not aware to each and every bit in the register.
Well, I am an electrical engineer :D so I will look into intel's data sheets.

The thing that scared me the most was the power in mW in each p-state, I don't really want just to experiment with that, I will look in the data sheet and see if something there's helpful.

There's just one thing I haven't figured out yet, Master Chief said something about seeing the power value in CPU-i drop to 0.5 and go up to 1.0 if I have c-states working, I just could not find anywhere on CPU-i this information.

Where the heck to I see this info ??? and if not that info, how can I see if c-states are changing ?

10x again,
Jonathan.

P.S - does manual throttling in CPU-i work for anyone ?

#160
xopher

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There's just one thing I haven't figured out yet, Master Chief said something about seeing the power value in CPU-i drop to 0.5 and go up to 1.0 if I have c-states working, I just could not find anywhere on CPU-i this information.

Where the heck to I see this info ???


http://www.insanelym...p...st&id=56616

The voltage value is what MasterChief is referring to. It should drop to the value designated in your _PSS when Speedstep changes multiplier when eg. idle. If it falls to 0.5 you should have C-states working, because it reduces the power consumption even further.





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