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[AMD] Yosemite Kernel Testing (for help use the Help Topic)


Duran Keeley
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Ok, I implemented the changes in your opemu.

I also took the liberty of fixing some warnings...

Please test people, I'm curious to see the results...

10.10.2 Kernel Panic. Chameleon 2538

 

Update Old TSC For 5350

 

I like old TSC

 

Because it is easy to modify

 

And support PENTIUM series

10.10.0 Works ok. Haven't had much time to test but there's no image glitch. Adobe flash works and even safari webkit nightly works (it usually crashed at start on previous kernels)

post-670953-0-93868500-1423411991_thumb.jpg

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Update Old TSC For 5350

 

I like old TSC

 

Because it is easy to modify

 

And support PENTIUM series

 

I replied system to 10.10.1

Found that the JPEG problems have been resolved
 
Including the original xcode 6 clang not compile problems
and Google Chrome 40.xxxx & adobe flash player …etc
All issues have been resolved
 
Very long time….
 
Now Can finally rest & enjoy this perfect results face62.gif face62.gif
 

 

 

:)

 

invalid opcode 64  (kabini)  :) 

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(10.10.1 - 10.10.2)

copy and paste content Extensions 10.10.1 inside extensions

10.10.2 with kext wizard put the kext replace
 
10.10.2  -  10.10.3
copy and paste content Extensions 10.10.2 inside extensions
10.10.3 with kext wizard put the kext replace
 
carlo_67
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(10.10.1 - 10.10.2)

copy and paste content Extensions 10.10.1 inside extensions

10.10.2 with kext wizard put the kext replace
 
10.10.2  -  10.10.3
copy and paste content Extensions 10.10.2 inside extensions
10.10.3 with kext wizard put the kext replace
 
carlo_67

 

:)

 

replace iopci and acpip but no boot ( KP or invalide opcode 64 )   :worried_anim:

post-1093405-0-25805000-1423437565_thumb.png

post-1093405-0-72703600-1423437580_thumb.png

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invalid kernel opcode Analysis 10.10.2 v2

 
invalid kernel opcode (64-bit): 44 0F B6 1F
 
 
this x86 opcode 0F B6 movzx 
Add REX Prefix to 64-bit Opcode
 
44 0F B6 1F
movzx r11d, byte [ds:rdi]
 
mod 0 r/m 7 digit 3 
 
0x44 = REX Prefix
0xB6 = opcode
0x1F =  modrm
 
dst 32-bit r11d reg <— src 64bit reg get ptr rdi 1-byte (movzx Convert to 32bit zero-extension)
 
 
example:
 
if  PTR RDI = 0x0000000000001234
addr 0x0000000000001234 Value = 0x05 0x06 0x07 0x08
get ptr 0x0000000000001234 byte 0x05
Convert to 32bit zero-extension = 0x00000005
src 0x00000005 move to r11d Register
 
My K10 Athlon seem Not support this Opcode
 
 
REX Mode
mod 3 mode
40 0F B6 C0 
movzx      eax, al
 
41 0F B6 C0 
movzx      eax, r8b
 
44 0F B6 C0
movzx      r8d, al
 
45 0F B6 C0 
movzx      r8d, r8b
 
May be required add new register r8d-r15d
 
10.10.2 xnu version number is xnu-2782.10.72
 
 
===================================
 
 
64-bit Register
1   2   3   4   5   6   7   8
01  02  03  04  05  06  07  08
                           |AL| Byte            8bit
                       |AH|     Byte            8bit
                       |AX    | word (2-Byte)   16bit
                |EAX          | dword (4-Byte)  32bit
|RAX                          | qword (8-Byte)  64bit
 
8-bit Register
0    1    2    3    7    5    6    7
AL   CL   DL   BL   SIL  BPL  SIL  DIL
R8b  R9b  R10b R11b R12b R13b R14b R15b
 
16-bit Register
0    1    2    3    7    5    6    7
AX   CX   DX   BX   SP   BP   SI   DI
R8w  R9w  R10w R11w R12w R13w R14w R15w
 
32-bit Register
0    1    2    3    7    5    6    7
EAX  ECX  EDX  EBX  ESP  EBP  ESI  EDI
R8d  R9d  R10d R11d R12d R13d R14d R15d
 
64-bit Register
0    1    2    3    7    5    6    7
RAX  RCX  RDX  RBX  RSP  RBP  RSI  RDI
R8   R9   R10  R11  R12  R13  R14  R15
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Is it possible that ssl error is present in latest kernel? And that's why method with iCloud files replacement from Intel machine does not work on Yosemite.

I ask because I have such problem earlier on Maverics, http://www.insanelymac.com/forum/topic/282821-icloud-for-amd-hackintoshes-a-workaround/page-2?do=findComment&comment=2023034.

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Update Old TSC For 5350

 

I like old TSC

 

Because it is easy to modify

 

And support PENTIUM series

 

I replied system to 10.10.1

Found that the JPEG problems have been resolved
 
Including the original xcode 6 clang not compile problems
and Google Chrome 40.xxxx & adobe flash player …etc
All issues have been resolved
 
Very long time….
 
Now Can finally rest & enjoy this perfect results face62.gif face62.gif
 

 

 

Hello Tora Chi Yo !

 

Many thanx for your work, 1010-SSEPlus-Rev.6 works very well on my old Athlon 64 x2 3800+ !

AppStore, iCloud, Safari, Flash, are all OK on 10.10.1 with AMD Replacement kexts :thumbsup_anim:

 

Tried 10.10.2 update but stuck at invalid kernel opcode so I'll wait for a fix before retry :D

 

But I'm confident ! :thumbsup_anim:  You guys made a wonderful job so far !!!

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@Tora Chi Yo: I've got a little something for you.

I've got my hands on the intel arch manuals... complete...

This includes instructions not yet released (but bound to be implemented in the next gen of Broadwel CPU's).

It are complete manuals so a must read. ;)

Intel_Arch_Docs.zip

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Is it possible that ssl error is present in latest kernel? And that's why method with iCloud files replacement from Intel machine does not work on Yosemite.

I ask because I have such problem earlier on Maverics, http://www.insanelymac.com/forum/topic/282821-icloud-for-amd-hackintoshes-a-workaround/page-2?do=findComment&comment=2023034.

Yes, it still is present in latest OS X.

This is why I created my own custom OpenSSL upgrade (based on latest 1.0.1l and Apple's sources).

I was tired of seeing SSL errors...

Actually... when I first installed Yosemite, the first conclusion was that I had to delete the rejection cache and reset keychain...

I actually offered Apple my upgrades but never got a mail back... shame... they shouldn't waste proven technologies lol

 

invalid kernel opcode Analysis 10.10.2 v2

 
invalid kernel opcode (64-bit): 44 0F B6 1F
 
 
this x86 opcode 0F B6 movzx 
Add REX Prefix to 64-bit Opcode
 
44 0F B6 1F
movzx r11d, byte [ds:rdi]
 
mod 0 r/m 7 digit 3 
 
0x44 = REX Prefix
0xB6 = opcode
0x1F =  modrm
 
dst 32-bit r11d reg <— src 64bit reg get ptr rdi 1-byte (movzx Convert to 32bit zero-extension)
 
 
example:
 
if  PTR RDI = 0x0000000000001234
addr 0x0000000000001234 Value = 0x05 0x06 0x07 0x08
get ptr 0x0000000000001234 byte 0x05
Convert to 32bit zero-extension = 0x00000005
src 0x00000005 move to r11d Register
 
My K10 Athlon seem Not support this Opcode
 
 
REX Mode
mod 3 mode
40 0F B6 C0 
movzx      eax, al
 
41 0F B6 C0 
movzx      eax, r8b
 
44 0F B6 C0
movzx      r8d, al
 
45 0F B6 C0 
movzx      r8d, r8b
 
May be required add new register r8d-r15d
 
10.10.2 xnu version number is xnu-2782.10.72
 
 
===================================
 
 
64-bit Register
1   2   3   4   5   6   7   8
01  02  03  04  05  06  07  08
                           |AL| Byte            8bit
                       |AH|     Byte            8bit
                       |AX    | word (2-Byte)   16bit
                |EAX          | dword (4-Byte)  32bit
|RAX                          | qword (8-Byte)  64bit
 
8-bit Register
0    1    2    3    7    5    6    7
AL   CL   DL   BL   SIL  BPL  SIL  DIL
R8b  R9b  R10b R11b R12b R13b R14b R15b
 
16-bit Register
0    1    2    3    7    5    6    7
AX   CX   DX   BX   SP   BP   SI   DI
R8w  R9w  R10w R11w R12w R13w R14w R15w
 
32-bit Register
0    1    2    3    7    5    6    7
EAX  ECX  EDX  EBX  ESP  EBP  ESI  EDI
R8d  R9d  R10d R11d R12d R13d R14d R15d
 
64-bit Register
0    1    2    3    7    5    6    7
RAX  RCX  RDX  RBX  RSP  RBP  RSI  RDI
R8   R9   R10  R11  R12  R13  R14  R15

 

Actually those are the same registers but lower bits...

/* 16 bits register */
typedef struct register16_s
{
    uint8_t L; // Lower 8 bits
    uint8_t H; // Upper 8 bits
} register16_t;

typedef union
{
    register16_t P; // Parts
    uint16_t D; // Data
} register16;

/* 32 bits register */
typedef struct register32_s
{
    register16 L; // Lower 16 bits
    register16 H; // Upper 16 bits
} register32_t;

typedef union
{
    register32_t P; // parts
    uint32_t D; // Data
} register32;

/* 64 bits register */
typedef struct register64_s
{
    register32 L; // Lower 32 bits
    register32 H; // Upper 32 bits
} register64_t;

typedef union
{
    register64_t P; // Parts
    uint64_t D; // Data
} register64;

Note the use of a union to be able to access direct values and structures to be able to access parts...

This way one can access both the upper and lower data parts (where required) and only handle those parts of the registers.

This is perfect for for example r8d.

As you would be able to handle only the 32 bits in the lower parts, not changing the upper parts.

Same for r8w...

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Hi Tora Chi Yo!

I now get panic from your patch.diff ! 

I found and fix (modified) ! Now without panic ! 

 

1) In sse3_run() :

// SSE3 Type 1

    if((*bytep == 0x66 && bytep[1] == 0x0f && bytep[2] != 0x38) || (*bytep == 0x66 && bytep[1] == 0x0f && bytep[2] != 0x3A)) <<-- you see 0x3a and 0x38 <<-- you should delete and should how show : 

// SSE3 Type 1

    if((*bytep == 0x66 && bytep[1] == 0x0f ) || (*bytep == 0x66 && bytep[1] == 0x0f ))  < because 0x38 and 0x3a - this only for ssse3 =)))

 

2) in operands()

in mod==2 i fix :

 

//INS    phaddw xmm0, xmmword ptr [rax+1020304h]

address = reg_sel[base] + ...

to 

address = reg_sel[index] + ...

 

and other fix ... )))

 

 

Include patch.diff )

Now without glitches in safari from my opemu ))) 

 

kernel_10.10_all_amd_rc5.zip

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Just making sure I'm understanding correctly (been lurking for several months now), but to go from 10.10.1 to 10.10.3 (directly or indirectly), I should back up System.kext, Sandbox.kext, IOPCIFamily.kext, and AppleACPIPlatform.kext, right? 

Also, am I missing any Kexts that I should back up? AMD FX-4100 here. Just want to make sure I've got everything in order before I pull the trigger and download the update combo installers.

One more thing: if there's anything I can do to help in testing, I'll do so.

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Hi Tora Chi Yo!

I now get panic from your patch.diff ! 

I found and fix (modified) ! Now without panic ! 

 

1) In sse3_run() :

// SSE3 Type 1

    if((*bytep == 0x66 && bytep[1] == 0x0f && bytep[2] != 0x38) || (*bytep == 0x66 && bytep[1] == 0x0f && bytep[2] != 0x3A)) <<-- you see 0x3a and 0x38 <<-- you should delete and should how show : 

// SSE3 Type 1

    if((*bytep == 0x66 && bytep[1] == 0x0f ) || (*bytep == 0x66 && bytep[1] == 0x0f ))  < because 0x38 and 0x3a - this only for ssse3 =)))

 

2) in operands()

in mod==2 i fix :

 

//INS    phaddw xmm0, xmmword ptr [rax+1020304h]

address = reg_sel[base] + ...

to 

address = reg_sel[index] + ...

 

and other fix ... )))

 

 

Include patch.diff )

Now without glitches in safari from my opemu ))) 

 

attachicon.gifkernel_10.10_all_amd_rc5.zip

 

 

HI Bronya

 

//INS phaddw xmm0, xmmword ptr [rax+1020304h]

 

[rax+.....]

 

this rax is Base Not Index
 

 

if index in Pointer [ ] is display [rax*2] or[rax*4] or[rax*8]
 
index register  in Pointer Must is [index * Scaling factor]
 
 
Use this Debuger "Hopper.Disassembler"open any binary file 
 
Enter HEX instruction set encoded
 
Click “ ⌘ + Shift + H” Can modify the HEX value
 
Before the operation you may want to read the Intel manual 32bit-addressing mode Table 2-2
 
if SIB Byte HEX value increment 1 Change register Is Base
 
if SIB Byte HEX value increment 8 Change register Is Index

Yes, it still is present in latest OS X.

This is why I created my own custom OpenSSL upgrade (based on latest 1.0.1l and Apple's sources).

I was tired of seeing SSL errors...

Actually... when I first installed Yosemite, the first conclusion was that I had to delete the rejection cache and reset keychain...

I actually offered Apple my upgrades but never got a mail back... shame... they shouldn't waste proven technologies lol

Actually those are the same registers but lower bits...

/* 16 bits register */
typedef struct register16_s
{
    uint8_t L; // Lower 8 bits
    uint8_t H; // Upper 8 bits
} register16_t;

typedef union
{
    register16_t P; // Parts
    uint16_t D; // Data
} register16;

/* 32 bits register */
typedef struct register32_s
{
    register16 L; // Lower 16 bits
    register16 H; // Upper 16 bits
} register32_t;

typedef union
{
    register32_t P; // parts
    uint32_t D; // Data
} register32;

/* 64 bits register */
typedef struct register64_s
{
    register32 L; // Lower 32 bits
    register32 H; // Upper 32 bits
} register64_t;

typedef union
{
    register64_t P; // Parts
    uint64_t D; // Data
} register64;

Note the use of a union to be able to access direct values and structures to be able to access parts...

This way one can access both the upper and lower data parts (where required) and only handle those parts of the registers.

This is perfect for for example r8d.

As you would be able to handle only the 32 bits in the lower parts, not changing the upper parts.

Same for r8w...

 

@ AnV

 

C ++ aspect I was a beginner

 

I only know how to analyze

 

I try to further study

 
THX

:)

 

This is your APU test results ??

Hopper.Disassembler.v3.6.10.zip

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