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[AMD] Yosemite Kernel Testing (for help use the Help Topic)


Duran Keeley
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Does the latest kernel work for you Gils?

 

I have yet to test your kernel but Andy AppStore on FX CPU works perfectly, Carlo has a direct problem with its network that has nothing to do with the kernel, I have not tested K10 CPU in Right now I galley on a HD 6850 that bug :(

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Implementation code for old opemu:

const int palignr_getimm128(const unsigned char *bytep)
{
    int rv = 0;
    uint8_t modrm = bytep[4];
    
    if (modrm < 0x40)
    {
        rv = (int)bytep[5];
    } else if (modrm < 0x80) {
        rv = (int)bytep[6];
    } else if (modrm < 0xC0) {
        rv = (int)bytep[9];
    } else {
        rv = (int)bytep[5];
    }
    
    return (const int)rv;
}

const int palignr_getimm64(const unsigned char *bytep)
{
    int rv = 0;
    uint8_t modrm = bytep[3];
    
    if (modrm < 0x40)
    {
        rv = (int)bytep[4];
    } else if (modrm < 0x80) {
        rv = (int)bytep[5];
    } else if (modrm < 0xC0) {
        rv = (int)bytep[8];
    } else {
        rv = (int)bytep[4];
    }
    
    return (const int)rv;
}

/** Runs the ssse3 emulator. returns the number of bytes consumed.
 **/
int ssse3_run(uint8_t *instruction, x86_saved_state_t *state, int longmode, int kernel_trap)
{
    // pointer to the current byte we're working on
    uint8_t *bytep = instruction;
    int ins_size = 0;
    int is_128 = 0, src_higher = 0, dst_higher = 0;
    
    
    ssp_m128 xmmsrc, xmmdst, xmmres;
    ssp_m64 mmsrc,mmdst, mmres;
    
    
    /** We can get a few prefixes, in any order:
     **  66 throws into 128-bit xmm mode.
     **  40->4f use higher xmm registers.
     **/
    if(*bytep == 0x66) {
        is_128 = 1;
        bytep++;
        ins_size++;
    }
    if((*bytep & 0xF0) == 0x40) {
        if(*bytep & 1) src_higher = 1;
        if(*bytep & 4) dst_higher = 1;
        bytep++;
        ins_size++;
    }
    
    if(*bytep != 0x0f) return 0;
    bytep++;
    ins_size++;
    
    /* Two SSSE3 instruction prefixes. */
    if((*bytep == 0x38 && bytep[1] != 0x0f) || (*bytep == 0x3a && bytep[1] == 0x0f)) {
        uint8_t opcode = bytep[1];
        uint8_t *modrm = &bytep[2];
        uint8_t operand;
        ins_size += 2; // not counting modRM byte or anything after.
        
        if(is_128) {
            int consumed = fetchoperands(modrm, src_higher, dst_higher, &xmmsrc, &xmmdst, longmode, state, kernel_trap, 1, ins_size);
            operand = bytep[2 + consumed];
            ins_size += consumed;

            switch(opcode) {
                case 0x00:
                    //pshufb128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_shuffle_epi8_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x01:
                    //phaddw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hadd_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x02:
                    //phaddd128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hadd_epi32_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x03:
                    //phaddsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hadds_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x04:
                    //pmaddubsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_maddubs_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x05:
                    //phsubw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hsub_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x06:
                    //phsubd128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hsub_epi32_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x07:
                    //phsubsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hsubs_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x08:
                    //psignb128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_sign_epi8_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x09:
                    //psignw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_sign_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x0A:
                    //psignd128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_sign_epi32_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x0B:
                    //pmulhrsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_mulhrs_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x0F:
                    //palignr128(&xmmsrc,&xmmdst,&xmmres,(const int)operand);
                    xmmres.i = ssp_alignr_epi8_REF(xmmdst.i, xmmsrc.i, palignr_getimm128(bytep));
                    ins_size++;
                    break;

                case 0x1C:
                    //pabsb128(&xmmsrc,&xmmres);
                    xmmres.i = ssp_abs_epi8_REF(xmmsrc.i);
                    break;

                case 0x1D:
                    //pabsw128(&xmmsrc,&xmmres);
                    xmmres.i = ssp_abs_epi16_REF(xmmsrc.i);
                    break;

                case 0x1E:
                    //pabsd128(&xmmsrc,&xmmres);
                    xmmres.i = ssp_abs_epi32_REF(xmmsrc.i);
                    break;

                default:
                    return 0;
            }

            storeresult128(*modrm, dst_higher, xmmres);
        } else {
            int consumed = fetchoperands(modrm, src_higher, dst_higher, &mmsrc, &mmdst, longmode, state, kernel_trap, 0, ins_size);
            operand = bytep[2 + consumed];
            ins_size += consumed;

            switch(opcode) {
                case 0x00:
                    //pshufb64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_shuffle_pi8_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x01:
                    //phaddw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hadd_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x02:
                    //phaddd64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hadd_pi32_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x03:
                    //phaddsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hadds_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x04:
                    //pmaddubsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_maddubs_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x05:
                    //phsubw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hsub_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x06:
                    //phsubd64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hsub_pi32_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x07:
                    //phsubsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hsubs_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x08:
                    //psignb64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_sign_pi8_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x09:
                    //psignw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_sign_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x0A:
                    //psignd64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_sign_pi32_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x0B:
                    //pmulhrsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_mulhrs_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x0F:
                    //palignr64(&mmsrc,&mmdst,&mmres, (const int)operand);
                    mmres.m64 = ssp_alignr_pi8_REF(mmdst.m64, mmsrc.m64, palignr_getimm64(bytep));
                    ins_size++;
                    break;

                case 0x1C:
                    //pabsb64(&mmsrc,&mmres);
                    mmres.m64 = ssp_abs_pi8_REF(mmsrc.m64);
                    break;

                case 0x1D:
                    //pabsw64(&mmsrc,&mmres);
                    mmres.m64 = ssp_abs_pi16_REF(mmsrc.m64);
                    break;

                case 0x1E:
                    //pabsd64(&mmsrc,&mmres);
                    mmres.m64 = ssp_abs_pi32_REF(mmsrc.m64);
                    break;

                default:
                    return 0;
            }

            storeresult64(*modrm, dst_higher, mmres);
        }
        
    } else {
        // opcode wasn't handled here
        return 0;
    }
    
    return ins_size;
}

I'm currently working on the opemu mark 4.

It even supports relative displacement (disp8 / disp32).

I just finished adaptations to the code and I'm ready to start compiling the code.

If all goes well, new kernel in a short while.

 

HI AnV

 

sorry

 

Before my analysis is wrong

0  1  2  3  4
66 0f 3a 0f **

byte[4] is「modrm byte」 Range 0x00 - 0xff (0-255)

 

modrm 4 mode is 「mod = *ModRM >> 6;」get mod 0 - 3

 

//modrm 00

mod == 0 Range (0x00 - 0x3f)

 

//modrm 01

mod ==1 Range (0x40 - 0x7f)

 

//modrm 10

mod ==2 Range (0x80 - 0xbf)

 

//modrm 11

mod ==3 Range (0xc0 - 0xff)

 

 

Not 「if modrm (byte[4])  > BF」

 

Should be

unsigned char mod = *ModRM >> 6; //(0-255)

if mod == 0
   ....
if mod == 1
   ....
if mod == 2
   ....

I checked ssse3_run No Error

I currently checking fetchoperands

 

I found  modrm src = 4 or 5 There are differences in the length of byte

 

I will re-decryption SINETEK code

 

re-correction data repost

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Hi AnV

 

SINETEK code has been decrypted

Please See http://www.insanelymac.com/forum/topic/304258-ssse3-opcode-mode-for-amd-opemu/

Function fetchoperands Is wrong

 

This is my idea

original mod 3 is Right

but mod 0 src 4 Missing mod0-src4-base5

if(mod == 0)
    if(num_src == 4)
        if(base == 5)
            mod0-src4-base5 ....(original Missing)
        else
            mod0-src4 ....

    else if(num_src == 5)
        mod0-src5 ....

    else
        mod0....

if(mod == 1)
    if(num_src == 4)
        mod1-src4 ....
    else
        mod1....

if(mod == 2)
    if(num_src == 4)
        mod2-src4 ....
    else
        mod2 ....

First understand the SSE instruction set works

Then modify

 

 

There is also a question

 

pshufb A & Mask

A is dst

Mask ??

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Hi AnV

 

SINETEK code has been decrypted

 

Please See http://www.insanelymac.com/forum/topic/304258-ssse3-opcode-mode-for-amd-opemu/

 

Function fetchoperands Is wrong

 

This is my idea

original mod 3 is Right

but mod 0 src 4 Missing mod0-src4-base5

if(mod == 0)
    if(num_src == 4)
        if(base == 5)
            mod0-src4-base5 ....(original Missing)
        else
            mod0-src4 ....

    else if(num_src == 5)
        mod0-src5 ....

    else
        mod0....

if(mod == 1)
    if(num_src == 4)
        mod1-src4 ....
    else
        mod1....

if(mod == 2)
    if(num_src == 4)
        mod2-src4 ....
    else
        mod2 ....

First understand the SSE instruction set works

 

Then modify

 

 

There is also a question

 

pshufb A & Mask

A is dst

Mask ??

Shuffle bytes mask.

Described inside the docs for Intel SSSE3 implementation.

This should be fine.

If you want to, you're free to do some tests...

I still have no time as I'm still doing payed work for that developer in poland, I did however complete my first milestone for him so that should be my second payment.

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Really?

 

Yes . I tried get value from ud_insn_hex with "printf" - this panic . 

You forgot add one:

1)in function ssse3_grab_operands(...) need add :

 

 if (ssse3_obj->op_obj->state_flavor == SAVEDSTATE_64)

    {

        ssse3_obj->op_obj->state64 = saved_state64(state); <--- this need add and same 32 bit . and normal work

        reg_sel[0] = ssse3_obj->op_obj->state64->rax;

        reg_sel[1] = ssse3_obj->op_obj->state64->rcx;

...

}

2) disp8/disp32 don't working - maybe because problem getting "bytep = ...ud_insn_hex ...;"

 

 

Weird... it should just return the hex data of the instruction :/

Can you trace it to its origin?

 

I tried other metod .  but i get panic :\ . I think that need other try ... 

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Yes . I tried get value from ud_insn_hex with "printf" - this panic . 

You forgot add one:

1)in function ssse3_grab_operands(...) need add :

 

 if (ssse3_obj->op_obj->state_flavor == SAVEDSTATE_64)

    {

        ssse3_obj->op_obj->state64 = saved_state64(state); <--- this need add and same 32 bit . and normal work

        reg_sel[0] = ssse3_obj->op_obj->state64->rax;

        reg_sel[1] = ssse3_obj->op_obj->state64->rcx;

...

}

2) disp8/disp32 don't working - maybe because problem getting "bytep = ...ud_insn_hex ...;"

 

 

 

I tried other metod .  but i get panic :\ . I think that need other try ... 

I know you'll find it... ;)

I'll return to developing the kernel as soon as I've done my work for that developer...

Step 1/4 completed... for now...

So I do have a break now but I've been buried in code and study between yesterday and today... been developing for at least 12 hours (probably more) and now I finished the first module.

I cannot give any specifics of course (this project is private).

I could use a little break... you know how it is...

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10.10  SSSE3 FiX rev.1 for AMD K8 K10
 
fetchoperands memory pointer error FIX
 
Screen Capture PNG & Tiff FIX
 
Safari 8 & Webkit bug FIX
 

My first results with 1010-SSSE3-FIX-rev.1.zip:

Seems that work very...very good))

- png screenshot work

- safari works

- app store works

- can select file with click on icon

 

post-302440-0-20422900-1422972945_thumb.png

 

post-302440-0-01391900-1422972959_thumb.png

 

UPD1:

Graphics bugs with some avatars in Safari:

post-302440-0-62704200-1422973092_thumb.png

 

but it is a vary small problem for this nice kernel)

 

Will be perfect to get iCloud too. Method with replacement files from Intel machine does not work for me.

 

 

UPD2:

Same results with 1010-SSEPlus-SSSE3-FIX.zip

For now I don't see any difference.

 

UPD3:

Made fresh installation.

Safari and App Store work perfect without webkit fix!!!

Launchpad looks good without fixes.

No need any kexts replacements.

Almost perfect kernel!

Thanks for it!!!

 

But one question. Will it work with 10.10.2?

Edited by lpukraine
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10.10  SSSE3 FiX rev.1 for AMD K8 K10
 
fetchoperands memory pointer error FIX
 
Screen Capture PNG & Tiff FIX
 
Safari 8 & Webkit bug FIX
 
 

 

SSSE3 palignr Building…………
 
 

 1010-SSSE3-FIX-rev

 

Hi, 

 

quick test with safari webkit and Safari Preview kit installed.

 

I could  procedure the last 10 min obtain  no error message in safari. after to open  15 internet sides (at the same time, incl. Youtube) no crashes, app store functioned also. I test ........

 

update 1:

 

+   without safari webkit and Safari Picture Preview kit, safari no crashes :angel: , app store functioned, i think this is the solution.......  :lol:  :yes:  :thumbsup_anim:

 

-   without Safari Picture Preview kit, the Preview picture in Safari ,the picture are not sharp, color are not correctly represented (only the preview picture).

 

update 2:

-   without Safari Picture Preview kit, the Preview picture in Safari ,the picture are not sharp, color are not correctly represented (only the preview picture).

----> Solution:   simply the file  ImageIO.Framework and preview app from 10.9.5 to 10.10.1, picture Preview in Safari are now ok.  :rolleyes:

 

 

many thanks

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10.10  SSSE3 FiX rev.1 for AMD K8 K10
 
fetchoperands memory pointer error FIX
 
Screen Capture PNG & Tiff FIX
 
Safari 8 & Webkit bug FIX
 
 

 

SSSE3 palignr Building…………
 
ssse3-fix-rev1_zpscb8677c4.png

 

 

So the kernels work with Phenom CPU-s as well?

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I think yes, 'cauz Phenom is K10 Family

 

Soryy but....i've to copy kernel in S/L/Kernels, right??but how??i've no more the utilities i used to install old kernels, can u pass me a link with instructions??Sorry

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This doesn't work on old Phenom X4 9550, I get only kernel panic.

 

^ Just regular copy-paste, replace and confirm with your password, and reboot, use UseKernelCache=No flag to boot (or -f, it still works I think). After reboot, if it works fine and you want to keep it, use this command in Terminal: sudo kextcache -z -invalidate /

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10.10  SSSE3 FiX rev.1 for AMD K8 K10
 
fetchoperands memory pointer error FIX
 
Screen Capture PNG & Tiff FIX
 
Safari 8 & Webkit bug FIX
 
 

 

SSSE3 palignr Building…………
 
 

 

Congratulation!
I backup !
I checked your diff , cool idea from you ! Thank for use ! ))) 
I need make all modified and kernel ))) . 
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If i try to replace kext in S/L/Kernels, i see no kernel to replace....how to do??I don't want to damage my working system, can u help me?

Ok, i find the issue, i try to show invisible files, but when i try to explore to S/L/Kernels,the files go hidden again, and really i don't know why....how to solve?No way to show hidden files neither with termini commands

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If i try to replace kext in S/L/Kernels, i see no kernel to replace....how to do??I don't want to damage my working system, can u help me?

Ok, i find the issue, i try to show invisible files, but when i try to explore to S/L/Kernels,the files go hidden again, and really i don't know why....how to solve?No way to show hidden files neither with termini commands

IT

qui si testa il kernel non è di aiuto

 

comunque trova in rete ShowAllFiles con quello vedi i file nascosti

 

GOOGLE TRANSLATE:

-----------------

 

IT

here you head the kernel does not help

 

still located in the network with that ShowAllFiles see hidden files

Edited by Duran Keeley
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