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DSDT - Vanilla Speedstep - Generic Scope (_PR)


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#541
FKA

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@FormerlyKnownAs

Question, when observing CPU performance with CPU-i pr VoodooMonitor how often does your CPU hit the x7.0 multiplier? I see mine hit every once and while but not as often as you'd think. Does anyone else see short hits on the "in-between" multipliers? I have three x6, x7 and x8. The x6 and x8 get 90% of the activity.

I'm trying to see how effective my C & P states are.


It depends obviously on activity - but I agree with your findings, I spend most time at 6x or 8x (I have 6x, 7x, 8x)

D.

#542
DieBuche

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@FormerlyKnownAs

Question, when observing CPU performance with CPU-i pr VoodooMonitor how often does your CPU hit the x7.0 multiplier? I see mine hit every once and while but not as often as you'd think. Does anyone else see short hits on the "in-between" multipliers? I have three x6, x7 and x8. The x6 and x8 get 90% of the activity.

I'm trying to see how effective my C & P states are.


Same here: i got 6,7,8,9 but most the time it's either 6 or 9 , never 7 or 8 for more than a second

#543
mm67

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Same here: i got 6,7,8,9 but most the time it's either 6 or 9 , never 7 or 8 for more than a second


Just checking what happens on Windows, Gigabyte naturally has only 2 steps in PSS so that's it for steps, but voltages go through the whole scale exactly same way as in OS X. My MSI board has 5 steps in factory PSS, but it seems to be doing exactly the same as Gigabyte, uses only the max and min values for stepping but voltages go through the whole scale. Maybe it doesn't really matter if you have 2 steps or 6 steps or whatever.

#544
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Just checking what happens on Windows, Gigabyte naturally has only 2 steps in PSS so that's it for steps, but voltages go through the whole scale exactly same way as in OS X. My MSI board has 5 steps in factory PSS, but it seems to be doing exactly the same as Gigabyte, uses only the max and min values for stepping but voltages go through the whole scale. Maybe it doesn't really matter if you have 2 steps or 6 steps or whatever.

What that tells me is that it ain't working for you. Not properly at least. Here all P-States are used. And I bet that you see all cores step up/down simultaneously. Right?

You should see changes in: Frequency, multiplier, voltage and temperature. And all per core, not simultaneously!

Note: The native Intel SpeedStep Technology uses only the lowest and highest multipliers. Not seeing the P-States in between, with a customized _PSS object, usually means that your P-State (latency) values are either invalid or dead wrong.

#545
mm67

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What that tells me is that it ain't working for you. Not properly at least. Here all P-States are used. And I bet that you see all cores step up/down simultaneously. Right?

You should see changes in: Frequency, multiplier, voltage and temperature. And all per core, not simultaneously!

Note: The native Intel SpeedStep Technology uses only the lowest and highest multipliers. Not seeing the P-States in between, with a customized _PSS object, usually means that your P-State (latency) values are either invalid or dead wrong.


I do have all P-states working on OS X, and cores are working independently. It's just that most of the times it's only the lowest and highest steps that are used.

#546
kdawg

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I do have all P-states working on OS X, and cores are working independently. It's just that most of the times it's only the lowest and highest steps that are used.


By independently you mean each core at a different voltage and multiplier?

Update: I retract that. Just read MC's thread.

#547
Matthew L.

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I do have all P-states working on OS X, and cores are working independently. It's just that most of the times it's only the lowest and highest steps that are used.


Uh-oh. Something must be wrong at me, can you please upload your DSDT? (My cpu's cores always change states simultaneously, and really often.)
Stupid speedstep jumps up and down while just browsing the web (no flash content) with playing music and downloading torrents in the background.

#548
mm67

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Uh-oh. Something must be wrong at me, can you please upload your DSDT? (My cpu's cores always change states simultaneously, and really often.)
Stupid speedstep jumps up and down while just browsing the web (no flash content) with playing music and downloading torrents in the background.


You can take my dsdt from Gigabyte thread, on both both my systems it is pretty much only voltages that change until cpu load is about 10 %, then also the multipliers start changing, I'd say that 99 % of time voltages and multipliers change at same time on all cores.

#549
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You can take my dsdt from Gigabyte thread, on both both my systems it is pretty much only voltages that change until cpu load is about 10 %, then also the multipliers start changing, I'd say that 99 % of time voltages and multipliers change at same time on all cores.

Ok then, I was starting to think that I was torturing my CPU for days... BTW, is there any good explanation for the bold part? It's strange, but does happen with mine too. (How come it doesn't hurt the CPU if it changes voltages for nothing so often?)

#550
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What that tells me is that it ain't working for you. Not properly at least. Here all P-States are used. And I bet that you see all cores step up/down simultaneously. Right?

You should see changes in: Frequency, multiplier, voltage and temperature. And all per core, not simultaneously!

Note: The native Intel SpeedStep Technology uses only the lowest and highest multipliers. Not seeing the P-States in between, with a customized _PSS object, usually means that your P-State (latency) values are either invalid or dead wrong.


What's actually being talked about here is what mitch_de has been asking about for the last week or so !

It's the threashold (or cpu load) at which the cpu is stepped up.

We obviously have a very low threashold/ cpu load at which the cpu is stepped up to max multi.

You can see each step - or multi being used - but 90% or the time we're in the lowest or highest multi
.... i.e. we're either loading the cpu or we're not - effectively giving us an i/o (on or off) situation with regards to stepping rather than graduated steps!

I'm not too bothered about this as I'm just happy to make a power saving when my PC is idle.

The question for others (mitch_de's question) is how can that threashold be changed?

D.

#551
stellarola

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Hey guys. So wow, 28 pages and counting. The idea of this thread is great, but it really is hella confusing, possibly a lot of extra stuff not needed? I guess that's just the way threads go anyways. :(

Thankfully I got some help from roisoft to get proper speedstep working on my board (MSI P45 Platinum). Anyways, I figured I'd try my hand at it for my girlfriend's Hackintosh which is a Gigabyte GA-945GCMX-S2 with an Intel Core2Duo E6600. From what it looks like I wasn't able to initiate speedstep yet, but I was however able to lower the temperature significantly and remove the CST errors which is really what I wanted from the beginning. Not to mention I got some odd results with some messing around with model name. Here are my results...

I first took this section that roisoft posted here in post #70 and added it to the beginning of my DSDT in the CPU section. At this point I had my model set for MacPro3,1 and didn't see a difference and had the same temperature as before (45-50c). BTW, CPUPM is loaded.

The next step I took was to inject a device id from AppleLPC which is supposed to help lower temperatures. I added the device id for ICH7M, because it seemed to be the closest to this board which is just ICH7. I added the device id in the PX40 section of the DSDT like this...
Device (PX40)
			{
				Name (_ADR, 0x001F0000)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", 
							Buffer (0x04)
							{
								0xB9, 0x27, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}

After adding this, I rebooted and verbose mode showed that the LPC couldn't be loaded and hence the temperatures still stayed the same, which is hottttt. :P

I read that some people got speedstep working natively when they used the model name MacBookPro5,1 or iMac9,1. So I tried this and ran temperature monitor. The CST errors were gone from verbose mode and the temps dropped from 45-50c to 30c! So I opened up MSR Tools to check this and I found out why. This had dropped the clock speed from 2.4ghz to 1.6ghz and wasn't stepping up! :P
Posted Image

So this wasn't really working for me as it dropped my clock way down. I tried some generic names for the system (GA-945GCMX-S2) and it still didn't do much.

So figuring that choosing a proper model name had to do with something so I finally tried MacPro1,1. This was the sweet spot for me. In verbose mode it loaded up "LegacyHPET" which was different than what the other model names loaded up. I checked in MSR Tools and my clock speed was back up to 2.4ghz but dropped here and there to 2.25ghz at it's lowest point. The best thing though was my temps dropped dramatically. They sit about 30-35C now with CPUPM loaded instead of 45-50c. Here's proof...
Posted Image

Of course this is when I turned the machine on from sleep, but it basically idles about 30-35c now. Also, I removed IRQs from Device PIC and TMR in the DSDT as well. Thats more of a preventative measure than anything but nonetheless it helps for a proper DSDT.

So I'll try to do proper speedstepping later, but for now this has made me extremely happy that her computer's CPU fan doesn't kick into high speed for no reason. Hopefully this has been helpful to some people.

Take care,

-Stell

UPDATE: Using 10.6.2 I don't need to change the model to MacPro1,1 to get proper temps. I ended up renaming back to "GA-945GCMX-S2" and all is fine. :)

#552
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What's actually being talked about here is what mitch_de has been asking about for the last week or so !

< snip />

The question for others (mitch_de's question) is how can that threashold be changed?

D.


There is no such thing as a "threshold" in terms of Intel Speedstep Technology. There might be one in VoodooPower but my guess is that this is a refresh threshold. We do have latency values to work with, and there might be values in the stepper data, but I haven't looked into it – and I am not willing to fry another CPU.

#553
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Hey guys. So wow, 28 pages and counting. The idea of this thread is great, but it really is hella confusing, possibly a lot of extra stuff not needed? I guess that's just the way threads go anyways. :(


So I'll try to do proper speedstepping later, but for now this has made me extremely happy that her computer's CPU fan doesn't kick into high speed for no reason. Hopefully this has been helpful to some people.

Take care,

-Stell


Thanks Stell

and I agree - there's a lot thats needs to be updated in the first post - I'll try to get round to it soon :)

D.

There is no such thing as a "threshold" in terms of Intel Speedstep Technology. There is one in VoodooPower but that is the refresh threshold. You have latency values to work with. That's all.


So you say - it is what it is ?

#554
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So you say - it is what it is ?

Like I said – I was still editing my post hen you replied – there might be in the stepper data, but I am currently unaware of it. At least until someone goes mad and starts to edit the stepper data.

#555
mitch_de

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There is no such thing as a "threshold" in terms of Intel Speedstep Technology. There might be one in VoodooPower but my guess is that this is a refresh threshold. We do have latency values to work with, and there might be values in the stepper data, but I haven't looked into it – and I am not willing to fry another CPU.

I also think that that threshold is an thing which the software must compute. IntelSpeedStep does only support the hw environment for stepping, but has no "AI" when it has to step up/down - simple steps by can call of the software.
So somewhere must the threshold value also in AppleCPU usage. In that .plist of ACPI- (with that lots of modelnames, ctstates) there are only threshold for gpu to find, but not for cpu. I would say that that threshold is "hardcoded" in the code of AppleIntelCPU kext.

#556
stellarola

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Hate to add to the longest thread ever again, but I couldn't help myself. :)

So I've done some more testing and I just want to make it clear that my current mission is just to lower cpu temps whilst CPUPM is loaded in OS X, not speedstepping yet.

In my first test I added what roisoft wrote here to my DSDT, overwriting the CPU section. I also of course added the ICH7M LPC info to my ICH7 board to the PX40 section which is Gigabyte's name for LPCB. This resulted in lower temps when CPUPM was loaded and I was happy. HOWEVER if I overclocked the system, I'd receive the _CST failed message in verbose mode, and hence insanely hot temperatures. When I overclocked from 2.4ghz to 2.88ghz my temps were around the 65C mark!

I figured I'd check around some more and came across another injection which lead me to a post by Keeza. I took this section of the DSDT and added it to mine...

{
	Scope (_PR)
	{
		Processor (CPU0, 0x00, 0x00000410, 0x06) {}
		Processor (CPU1, 0x01, 0x00000410, 0x06) {}
	}

	Scope (\)
	{
		Name (CFGD, 0x040383F2)
		Name (PDC0, 0x80000000)
		Name (PDC1, 0x80000000)
		Name (PDC2, 0x80000000)
		Name (PDC3, 0x80000000)
	}

	Scope (_PR.CPU0)
	{
		Method (_CST, 0, NotSerialized)
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							,)
					}, 

					One, 
					Zero, 
					Zero
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							,)
					}, 

					0x02, 
					Zero, 
					Zero
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							,)
					}, 

					0x03, 
					Zero, 
					Zero
				}
			})
		}
	}

He also had a section of P-States, but I didn't add that part, I just wanted the basic CST section. Also, it's only for CPU0 technically but it applies itself to the other cores as well. Compiled properly and tried it out.

The result?

I can now overclock the CPU without worry of CST errors in verbose mode and therefore lower temperatures. Even lower than using a disabler kext.

Overclocking from 2.4ghz to 2.88ghz on an Intel E6600

Before Temp with CPUPM loaded and no CST/LPC injection - 60-65C

After Temp with CPUPM loaded and CST/LPC injection - 42-45C

Also to note with this other method I don't have any performance array section in IOREG, but that's expected. Good news is the temps are lower and it's overclocking/sleeping fine. I want to admit as well I didn't read much of this thread and I jumped in blindly. I'm sure some of what I'm do is incorrect, but it's working for me. :P

Take care,

-Stell

#557
stellarola

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Just got a message from a user saying the above code will hurt my cpu, anyone care to explain why? I'm humble, trust me. This is a learning experience after all. :)

He told me to use this instead:
{
	Scope (_PR)
	{
		Processor (CPU0, 0x00, 0x00000410, 0x06) {}
		Processor (CPU1, 0x01, 0x00000410, 0x06) {}
	}

	Scope (_PR.CPU0)
	{
		Method (_CST, 0, NotSerialized)
		{
			Return (Package (0x02)
			{
				One, 
				Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x1, 0x2, 0x0, 0x1,)},0x01,0x9D,0x3E8}
			})
		}
	}

	Scope (_PR.CPU1)
	{
		Method (_CST, 0, NotSerialized)
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, ,)},0x01,0x01,0x3E8}, 
				Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x08, 0x00, 0x414, ,)},0x02,0x01,0x1F4}, 
				Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x08, 0x00, 0x415, ,)},0x03,0x55,0x0FA} 
			})
		}
	}


-Stell

#558
tinush

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The next step I took was to inject a device id from AppleLPC which is supposed to help lower temperatures. I added the device id for ICH7M, because it seemed to be the closest to this board which is just ICH7. I added the device id in the PX40 section of the DSDT like this...

Device (PX40)
			{
				Name (_ADR, 0x001F0000)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", 
							Buffer (0x04)
							{
								0xB9, 0x27, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}


Hi there Stell

can you tell me what your device id is, i want to ad my device-id in the dsdt (id 3a18)
don't really know what to ad (also in the learning curve)

thnx
T

#559
mm67

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Hi there Stell

can you tell me what your device id is, i want to ad my device-id in the dsdt (id 3a18)
don't really know what to ad (also in the learning curve)

thnx
T


Anyone from the IONameMatch table will work. If you have 3a18 as default like me then you don't need to add anything to PX40.
Attached File  Screen_shot_2009_11_01_at_14.01.42.png   169.2KB   46 downloads

#560
blackosx

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I don't have PX40 in my DSDT, should I?

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