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Help installing Mojave on Xeon W-2175 and Asus WS C422 mobo

obus

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in OSx86 10.14 (Mojave)

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hi @obus

those Yes on PCI tab are pretty cosmetics stuff you can write in it what you want via ssdt

 

click on thunderbolt tab on the left side

you should see there also "no driver loaded" but your Tb works fine

 

I do not know with your kind of motherboard but with designare ex there was an IRQ problem with 2 internal gfx an 1 external in a tb box

 

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obus
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3 hours ago, fabiosun said:

hi @obus

those Yes on PCI tab are pretty cosmetics stuff you can write in it what you want via ssdt

 

click on thunderbolt tab on the left side

you should see there also "no driver loaded" but your Tb works fine

 

I do not know with your kind of motherboard but with designare ex there was an IRQ problem with 2 internal gfx an 1 external in a tb box

 

Yeah I know that the SSDT is cosmetic and that there is no driver loaded. I just wanted to show that my Thunderbolt AHCI controller was showing up in IOReg and in "About This Mac -> System Report -> PCI" as connected. Without SSDT hot swap is not working with my Buffalo disk but with SSDT hot swap is working like a treat.

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obus
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3 hours ago, khe91 said:

The Thunderbolt card is visible as PCI device.

And the USB ports on the eGPU work, so the Thunderbolt bus is connected.

Just the eGPU is not visible.

Try this settings in bios.

Only if you are running 1102 bios of course. (1202 bios is not invented yet:rolleyes:)

1102 black.CMO

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1 hour ago, obus said:

Yeah I know that the SSDT is cosmetic and that there is no driver loaded. I just wanted to show that my Thunderbolt AHCI controller was showing up in IOReg and in "About This Mac -> System Report -> PCI" as connected. Without SSDT hot swap is not working with my Buffalo disk but with SSDT hot swap is working like a treat.

For Hotplug is mandatory to have a correct ssdt

But his problem is different

He should check in windows if its card is working well

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51 minutes ago, fabiosun said:

For Hotplug is mandatory to have a correct ssdt

But his problem is different

He should check in windows if its card is working well

 

I don't need hot plug.

In Windows the eGPU is working.

 

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7 minutes ago, khe91 said:

 

I don't need hot plug.

In Windows the eGPU is working.

 

in bios have you put SL0 in TB bios option?

Have you attached a monitor on it?

could you see in windows list of all your GPU if there you see same exclamation warning point?

Could you put an IOREG with card connected?

 

 

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7 minutes ago, fabiosun said:

in bios have you put SL0 in TB bios option?

Have you attached a monitor on it?

could you see in windows list of all your GPU if there you see same exclamation warning point?

Could you put an IOREG with card connected?

 

 

 

SL0-No Security activated

monitor connected

no exclamation warning in Windows, says AMD RX580 GPU

 

Found the problem, have to remove the SSDT-ALL.aml from obus then the eGPU is recognised and working.

 

 

2 hours ago, obus said:

Try this settings in bios.

Only if you are running 1102 bios of course. (1202 bios is not invented yet:rolleyes:)

1102 black.CMO

 

hi @obus

 

Could you please point me in the right direction how to get PowerManagment working without your SSDT-ALL.aml since it interferes with eGPU.

 

Thanks

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eritius
eritius
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I've been working with @vit9696 and @PMheart on adding better support for Xeon Scalable (Skylake-SP) CPUs to Open Core. So far, that means treating them as a Xeon W and properly calculating their CPU frequency based on their Always Running Timer (ART) which runs at 25 Mhz rather than 24 Mhz which every other Intel Skylake or later CPU uses.

 

I also was finally able to get the Xeon Golds running without emulating or faking the CPUID and using the processors' native ID 0x050654. It turns out that XNU wants to have complete control over MSR 1AAh (MISC_PWR_MGMT). And like some other MSRs, it gets locked by the firmware. You can tell the MSR is locked if bit 13 (0x2000) is set. Looking at some of the MSR dumps in here, values like 0x403040 indicate that it's locked just like mine is. My motherboard had no BIOS settings to configure this lock, even hidden.

 

Writing to that MSR when it is locked causes a panic. Faking the CPUID and other patches served to avoid this code but did more than that. Instead, I added a patch that removes any attempts by XNU to write to MISC_PWR_MGMT. If you compile the latest Open Core and enable AppleXcpmExtraMsrs, this patch will now be applied.

https://github.com/acidanthera/OcSupportPkg/pull/12

 

At the moment, XNU only writes to MISC_PWR_MGMT if the CPU is a Xeon W (or Scalable). It attempts to enable SpeedShift (set 0x40) and HWP (unset bit 0), which you can configure from your BIOS. If MISC_PWR_MGMT's low byte is set to 0x40, then you're already in the state that XNU is trying to achieve.

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obus
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9 minutes ago, eritius said:

I've been working with @vit9696 and @PMheart on adding better support for Xeon Scalable (Skylake-SP) CPUs to Open Core. So far, that means treating them as a Xeon W and properly calculating their CPU frequency based on their Always Running Timer (ART) which runs at 25 Mhz rather than 24 Mhz which every other Intel Skylake or later CPU uses.

 

I also was finally able to get the Xeon Golds running without emulating or faking the CPUID and using the processors' native ID 0x050654. It turns out that XNU wants to have complete control over MSR 1AAh (MISC_PWR_MGMT). And like some other MSRs, it gets locked by the firmware. You can tell the MSR is locked if bit 13 (0x2000) is set. Looking at some of the MSR dumps in here, values like 0x403040 indicate that it's locked just like mine is. My motherboard had no BIOS settings to configure this lock, even hidden.

 

Writing to that MSR when it is locked causes a panic. Faking the CPUID and other patches served to avoid this code but did more than that. Instead, I added a patch that removes any attempts by XNU to write to MISC_PWR_MGMT. If you compile the latest Open Core and enable AppleXcpmExtraMsrs, this patch will now be applied.

https://github.com/acidanthera/OcSupportPkg/pull/12

 

At the moment, XNU only writes to MISC_PWR_MGMT if the CPU is a Xeon W (or Scalable). It attempts to enable SpeedShift (set 0x40) and HWP (unset bit 0), which you can configure from your BIOS. If MISC_PWR_MGMT's low byte is set to 0x40, then you're already in the state that XNU is trying to achieve.

@eritius and @mrmiller = true:)

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obus
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7 minutes ago, eritius said:

All looks good to me, on both the MSR patching and the CPU and timer frequency stuff. Can you post the readout from AppleIntelInfo as well?

Here we go.

By the way are you using CPUFriend.kext, TSCAdjustReset.kext or PikerAlphas FreqVectorsEdit.sh?

AppleIntelInfo.rtf

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For the first time I've got Turbo Ratio/Frequency over 4000 Mhz using the processors native ID 0x050654 when testing with CineBench. Earlier always stuck to max 3500 Mhz.

 

1471626760_Screenshot2019-08-27at11_34_28.thumb.png.a11ad4a5b0d4cf0504f1a410c93d3ced.png

 

Maximum Turbo Ratio/Frequency is 4300 Mhz on my Xenon W-2175.

 

OpenCore rock:s:hysterical:

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eritius
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8 hours ago, obus said:

Here we go.

By the way are you using CPUFriend.kext, TSCAdjustReset.kext or PikerAlphas FreqVectorsEdit.sh?

AppleIntelInfo.rtf

 

I'm using CPUFriend to patch AppleIntelMCEReporter because I have a dual processor setup (https://github.com/acidanthera/bugtracker/issues/424#issuecomment-512596034 ). I haven't edited any frequency vectors.

I'm also using TSCAdjustReset though I'm not sure it's doing anything useful.

That said, I still have lower benchmark scores than I'd expect for my processor. My single core speeds are below baseline. If I can get those to where they should be, the multicore speed should follow suit. Not quite sure where to look next or whether it's just a configuration thing on my end.

 

Your power info looks good vis-a-vis MISC_PWR_MGMT. Look at MISC_PWR_MGM: 0x403040. That means the MSR is locked (0x2000) as I suspected and any writes to it would be problematic. The flags indiciate it is configured for SpeedShift and HWP. And as a result, looks like that's all enabled too: IA32_PM_ENABLE is on and all the HWP fields below that are visible. Seems good!

 

8 hours ago, obus said:

Have you got your THB working yet?

 

I did. I had to downgrade to a GC-Alpine Ridge controller. I also had to reveal a bunch of hidden pages in my BIOS to get access to the Thunderbolt settings. I haven't gotten hotplug working but it's a desktop and I'm fine living without it for the moment.

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obus
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Hi all with C422 mobo:s.

 

Test this OC version 0.0.4 "as is". Don't remove anything not even the SSDT-ALL in ACPI-folder. If you need any other SSDT:s integrate them in SSDT-ALL otherwise you have to change in config.plist -> ACPI -> Add according to attached manual Configuration.pdf .  

(My SSDT-ALL.aml contains only SSDT-PLUG = 1 (XCPM) ,SSDT-EC-USBX (Buspower) and Method DTGP, and this should be default for all C422-boards)

You need to provide MLB,ROM,Serial and SystemUUID in config.plist -> Platforminfo -> Generic according to attached manual Configuration.pdf.

I still use FakeSMC instead of VirtualSMC because it works better with iStat. This is a debug version so if you have problems booting there will be log-file created in the root of the EFI-folder.

 

This EFI should work OOB. Test and give feedback.

EFI.zip

Configuration.pdf

Edited by obus
Attached Configuration.pdf
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