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[AMD] Yosemite Kernel Testing (for help use the Help Topic)

Duran Keeley

By Duran Keeley,
in OS X 10.10 (Yosemite)

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gils83
gils83
Posted
Posted

:)

 

les test kernel FX / APU et Athlon ssse3 n'ont aucun intérêt car ils fonctionnent parfaitement , le kernel de Bronya ou Andy suffisent largement , sauf iCloud qui est le problème ;)

 

vaut mieux se concentrer sur les vieux CPU K10 :)

 

kernel test FX / Athlon SSSE3 APU and have no interest because they work perfectly, the kernel Bronya and Andy than enough unless iCloud is the problem ;)


is better to focus on the old K10 CPU :)

 
 
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Andy Vandijck
Andy Vandijck
Posted
Posted

Not work with 10.10.2

Kernel Panic :(

Replace System.kext with the custom one. System.kext must match kernel version. Remember: version is stamped inside and matches the Darwin 13.2.0 whereas kernel is 13.0.0
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user78405
user78405
Posted
Posted

 

:)

 

les test kernel FX / APU et Athlon ssse3 n'ont aucun intérêt car ils fonctionnent parfaitement , le kernel de Bronya ou Andy suffisent largement , sauf iCloud qui est le problème ;)

 

vaut mieux se concentrer sur les vieux CPU K10 :)

 

kernel test FX / Athlon SSSE3 APU and have no interest because they work perfectly, the kernel Bronya and Andy than enough unless iCloud is the problem ;)

 

 

is better to focus on the old K10 CPU :)

 
 

 

i understand your enthusiasm on getting K10 support, but in my understanding they shouldn't continue the support on older AMD due to OS constrains on SSSE3, AVX1,2, SSE4-2 and older cpu's would not benefit on performance..they still need to get the library's to work first on every apps..due to differences of instructions on Intel and AMD FX but that easy can be fix by translating to the correct patches...and also on GPU need more attention to benefit yosemite...so it be wise to let them work on only FX and APU's cpus this is the only architect is similar to i7 Haswell...all others can't be fixed

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Meowthra
Meowthra
Posted
Posted
I analysis of binary files ImageIO and Webkit
 
Found 10.10 Including SSSE3 instructions opcode
but No SSE4.1 or SSE4.2 opcode
 
10.9.5 libJPEG.dylib have SSSE3 opcode
Webkit No SSSE3 instructions opcode
Others are MMX SSE SSE2 SSE3 opcode
 

ImageIO

 

10.9.5

/System/Library/Frameworks/ImageIO.framework/Versions/A/Resources/libJPEG.dylib
000000000001dd36         pmulhrsw   xmm4, xmmword [ds:0x23270]
000000000001e39d         pshufb     xmm3, xmmword [ds:0x233c0]

10.10

/System/Library/Frameworks/ImageIO.framework/Versions/A/ImageIO

000000000007f59e         pshufb     xmm1, xmm0
0000000000092bd9         pshufb     xmm0, xmmword [ds:0x1171c0]
00000000000ac2c9         pshufb     xmm0, xmmword [ds:0x117560]
 
/System/Library/Frameworks/ImageIO.framework/Versions/A/Resources/libJPEG.dylib
0000000000010a07         pshufb     xmm0, xmm1
0000000000010a29         phaddd     xmm1, xmm1
0000000000012531         pshufb     xmm0, xmm1
0000000000012553         phaddd     xmm1, xmm1
000000000001ebe5         pmulhrsw   xmm5, xmm7
000000000001ebff         pmulhrsw   xmm1, xmmword [ds:0x24270]
000000000001ec15         pmulhrsw   xmm0, xmmword [ds:0x24280]
000000000001ecba         pmulhrsw   xmm4, xmm7
000000000001eccb         pmulhrsw   xmm3, xmm1
/System/Library/Frameworks/ImageIO.framework/Versions/A/Resources/libOpenEXR.dylib
0000000000038bf5         palignr    xmm0, xmm1, 0x2 (0x66 0x0f 0x3a 0x0f 0xc1 0x02)
/System/Library/Frameworks/ImageIO.framework/Versions/A/Resources/libTIFF.dylib
0000000000025a32         pshufb     xmm0, xmm2
0000000000025a54         phaddd     xmm1, xmm1
0000000000025cfb         pshufb     xmm0, xmm2
0000000000025d1d         phaddd     xmm1, xmm1

Webkit

 

10.10

/System/Library/Frameworks/JavaScriptCore.framework/Versions/A/JavaScriptCore
000000000000bc90         pshufb     xmm0, xmm2
000000000003c1c4         phaddd     xmm2, xmm2
/System/Library/Frameworks/JavaScriptCore.framework/Versions/A/Libraries/libllvmForJSC.dylib
000000000020ba8d         phaddd     xmm0, xmm0
00000000004606a7         pshufb     xmm0, xmmword [ds:0x9f2480]
/System/Library/Frameworks/WebKit.framework/Versions/A/Frameworks/WebCore.framework/Versions/A/WebCore
0000000000bb556b         phaddd     xmm1, xmm1
0000000000c02280         pshufb     xmm0, xmm2
/System/Library/Frameworks/WebKit.framework/Versions/A/Frameworks/WebKitLegacy.framework/Versions/A/WebKitLegacy
000000000006f6d0         pshufb     xmm0, xmm2

Error Problem Should still be in SSSE3 Emulator 

 

Error range in
 
pshufb
pmulhrsw
phaddd
palignr
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gils83
gils83
Posted
Posted

i understand your enthusiasm on getting K10 support, but in my understanding they shouldn't continue the support on older AMD due to OS constrains on SSSE3, AVX1,2, SSE4-2 and older cpu's would not benefit on performance..they still need to get the library's to work first on every apps..due to differences of instructions on Intel and AMD FX but that easy can be fix by translating to the correct patches...and also on GPU need more attention to benefit yosemite...so it be wise to let them work on only FX and APU's cpus this is the only architect is similar to i7 Haswell...all others can't be fixed

 

Haswell, who cares, it will be 100% operational in a short time.

 

the aim is to allow people who do not have the means to buy Intel and / or AMD prefer to keep their old system.

 

Phenom / Athlon CPUs are still relevant and they deserve our attention; that is the purpose of the subject.

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carlo_67
carlo_67
Posted
Posted

kern.version: Darwin Kernel Version 14.0.0: 2015年 1月28日 周三 08時16分41秒 WET; Torachiyo:xnu-2782.1.97-SSSE3-TEST/BUILD/obj/RELEASE_X86_64

 

I thank
 
in most of the kext that no place here because then there's people that you trust and makes clever
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yakei
yakei
Posted
Posted

 

kern.version: Darwin Kernel Version 14.0.0: 2015年 1月28日 周三 08時16分41秒 WET; Torachiyo:xnu-2782.1.97-SSSE3-TEST/BUILD/obj/RELEASE_X86_64

 

and no problems with Safari, app store. Safari Picture Preview is correct, Picture correctly shown, it also no webkit used?

everything  ok ?

compatible with AMD K10 ?

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Andy Vandijck
Andy Vandijck
Posted
Posted

 

SSSE3 XMM 128bit OPCODE Mode
 
=================
66 0F 38 ?? Mode
=================
 
Instructions pshufb.....
 
opcode byte[0-3]
 
opcode[0-3] +  modrm (byte[4])  + ....
 
00 01 02 03 04
66 0F 38 ?? **
===================================
if modrm (byte[4]) < 40 (00 - 3F = 64)
 
byte size 0-4
0  1  2  3  4
66 0F 38 ?? **
example:
66 0f 38 00 00
pshufb  xmm0, xmmword ptr [rax]
===================================
if  modrm (byte[4])  > 3F (40 - 7F = 64)
 
byte size 0-5
0  1  2  3  4  5
66 0F 38 ?? ** XX
example:
66 0F 38 00 40 01
pshufb  xmm0, xmmword ptr [rax+1]
===================================
if  modrm (byte[4])  > 7F (80 - BF = 64)
 
byte size 0-8
0  1  2  3  4  5  6  4  8
66 0F 38 ?? ** XX XX XX XX
example:
66 0F 38 00 80 01 02 03 04
pshufb  xmm0, xmmword ptr [rax+4030201h]
===================================
if modrm (byte[4]) > BF (C0 - FF = 64)
 
byte size 0-4
0  1  2  3  4
66 0F 38 ?? **
example:
66 0F 38 00 C0
pshufb  xmm0, xmm0
===================================
 
 
 
=================
66 0F 3A 0F Mode
=================
Instruction palignr only
 
opcode byte[0-3]
 
opcode[0-3] +  modrm (byte[4]) + ....
00 01 02 03 04
66 0F 3A 0F **
===================================
if modrm (byte[4])  < 40 (00 - 3F = 64)
 
byte size 0-5
0  1  2  3  4  5
66 0F 3A 0F ** @@
byte[5] = imm
 
example:
66 0F 3A 0F 00 01
palignr xmm0, xmmword ptr [rax], 1
===================================
if modrm (byte[4])  > 3F (40 - 7F = 64)
 
byte size 0-6
0  1  2  3  4  5  6
66 0F 3A 0F ** XX @@
byte[6] = imm
 
example:
66 0F 3A 0F 40 01 02
palignr xmm0, xmmword ptr [rax+1], 2
===================================
if modrm (byte[4])  > 7F (80 - BF = 64)
 
byte size 0-9
0  1  2  3  4  5  6  7  8  9
66 0F 3A 0F ** XX XX XX XX @@
byte[9] = imm
 
example:
66 0F 3A 0F 80 01 02 03 04 05
palignr xmm0, xmmword ptr [rax+4030201h], 5
 
=========================================
if modrm (byte[4])  > BF (C0 - FF = 64)
 
byte size 0-5
0  1  2  3  4  5
66 0F 3A 0F ** @@
byte[5] = imm
 
example:
66 0F 3A 0F C0 01
palignr xmm0, xmm0, 1

66 0F 3A 0F FF 01
palignr xmm7, xmm7, 1
=========================================
 
XMM Regs mode --- modrm (byte[4]) 
 
xmm0 0x00-0x07 0x40-0x47 0x80-0x87 0xc0-0xc7
xmm1 0x08-0x0f 0x48-0x4f 0x88-0x8f 0xc8-0xcf
xmm2 0x10-0x17 0x50-0x57 0x90-0x97 0xd0-0xd7
xmm3 0x18-0x1f 0x58-0x5f 0x98-0x9f 0xd8-0xdf
xmm4 0x20-0x27 0x60-0x67 0xa0-0xa7 0xe0-0xe7
xmm5 0x28-0x2f 0x68-0x6f 0xa8-0xaf 0xe8-0xef
xmm6 0x30-0x37 0x70-0x77 0xb0-0xb7 0xf0-0xf7
xmm7 0x38-0x3f 0x78-0x7f 0xb8-0xbf 0xf8-0xff

「SSSE3 MM 64bit OPCODE Mode」 Please See Attach Files

 

4 modes opcode size is different

 

 

=========================================

adding:

=========================================
 

128bit

modrm (byte[4])  (0x40-0x7F) mode

    byte[5] Range 0x00-0x80(0-127)

 

64bit

modrm (byte[3]) (0x40-0x7F) mode

    byte[4] Range 0x00-0x80(0-127)

 

palignr IMM Range 0x00 - 0xff (0-255)

 

 

modrm (byte[4])  Regs example:
660f380000 pshufb  xmm0, xmmword ptr [rax]
660f380001 pshufb  xmm0, xmmword ptr [rcx]
660f380002 pshufb  xmm0, xmmword ptr [rdx]
660f380003 pshufb  xmm0, xmmword ptr [rbx]
660f380004 pshufb  xmm0, xmmword ptr [rax+rax] R10:R11
660f380005 pshufb  xmm0, xmmword ptr [R12:R15]
660f380006 pshufb  xmm0, xmmword ptr [rsi]
660f380007 pshufb  xmm0, xmmword ptr [rdi]

660f380008 pshufb  xmm1, xmmword ptr [rax]
660f380009 pshufb  xmm1, xmmword ptr [rcx]
660f38000A pshufb  xmm1, xmmword ptr [rdx]
660f38000B pshufb  xmm1, xmmword ptr [rbx]
660f38000C pshufb  xmm1, xmmword ptr [rax+rax] R10:R11
660f38000D pshufb  xmm1, xmmword ptr [R12:R15]
660f38000E pshufb  xmm1, xmmword ptr [rsi]
660f38000F pshufb  xmm1, xmmword ptr [rdi]

660f380010 pshufb  xmm2, xmmword ptr [rax]
....

 

Implementation code for old opemu:

const int palignr_getimm128(const unsigned char *bytep)
{
    int rv = 0;
    uint8_t modrm = bytep[4];
    
    if (modrm < 0x40)
    {
        rv = (int)bytep[5];
    } else if (modrm < 0x80) {
        rv = (int)bytep[6];
    } else if (modrm < 0xC0) {
        rv = (int)bytep[9];
    } else {
        rv = (int)bytep[5];
    }
    
    return (const int)rv;
}

const int palignr_getimm64(const unsigned char *bytep)
{
    int rv = 0;
    uint8_t modrm = bytep[3];
    
    if (modrm < 0x40)
    {
        rv = (int)bytep[4];
    } else if (modrm < 0x80) {
        rv = (int)bytep[5];
    } else if (modrm < 0xC0) {
        rv = (int)bytep[8];
    } else {
        rv = (int)bytep[4];
    }
    
    return (const int)rv;
}

/** Runs the ssse3 emulator. returns the number of bytes consumed.
 **/
int ssse3_run(uint8_t *instruction, x86_saved_state_t *state, int longmode, int kernel_trap)
{
    // pointer to the current byte we're working on
    uint8_t *bytep = instruction;
    int ins_size = 0;
    int is_128 = 0, src_higher = 0, dst_higher = 0;
    
    
    ssp_m128 xmmsrc, xmmdst, xmmres;
    ssp_m64 mmsrc,mmdst, mmres;
    
    
    /** We can get a few prefixes, in any order:
     **  66 throws into 128-bit xmm mode.
     **  40->4f use higher xmm registers.
     **/
    if(*bytep == 0x66) {
        is_128 = 1;
        bytep++;
        ins_size++;
    }
    if((*bytep & 0xF0) == 0x40) {
        if(*bytep & 1) src_higher = 1;
        if(*bytep & 4) dst_higher = 1;
        bytep++;
        ins_size++;
    }
    
    if(*bytep != 0x0f) return 0;
    bytep++;
    ins_size++;
    
    /* Two SSSE3 instruction prefixes. */
    if((*bytep == 0x38 && bytep[1] != 0x0f) || (*bytep == 0x3a && bytep[1] == 0x0f)) {
        uint8_t opcode = bytep[1];
        uint8_t *modrm = &bytep[2];
        uint8_t operand;
        ins_size += 2; // not counting modRM byte or anything after.
        
        if(is_128) {
            int consumed = fetchoperands(modrm, src_higher, dst_higher, &xmmsrc, &xmmdst, longmode, state, kernel_trap, 1, ins_size);
            operand = bytep[2 + consumed];
            ins_size += consumed;

            switch(opcode) {
                case 0x00:
                    //pshufb128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_shuffle_epi8_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x01:
                    //phaddw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hadd_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x02:
                    //phaddd128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hadd_epi32_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x03:
                    //phaddsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hadds_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x04:
                    //pmaddubsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_maddubs_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x05:
                    //phsubw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hsub_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x06:
                    //phsubd128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hsub_epi32_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x07:
                    //phsubsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_hsubs_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x08:
                    //psignb128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_sign_epi8_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x09:
                    //psignw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_sign_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x0A:
                    //psignd128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_sign_epi32_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x0B:
                    //pmulhrsw128(&xmmsrc,&xmmdst,&xmmres);
                    xmmres.i = ssp_mulhrs_epi16_REF(xmmdst.i, xmmsrc.i);
                    break;

                case 0x0F:
                    //palignr128(&xmmsrc,&xmmdst,&xmmres,(const int)operand);
                    xmmres.i = ssp_alignr_epi8_REF(xmmdst.i, xmmsrc.i, palignr_getimm128(bytep));
                    ins_size++;
                    break;

                case 0x1C:
                    //pabsb128(&xmmsrc,&xmmres);
                    xmmres.i = ssp_abs_epi8_REF(xmmsrc.i);
                    break;

                case 0x1D:
                    //pabsw128(&xmmsrc,&xmmres);
                    xmmres.i = ssp_abs_epi16_REF(xmmsrc.i);
                    break;

                case 0x1E:
                    //pabsd128(&xmmsrc,&xmmres);
                    xmmres.i = ssp_abs_epi32_REF(xmmsrc.i);
                    break;

                default:
                    return 0;
            }

            storeresult128(*modrm, dst_higher, xmmres);
        } else {
            int consumed = fetchoperands(modrm, src_higher, dst_higher, &mmsrc, &mmdst, longmode, state, kernel_trap, 0, ins_size);
            operand = bytep[2 + consumed];
            ins_size += consumed;

            switch(opcode) {
                case 0x00:
                    //pshufb64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_shuffle_pi8_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x01:
                    //phaddw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hadd_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x02:
                    //phaddd64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hadd_pi32_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x03:
                    //phaddsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hadds_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x04:
                    //pmaddubsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_maddubs_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x05:
                    //phsubw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hsub_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x06:
                    //phsubd64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hsub_pi32_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x07:
                    //phsubsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_hsubs_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x08:
                    //psignb64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_sign_pi8_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x09:
                    //psignw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_sign_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x0A:
                    //psignd64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_sign_pi32_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x0B:
                    //pmulhrsw64(&mmsrc,&mmdst,&mmres);
                    mmres.m64 = ssp_mulhrs_pi16_REF(mmdst.m64, mmsrc.m64);
                    break;

                case 0x0F:
                    //palignr64(&mmsrc,&mmdst,&mmres, (const int)operand);
                    mmres.m64 = ssp_alignr_pi8_REF(mmdst.m64, mmsrc.m64, palignr_getimm64(bytep));
                    ins_size++;
                    break;

                case 0x1C:
                    //pabsb64(&mmsrc,&mmres);
                    mmres.m64 = ssp_abs_pi8_REF(mmsrc.m64);
                    break;

                case 0x1D:
                    //pabsw64(&mmsrc,&mmres);
                    mmres.m64 = ssp_abs_pi16_REF(mmsrc.m64);
                    break;

                case 0x1E:
                    //pabsd64(&mmsrc,&mmres);
                    mmres.m64 = ssp_abs_pi32_REF(mmsrc.m64);
                    break;

                default:
                    return 0;
            }

            storeresult64(*modrm, dst_higher, mmres);
        }
        
    } else {
        // opcode wasn't handled here
        return 0;
    }
    
    return ins_size;
}

I'm currently working on the opemu mark 4.

It even supports relative displacement (disp8 / disp32).

I just finished adaptations to the code and I'm ready to start compiling the code.

If all goes well, new kernel in a short while.

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Andy Vandijck
Andy Vandijck
Posted
Posted

New opemu mark IV built and ready for testing.

It's based on latest libudis86 my way...

I also implemented the missing disp8 and disp32 relative displacement code.

I also added the code required for proper immediate fetching...

This one should work pretty cool!

I'm hoping no more pixel bug...

Download below.

Previous opemu is still in place but new one is standard.

Report after test please...

Lets hope the eight build is what we need...

BTW: I initialized a Github repo containing latest code.

https://github.com/andyvand/XNU-AnV

This will always contain latest available...

BSA_YOS_R8.zip

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yakei
yakei
Posted
Posted

New opemu mark IV built and ready for testing.

It's based on latest libudis86 my way...

I also implemented the missing disp8 and disp32 relative displacement code.

I also added the code required for proper immediate fetching...

This one should work pretty cool!

I'm hoping no more pixel bug...

Download below.

Previous opemu is still in place but new one is standard.

Report after test please...

Lets hope the eight build is what we need...

BTW: I initialized a Github repo containing latest code.

https://github.com/andyvand/XNU-AnV

This will always contain latest available...

BSA_YOS_R8

 

Hi Andy, sorry kernel panic.

 

Best Regards

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carlo_67
carlo_67
Posted
Posted

New opemu mark IV built and ready for testing.

It's based on latest libudis86 my way...

I also implemented the missing disp8 and disp32 relative displacement code.

I also added the code required for proper immediate fetching...

This one should work pretty cool!

I'm hoping no more pixel bug...

Download below.

Previous opemu is still in place but new one is standard.

Report after test please...

Lets hope the eight build is what we need...

BTW: I initialized a Github repo containing latest code.

https://github.com/andyvand/XNU-AnV

This will always contain latest available...

good in 10.10.2
boot and shutdown ok
but creates problems in graphics screensaver
Schermata 2015-01-31 alle 18.55.33.png
 
carlo_67
 
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Andy Vandijck
Andy Vandijck
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good in 10.10.2
boot and shutdown ok
but creates problems in graphics screensaver
 
carlo_67
 

 

And the rest of the graphics?

Safari / Desktop / App Store / etc...

EDIT: Desktop look fine, screenshot too... yeah!

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user78405
user78405
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we all are getting confuse of which kernel to download for FX and did they fix the GPU sluggish performance ???????? 

its better to separate the kernels for FX and older AMD..You can't combine into one kernel due to difference of architect...When you fixing one thing for that older cpu then you end up breaking the newer cpu as well 

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