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DSDT - Vanilla Speedstep - Generic Scope (_PR)


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post-375259-1278665787_thumb.png

 

First you use lspci to find address of your LPC controller, then you use setpci command to read a specific register, on ICH10 that register is A6 and register is 8 bits long so I use sudo setpci -s 0:1f.0 0xa6.b. Let's say result from command is 80, I open Calculator, put it to Programmer mode and input value 80. From the picture you can see that bit 7 is set.

post-375259-1278666351_thumb.png

 

 

I tried it and it appears whatever c-state that is its not set. I got 00 as output. Which I guess means its not set. Or does it?

 

What exactly do c-state do? I know thats a noob question but I am a noob to this. Do they control temps somehow, or are they used to set sleeps states in the CPU or something like that.

 

Also do you have any comment on my experiment above? I was able to get pretty damn far with a MB4,1 DSDT during boot. I need guidelines on properly editing the DSDT. Like a rule book. I want to add as much of the MB4,1 DSDT to my own to properly get speedstep working. Is that a good idea or crazy? Much of the kings and others workarounds such as DGDT method are part of the Mac DSDT's so I am surprised someone with a really close matching system has not tried to make an almost 100% apple DSDT. Or have they. I can not find a good guide on making your own custom edits.

 

Does anyone have one? Or can they lend me some pointers here. I'm stumbling in the dark.

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I tried it and it appears whatever c-state that is its not set. I got 00 as output. Which I guess means its not set. Or does it?

 

What exactly do c-state do? I know thats a noob question but I am a noob to this. Do they control temps somehow, or are they used to set sleeps states in the CPU or something like that.

 

Also do you have any comment on my experiment above? I was able to get pretty damn far with a MB4,1 DSDT during boot. I need guidelines on properly editing the DSDT. Like a rule book. I want to add as much of the MB4,1 DSDT to my own to properly get speedstep working. Is that a good idea or crazy? Much of the kings and others workarounds such as DGDT method are part of the Mac DSDT's so I am surprised someone with a really close matching system has not tried to make an almost 100% apple DSDT. Or have they. I can not find a good guide on making your own custom edits.

 

Does anyone have one? Or can they lend me some pointers here. I'm stumbling in the dark.

 

Where exactly did you find that bit, what datasheet and which page ?

 

For C-states read this for starters : http://www.hardwaresecrets.com/article/611

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Where exactly did you find that bit, what datasheet and which page ?

 

For C-states read this for starters : http://www.hardwaresecrets.com/article/611

 

Thanks for the c-state brief. Thats what i thought they were low power states for the CPU..

 

As for what I read. I cant recall what I was looking at now. I googled ICH8M and got a few docs.

 

one of those was this one. http://www.intel.com/assets/pdf/datasheet/313056.pdf

 

It was either this one or one of the others that led me to believe I had that bit you were talking about. I might have been wrong. Ultimately I just want to see what c-states I have working and present. Speedstep is not working for me as expected. I currently have a froze step right now stuck at 2300mhz every time I boot. So my cpu is not stepping at all. I have not made any changes that would make this break as it was working before. I believe the real problem lies in the DSDT as I said before. It seems that with each boot speedstep either decides to load fully or not and I think it lies in what Master Chief has said about SBUS. That was in my previous post. I think I need to clear that up and then Ill have speedstep working better. Currently my system is load 4 CPU profiles. I think its randomly picking one to load of the 4 or something like that.

 

See my last post for details on the profile mismatch idea.

 

Thanks

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Hello guys,

 

you can easily apply this patch to your DSDT using this editor.

 

Here is the patch in the automated patcher format

SpeedStep.zip

Choose cpu0-3 if your DSDT has CPU0, CPU1, CPU2 and CPU3

 

Choose cpu1-4 if your DSDT has CPU1, CPU2, CPU3 and CPU4

 

There are files with 3 and 4 P-states, you just have to fill the FID and VID values for each state. If you add more states, remember to fix the package size.

 

Here for the Q6600 CPU

Q6600.zip

And here the LPC device-id patch, if you need it

LPC.txt.zip

Hope it helps the less experienced with DSDT patching.

 

Regards.

 

Many Thanks for this oldnapalm - I'm sure it will make things much easier for a lot of people !

 

;)

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Please help!

 

I am trying to change FID/VID value in DSDT but it doesn't affect anything.

 

No matter what I write in my DSDT I have have the following FID/VID values:

State 1: 0x0821

State 2: 0x071E

State 3: 0x061A

 

Please have a look and see if there is any reasons why my FID/VID changes in DSDT never happens.

 

I check with both VoodooMonitor and PstateChanger.

 

Thanks a lot!

 

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (Package (0x03)
               {
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x0825, // FF = FID, VV = VID
                       Zero    // P-state 0
                   }, 
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x0821, // FF = FID, VV = VID
                       One     // P-state 1
                   }, 
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x0710, // FF = FID, VV = VID
                       0x02    // P-state 2
                   }
               })
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (Package (0x05)
               {
                   0x05, 
                   Zero, 
                   Zero, 
                   0xFC, 
                   0x04
               })
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x02)
               {
                   One, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               0x01,               // Access Size
                               )
                       }, 
                       One, 
                       0x9D, 
                       0x03E8
                   }
               })
           }
       }
       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x04)
               {
                   0x03, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 
                       One, 
                       Zero, 
                       0x03E8
                   }, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000414, // Address
                               ,)
                       }, 
                       0x02, 
                       One, 
                       0x01F4
                   }, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000415, // Address
                               ,)
                       }, 
                       0x03, 
                       0x55, 
                       0xFA
                   }
               })
           }
       }
       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
   }

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I am trying to change FID/VID value in DSDT but it doesn't affect anything.

 

No matter what I write in my DSDT I have have the following FID/VID values:

State 1: 0x0821

State 2: 0x071E

State 3: 0x061A

 

Please have a look and see if there is any reasons why my FID/VID changes in DSDT never happens.

 

I check with both VoodooMonitor and PstateChanger.

The values you put in DSDT won't show in VoodooMonitor and PstateChanger. You should use PstateChanger to find FID and VID values to put in DSDT, then remove kext voodoopstate and use VoodooMonitor to check if frequency and voltage change according to CPU usage.

 

For what I understand your _PSS should be:

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (Package (0x03)
               {
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x0821, // FF = FID, VV = VID
                       Zero    // P-state 0
                   }, 
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x071E, // FF = FID, VV = VID
                       One     // P-state 1
                   }, 
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x061A, // FF = FID, VV = VID
                       0x02    // P-state 2
                   }
               })
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (Package (0x05)
               {
                   0x05, 
                   Zero, 
                   Zero, 
                   0xFC, 
                   0x04
               })
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x02)
               {
                   One, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               0x01,               // Access Size
                               )
                       }, 
                       One, 
                       0x9D, 
                       0x03E8
                   }
               })
           }
       }
       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x04)
               {
                   0x03, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 
                       One, 
                       Zero, 
                       0x03E8
                   }, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000414, // Address
                               ,)
                       }, 
                       0x02, 
                       One, 
                       0x01F4
                   }, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000415, // Address
                               ,)
                       }, 
                       0x03, 
                       0x55, 
                       0xFA
                   }
               })
           }
       }
       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
   }

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The values you put in DSDT won't show in VoodooMonitor and PstateChanger. You should use PstateChanger to find FID and VID values to put in DSDT, then remove kext voodoopstate and use VoodooMonitor to check if frequency and voltage change according to CPU usage.

 

For what I understand your _PSS should be:

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (Package (0x03)
               {
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x0821, // FF = FID, VV = VID
                       Zero    // P-state 0
                   }, 
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x071E, // FF = FID, VV = VID
                       One     // P-state 1
                   }, 
                   Package (0x06)
                   {
                       Zero, 
                       Zero, 
                       0x10, 
                       0x10, 
                       0x061A, // FF = FID, VV = VID
                       0x02    // P-state 2
                   }
               })
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (Package (0x05)
               {
                   0x05, 
                   Zero, 
                   Zero, 
                   0xFC, 
                   0x04
               })
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x02)
               {
                   One, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               0x01,               // Access Size
                               )
                       }, 
                       One, 
                       0x9D, 
                       0x03E8
                   }
               })
           }
       }
       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x04)
               {
                   0x03, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 
                       One, 
                       Zero, 
                       0x03E8
                   }, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000414, // Address
                               ,)
                       }, 
                       0x02, 
                       One, 
                       0x01F4
                   }, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000415, // Address
                               ,)
                       }, 
                       0x03, 
                       0x55, 
                       0xFA
                   }
               })
           }
       }
       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Method (_PSS, 0, NotSerialized)
           {
               Return (^^CPU0._PSS ())
           }
           Method (_PSD, 0, NotSerialized)
           {
               Return (^^CPU0._PSD ())
           }
           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
   }

 

I thought I could just calculate a p-state with p-states calculator and override the default voltage that way?

 

Does that mean that while using speedstep there is no way to higher the vcore while overcloking?

 

Basically I can only overclock on stock voltage if using speedstep?

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I thought I could just calculate a p-state with p-states calculator and override the default voltage that way?

 

Does that mean that while using speedstep there is no way to higher the vcore while overcloking?

 

Basically I can only overclock on stock voltage if using speedstep?

 

Voltage values for P-states in dsdt always stay the same, you change Vcore setting only in bios when you are overclocking. You can dump your SSDT tables using some different Vcore settings in bios and you will see that VID values for P-states don't change.

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Voltage values for P-states in dsdt always stay the same, you change Vcore setting only in bios when you are overclocking. You can dump your SSDT tables using some different Vcore settings in bios and you will see that VID values for P-states don't change.

 

Thanks a lot!

 

Works fine overcloking.

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Finally after days of experimenting it looks like i got C-states working.

 

Reading the ACPI specs gave me the impression there could be either SystemIO or

FFixed registers to be used in CST-objects as reference for OSPM to transit cpu into different

states.

It never happend with SystemIO whatever i tried, maybe caused by lack of experience or

misinterpretation, i don't know.

 

@mm67

 

would you please be so kind and point me to where/how you found the 0xa6.b register ?

0:1f.0 is obvious but i couldn't find anything about the other in any datasheets.

That could probably help me to understand how to access registers in general.

 

thanks

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@mm67

 

would you please be so kind and point me to where/how you found the 0xa6.b register ?

0:1f.0 is obvious but i couldn't find anything about the other in any datasheets.

That could probably help me to understand how to access registers in general.

 

thanks

post-375259-1278947146_thumb.png

 

ICH10 datasheet, page 455. Interesting parts surrounded with red rectangles.

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Reading the ACPI specs gave me the impression there could be either SystemIO or

FFixed registers to be used in CST-objects as reference for OSPM to transit cpu into different

states.

It never happend with SystemIO whatever i tried, maybe caused by lack of experience or

misinterpretation, i don't know.

I have found the same, my assumption is that OSX reads FFixedHware addresses and ignores SystemIO addresses, at least on my Gigabyte board anyway.

 

I think mm67 found the same with his MSI board as well.

 

Added

 

At present, to the best of my knowledge if you have:

 

CStateinfo 1240105

Low temps

Vcore changes in marki

0xa6.b register returns 80 (for those that support deeper cstates)

 

then it appears that you have working cstates.

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At present, to the best of my knowledge if you have:

 

CStateinfo 1240105

Low temps

Vcore changes in marki

0xa6.b register returns 80 (for those that support deeper cstates)

 

then it appears that you have working cstates.

 

Mine returns 00 so I must not have deeper cstates.. How do I fix this?

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Mine returns 00 so I must not have deeper cstates.. How do I fix this?

 

Does your processor support deeper C States?

 

If so then its probable that your CState addresses are not declared properly.

 

Go Here to read of my experience. What I know of this subject was discussed not long ago.

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Does your processor support deeper C States?

 

If so then its probable that your CState addresses are not declared properly.

 

Go Here to read of my experience. What I know of this subject was discussed not long ago.

 

I have a T9300 on a ICH8m laptop. Perhaps it does not support these deeper cstates. Thanks for the info.

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CStateinfo 1240105

Low temps

Vcore changes in marki

0xa6.b register returns 80 (for those that support deeper cstates)

 

then it appears that you have working cstates.

 

Idle i'm around 35, Vcore changes under load and register returns 80...

 

But !

 

Terminal shows me 19136773 for CSTInfo , and in IORegistry at ACPI_SMC_PlatformPlugin i get

1240105 !

 

Shouldn't these values be the same ?

 

@ 00diabolic

 

i found this info for your CPU, i hope it helps

http://www.phoronix.com/scan.php?page=arti...enryn&num=3

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Idle i'm around 35, Vcore changes under load and register returns 80...

 

But !

 

Terminal shows me 19136773 for CSTInfo , and in IORegistry at ACPI_SMC_PlatformPlugin i get

1240105 !

 

Shouldn't these values be the same ?

 

Same results for me - good question, wouldn't mind knowing the difference myself!

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mmmm Well then what can I do to get them working? I clearly have some of the c-states working. I think at least 2 or 3 of them, not sure since there is no way to tell which ones are active and/or available in OSX from what I have found. I get the 19136773 when I grep CST, and in IORegistry get the 1240105 for cstinfo, but is that all there is to check?

 

I think this might also be related to why I cant sleep my system.

advice?

 

 

@!Xabbu Thanks for the info!!

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...but is that all there is to check?

 

advice?

 

As i stated i didn't get C4 working untill i changed type of register to

FFixedHW. Found them in my SSDT dumps and played around with them.

 

Read post #1737 and following posts.

 

Use mark-i to check Vcore changes.

When terminal returns with 80 you're there !

 

good luck !

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As i stated i didn't get C4 working untill i changed type of register to

FFixedHW. Found them in my SSDT dumps and played around with them.

 

Read post #1737 and following posts.

 

Use mark-i to check Vcore changes.

When terminal returns with 80 you're there !

 

good luck !

 

Ohh yeah this is what mm67 was helping you with. I confirmed I have the bit but what do I do next? read on...

 

This is from the ICH8 datasheet. Same as ICH10 almost.

 

9.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration Lock

Register

Offset Address: A6h Attribute: R/W

Default Value: 00h Size: 8-bit

Lockable: No Usage: ACPI

Power Well: Core

This register is used to enable new C-state related modes.

 

Anyway what did you change in your SSDT dump exactly? Once you made that change I'm guessing you used anval bootloader to boot the edits SSDT right? Dont think asereBLN can boot edited SSDT's.

 

correct me if I'm wrong.

 

Thanks

 

@ALL

 

In another section I noticed front side bus interrupt delivery.

See: http://www.intel.com/assets/pdf/datasheet/313056.pdf

 

Sec 5.9.4 page 147

 

It talks about a bit that can change FSB on the fly. Now I am not sure if I can use this to combat my FSB problem in OSX. My front side bus is reported as 736mhz as some of you might know, supposed to be 800. Anyway it affects my CPU and ram also and Lowers my benchmark scores by 25%.

 

If one of you guys could clue me in and tell me if this is something I can use to address my problem or not? I have been looking for a DSDT or SSDT table edit I can do to get my 800FSB working. So far no luck.

 

Thanks...

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