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DSDT - Vanilla Speedstep - Generic Scope (_PR)

FKA

By FKA,
in Power Management

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keeza
keeza
Posted
Posted
Thanks.

but how does I dump the FACP table from his ACPI output ? With everest and Windows ? And the Post with the C1 to C4 State, I will search ^^

 

I don't usually provide SSDT code for others due to the nature of what we do and the risk involved with any mod we make to the dsdt, but I believe that the code you need to add is below:

		 Name (CST, Package (0x05)
	 {
		 0x04,   //<--number of C-States C1,C2,C4
		 Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x01,)},One,One,0x03E8}, 
		 Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000010,0x02,)},0x02,One,0x01F4}, 
		 Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000020,0x03,)},0x03,0x11,0xFA},
		 Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000030,0x04,)},0x04,0x39,0x64}
	 })

 

You also need to check in BIOS what C States are supported i.e. C1E C2E C3E C4E etc (my processor on supports C1, C2 and C4).

I think you are good for 4 C-Sates which I've included in the above code based on your SSDT.

 

If you are happy with the above code add it to your dsdt (you can use mine or many others to guide you- you need to use the same name method for the other core i.e. alias) and try it out. Try this code in terminal and post back your result - should be 00 or 80 or something like that.

 

sudo setpci -s 0:1f.0 0xa6.b

 

I personally believe that, based on my very limited knowledge of the ACPI specs that FFixedHW addresses are the way to go with CStates as opposed to System IO addresses that my original dumps generated. Since declaring CStates as FFixedHardware addresses it appears that all of my C-States are working. My assumption is that SystemIO addresses cause CState parity which in my case resulted in C1 only.

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dh.taran
dh.taran
Posted
Posted

Hi guys..k I need some suggestions

 

Its quiet obvious that IASLME is the recommended tool for compiling de-compiling dsdt's. However, what I wanna know what ahould I use to edit them, the simple text editor?

 

And the main question, like in DSDTSE (not recommended I know, Im not using it) there are certain patches/fixes which you are supposed to include in your dsdt. Is there some other tool/place where you can get the right patches/fixes from..to include in your dsdt.

 

I know, very n00bish question, but had to start the right way.

 

Thanks a ton.

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Freaky Chokra
Freaky Chokra
Posted
Posted
Hi guys..k I need some suggestions

 

Its quiet obvious that IASLME is the recommended tool for compiling de-compiling dsdt's. However, what I wanna know what ahould I use to edit them, the simple text editor?

 

And the main question, like in DSDTSE (not recommended I know, Im not using it) there are certain patches/fixes which you are supposed to include in your dsdt. Is there some other tool/place where you can get the right patches/fixes from..to include in your dsdt.

 

I know, very n00bish question, but had to start the right way.

 

Thanks a ton.

Hi dh.taran.

 

Long time.... Dude!

Finally looks like you dug out iASLMe for yourself.

 

There are infinite choices.

  1. Built in Textedit.app
  2. TextWrangler
  3. Eclipse <----- Which I've been recommended/suggested recently by a programmer.
  4. And many more.

The only thing is, the DSDT Code should be free of any non-printing characters, spaces, tabs, etc. that would screw up during compilation.

 

Regards,

Freaky Chokra :wallbash:

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T-Bone90
T-Bone90
Posted
Posted
You also need to check in BIOS what C States are supported i.e. C1E C2E C3E C4E etc (my processor on supports C1, C2 and C4).

I think you are good for 4 C-Sates which I've included in the above code based on your SSDT.

Thanks a lot. Here is my CPU: http://processorfinder.intel.com/details.aspx?sSpec=SLGTE, it support C1E, C2E, C3E and C4E.

 

If you are happy with the above code add it to your dsdt (you can use mine or many others to guide you- you need to use the same name method for the other core i.e. alias) and try it out. Try this code in terminal and post back your result - should be 00 or 80 or something like that.

 

sudo setpci -s 0:1f.0 0xa6.b

 

I personally believe that, based on my very limited knowledge of the ACPI specs that FFixedHW addresses are the way to go with CStates as opposed to System IO addresses that my original dumps generated. Since declaring CStates as FFixedHardware addresses it appears that all of my C-States are working. My assumption is that c addresses cause CState parity which in my case resulted in C1 only.

What do you mean with "you need to use the same name method for the other core i.e. alias)"

Do you mean this part

		Processor (CPU0, 0x01, 0x00000810, 0x06)
	{
		Alias (PSS, _PSS)
		Alias (PSD, _PSD)
		Alias (CST, _CST)
	}

	Processor (CPU1, 0x02, 0x00000810, 0x06)
	{
		Alias (PSS, _PSS)
		Alias (PSD, _PSD)
		Alias (CST, _CST)
	}

	Method (NOTI, 0, Serialized)
	{
		Notify (CPU0, 0x80)
		Sleep (0x64)
		Notify (CPU0, 0x81)
		Notify (CPU1, 0x80)
		Sleep (0x64)
		Notify (CPU1, 0x81)
	}

 

When I post the code in the Terminal, it shows "sudo: setpci: command not found".

 

And the last, you mean also FFixedHW is better than SystemIO ?

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keeza
keeza
Posted
Posted
Thanks a lot. Here is my CPU: http://processorfinder.intel.com/details.aspx?sSpec=SLGTE, it support C1E, C2E, C3E and C4E.

Sweet, I had since checked however, to ensure my post is as accurate as I can be.

 

What do you mean with "you need to use the same name method for the other core i.e. alias)"

Do you mean this part

Processor (CPU0, 0x01, 0x00000810, 0x06)

{

Alias (PSS, _PSS)

Alias (PSD, _PSD)

Alias (CST, _CST)

}

 

Processor (CPU1, 0x02, 0x00000810, 0x06)

{

Alias (PSS, _PSS)

Alias (PSD, _PSD)

Alias (CST, _CST)

}

 

Yes thats correct. Using the Name PSS PSD and CST allows us to use Alias for the other cores, in your case two cores, in my case four. It saves us having to replicate the same info over and over for each core. I fondly remember the days when our SSDT's were about a squizzillion lines long.... :)

 

 

When I post the code in the Terminal, it shows "sudo: setpci: command not found".

OK, you probably don't have PCTools installed then. This will allow you to update your PCI info - helpful if you have unrecognised devices when running LSPCI. I believe I actually received help on this very subject along with how to update your PCI devices in this very thread.

 

To get PCITools run OSX86Tools, it will give you the option to install it.

 

To update PCI Devices...

sudo update-pciids

 

And the last, you mean also FFixedHW is better than SystemIO ?

In my case with my board, for each C-State I got a SystemIO address with my SSDT dumps with the exception of C1 which is a FFixedHW address.

It was only since I added all C-States with FFixedHW addresses that all 3 of my C-states work (C1 works by default if you have CStateinfo in Ioreg but not necessarily C2, C3, C4 etc). My temps are running at 33-39 degrees at idle, the lowest I've ever got it.

 

My theory:

I posted on the Gigabyte fix forum and asked about my assumption regarding SystemIO addresses.

I believe that the SystemIO address reads the P_BLK register for C-State info. The P_BLK register requires all cores to be the same, i.e. CPU0 CPU1 CPU2 etc must load the same cstate/s. But I got no response on it so its still a theory.

 

If CPU0 only supports C1 (which I read somewhere but can't find where) then all other CPU cores will support CPU1 only (C2 C3 etc will be disabled). Therefore all other CStates will be disabled if using SystemIO addresses. If you use FFixedHW addresses then CState parity can be overridden and all declared CStates should work.

 

I'm currently testing this with my new dsdt which I will upload to my sig.

 

P.S. I'm playing around with some latency and power settings in my FFixedHW addresses so change them to match yours. You have been warned.

 

P.P.S. Any comments regarding SystemIO vs FFixedHW addresses in relation to working CStates are welcome.

 

P.P.P.S. If BIOS flashing project proves successful then DSDT related CState and PState worries will be a thing of the past! :)

 

Hi guys..k I need some suggestions

 

Its quiet obvious that IASLME is the recommended tool for compiling de-compiling dsdt's. However, what I wanna know what ahould I use to edit them, the simple text editor?

 

And the main question, like in DSDTSE (not recommended I know, Im not using it) there are certain patches/fixes which you are supposed to include in your dsdt. Is there some other tool/place where you can get the right patches/fixes from..to include in your dsdt.

 

I know, very n00bish question, but had to start the right way.

 

Thanks a ton.

 

DSDTSE is useful for basic fixes as a starting point.

 

Here is a useful link also **Link is dead** Luckily I saved a copy in my Hack Archive folder :)

 

Edit:

Attached below is a html version of the broken link above.

 

For edits I use Araxis Merge, couldn't be without it. Tried Diffmerge also but found it a bit clunky to use.

DSDT_Fixes.html

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mikeetastic
mikeetastic
Posted
Posted

guys i need help! i changed board from Gigabyte EP45 to Zotac G43 ITX (same Q8400 processor).. now can i copy/paste my PSS tables from giga to zotac? i dont want to experiment so i will ask first just to be sure.

 

here's how it looks on my gigabyte before

 

Scope (_PR)
   {
       Name (PSS, Package (0x03)
       {
           Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x0825, Zero },
		Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x071E,  One },
		Package (0x06) { Zero, Zero, 0x0A, 0x0A, 0x0616, 0x02 }
       })

       Name (PSD, Package (0x05)
       {
           0x05, Zero, Zero, 0xFC, 0x04
       })

       Name (CST, Package (0x04)
       {
           0x03, 
           Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, ,)}, One, One, 0x03E8}, 
		Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x414, ,)}, 0x02,One, 0x01F4}, 
		Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x415, ,)}, 0x03,0x55,0xFA}
       })

       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }
   }

 

can i just safely copy this in my ICH10 Zotac? this is how it looks on my Zotac all of them are 0x00000000 while on my gigabyte it's 0x00000410

 

Scope (\_PR)
{
	Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) {}
	Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00) {}
	Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00) {}
	Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00) {}
}

 

Thanks!

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keeza
keeza
Posted
Posted
can i just safely copy this in my ICH10 Zotac? this is how it looks on my Zotac all of them are 0x00000000 while on my gigabyte it's 0x00000410

 

Scope (\_PR)
 {
	 Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) {}
	 Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00) {}
	 Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00) {}
	 Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00) {}
 }

 

Thanks!

 

You are missing the P_BLK register address in the above code. Not sure why.

 

One explanation, did you have C-states in BIOS enabled before dumping the Zotac code?

 

If you did, then the P_BLK address is easily obtained form your IO address.

 

Using your Gigabyte example in your original post you had SystemIO addresses of 414 & 415 for your CState registers.

ACPI specs say that these IO addresses are your P_BLK address plus 4 and 5 respectively therefore the P_BLK address is 410.

 

So you can check the above using your SSDT dumps.

 

By memory Quad core is 410 and Core2 is 810???

 

ADDED:

if you are the type to want to double check page 449 Intel ICH10R datasheet

Just had a quick look at your processor its a quad core suporting C1E C2E and C4E same as my Q9550. You can use my dsdt as a guide to help you.

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mikeetastic
mikeetastic
Posted
Posted
You are missing the P_BLK register address in the above code. Not sure why.

 

One explanation, did you have C-states in BIOS enabled before dumping the Zotac code?

 

If you did, then the P_BLK address is easily obtained form your IO address.

 

Using your Gigabyte example in your original post you had SystemIO addresses of 414 & 415 for your CState registers.

ACPI specs say that these IO addresses are your P_BLK address plus 4 and 5 respectively therefore the P_BLK address is 410.

 

So you can check the above using your SSDT dumps.

 

By memory Quad core is 410 and Core2 is 810???

 

ADDED:

if you are the type to want to double check page 449 Intel ICH10R datasheet

Just had a quick look at your processor its a quad core suporting C1E C2E and C4E same as my Q9550. You can use my dsdt as a guide to help you.

 

 

Thanks a lot Keeza but to be honest i just copied my dsdt for my EP45 and i believe yours is included on the list i compared so i dont know anything about it but now (on my Zotac) i promise i will learn everything before copying/applying a patch/code to my dsdt :rolleyes:

 

ill start with P_BLK? where is that coz i dont see it anywhere on my dsdt? and yes all are enabled including C State (i can choose C2-C3-C4) before dumping in linux and its still 0x00000000. here's a screenshot of my BIOS.

 

post-563478-1275111495_thumb.jpg

 

and here is my SSDT dump (hope i did it correctly) using this method at Projectosx

 

ACPI_Tables.zip

 

again, thanks a lot keeza and to all in advance.

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T-Bone90
T-Bone90
Posted
Posted
Yes thats correct. Using the Name PSS PSD and CST allows us to use Alias for the other cores, in your case two cores, in my case four. It saves us having to replicate the same info over and over for each core. I fondly remember the days when our SSDT's were about a squizzillion lines long.... :wallbash:

 

What I dont understand ? What I must chance to fix all the errors ?

 

 

And for SystemIO vs. FFixedHW.

 

I trust you because I need help and Idon't have Infos about this Things :-)

 

PS.: I have the BlockstorageDevice but I read, this kext I can fix in the DSDT. Is this the correct Thread: http://www.insanelymac.com/forum/index.php?showtopic=168014 for make the external ports to internal ?

 

PS2 ^^: I fix with DSDTSE the Powerbutton Fix, but it dont work. Any Idea ?

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keeza
keeza
Posted
Posted
Thanks a lot Keeza but to be honest i just copied my dsdt for my EP45 and i believe yours is included on the list i compared so i dont know anything about it but now (on my Zotac) i promise i will learn everything before copying/applying a patch/code to my dsdt ;)

 

ill start with P_BLK? where is that coz i dont see it anywhere on my dsdt? and yes all are enabled including C State (i can choose C2-C3-C4) before dumping in linux and its still 0x00000000. here's a screenshot of my BIOS.

 

post-563478-1275111495_thumb.jpg

 

and here is my SSDT dump (hope i did it correctly) using this method at Projectosx

 

ACPI_Tables.zip

 

again, thanks a lot keeza and to all in advance.

 

The P_BLK register for me is contained within my SSDT dumps within the CPU0CST, CPU1CST etc.

Yours however, only contains the same address for C1 in each of the CST files and no P_BLK register address.

Sorry but this is about as far as I can help you, maybe the board doesn't C-states or poorly implemented in your SSDT's, I don't know.

 

Try this Gigabyte Fix , there was a fair bit of work done by mm67 to get C-States working. I dont see how you could damage your CPU if you were to try it (monitor your temps before and after). Just make sure that you enter the correct PSS info for speedstepping. See FKA's tutorial at the beginning of the thread for more info. Check in Ioreg to see if CStateInfo appears, that will let you know if CStates are loaded.

 

What I dont understand ? What I must chance to fix all the errors ?

What is it that you are not sure of? The Name vs the Alias thing? There are many dsdt's floating around that use this method of declaring C-States mine included that you could adapt to yours. Also check out the work of MasterChief at the P5K thread.

And to what errors do you refer? Without further info I can't advise.

 

And for SystemIO vs. FFixedHW.

Everything I have to say (and know) about this refer to my previous post.

 

I trust you because I need help and Idon't have Infos about this Things :-)

I am by no means an expect and have received a lot of help myself but thanks anyway.

 

PS.: I have the BlockstorageDevice but I read, this kext I can fix in the DSDT. Is this the correct Thread: http://www.insanelymac.com/forum/index.php?showtopic=168014 for make the external ports to internal ?

I've used the dsdt fix in my dsdt, others prefer the kext option (currently using kext). I've not noticed any difference between the two but some have reported issues with the dsdt fix.

 

PS2 ^^: I fix with DSDTSE the Powerbutton Fix, but it dont work. Any Idea ?

Again to what fix do you refer? If you refer to the powerbutton sleeps computer fix then thats in my dsdt. If you mean the shutdown menu appears when you press the power button, doesn't work for me (and doesn't on my imac either)

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mikeetastic
mikeetastic
Posted
Posted
The P_BLK register for me is contained within my SSDT dumps within the CPU0CST, CPU1CST etc.

Yours however, only contains the same address for C1 in each of the CST files and no P_BLK register address.

Sorry but this is about as far as I can help you, maybe the board doesn't C-states or poorly implemented in your SSDT's, I don't know.

 

Try this Gigabyte Fix , there was a fair bit of work done by mm67 to get C-States working. I dont see how you could damage your CPU if you were to try it (monitor your temps before and after). Just make sure that you enter the correct PSS info for speedstepping. See FKA's tutorial at the beginning of the thread for more info. Check in Ioreg to see if CStateInfo appears, that will let you know if CStates are loaded.

 

decided to copy paste my PSS from gigabyte and its working (well i can see voodoomonitor change frequency), what still concerns me is if the values are correct :(

 

and looking at your CST it's totally different.

 

post-563478-1275190498_thumb.png

post-563478-1275190537_thumb.png

 

how do you guys get the values in red?

 

Scope (_PR)
   {
       Name (PSS, Package (0x03)
       {
           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x0825, 
               Zero
           }, 

           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x071E, 
               One
           }, 

           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x0616, 
               0x02
           }
       })
       Name (PSD, Package (0x05)
       {
           0x05, 
           Zero, 
           Zero, 
           0xFC, 
           0x04
       })
       [color="#FF0000"]Name (CST, Package (0x04)
       {
           0x03, 
           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x01,               // Bit Width
                       0x02,               // Bit Offset
                       0x0000000000000000, // Address
                       ,)
               }, 

               One, 
               One, 
               0x03E8
           }, 

           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000414, // Address
                       ,)
               }, 

               0x02, 
               One, 
               0x01F4
           }, 

           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000415, // Address
                       ,)
               }, 

               0x03, 
               0x55, 
               0xFA
           }
       })[/color]
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }
   }

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keeza
keeza
Posted
Posted
decided to copy paste my PSS from gigabyte and its working (well i can see voodoomonitor change frequency), what still concerns me is if the values are correct :(

Instructions to check/find out your pss values are at the beginning of this thread - you need to use pstate changer. Do your multiplier and voltages change as well? My temps are in the 33-39 range at idle so I presume that CStates is not working for you yet.

 

and looking at your CST it's totally different.

You're probably aware but PStates and CStates are two differnet things.

As I mentioned in one of my previous posts I'm experimenting with it so may be different to most. My experimentation yielded no results so will revert it back later.

 

how do you guys get the values in red?

My values to which you refer to were obtained via my SSDT dumps (linux). The FFixedHardware address is all zero in my original dumps. Without the modification of FfixedHardware addresses CStates wouldn't load. The SystemIO addresses for C2 and above don't work for me hence my change to all FFixedhardware addresses.

 

Some motherboards appear to do a better job than others in the writing of SSDT tables. The FFixed Hardware address of 1,2,0,1 that I use came from a MSI board care of another poster.

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mikeetastic
mikeetastic
Posted
Posted
Instructions to check/find out your pss values are at the beginning of this thread - you need to use pstate changer. Do your multiplier and voltages change as well? My temps are in the 33-39 range at idle so I presume that CStates is not working for you yet.

 

im sure its working because if i taken out the PSS code and remove NULLCPUPM kext temp is on the 50+.. also its hot from where im from and im also using a stock cooler :D

 

still my concern is am i safe using this code (right now im using it)? do i need to change/remove anything or just use Speedstep via kext :D

 

Scope (_PR)
   {
       Name (PSS, Package (0x03)
       {
           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x0825, 
               Zero
           }, 

           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x071E, 
               One
           }, 

           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x0616, 
               0x02
           }
       })
       Name (PSD, Package (0x05)
       {
           0x05, 
           Zero, 
           Zero, 
           0xFC, 
           0x04
       })
       Name (CST, Package (0x04)
       {
           0x03, 
           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x01,               // Bit Width
                       0x02,               // Bit Offset
                       0x0000000000000000, // Address
                       ,)
               }, 

               One, 
               One, 
               0x03E8
           }, 

           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000414, // Address
                       ,)
               }, 

               0x02, 
               One, 
               0x01F4
           }, 

           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000415, // Address
                       ,)
               }, 

               0x03, 
               0x55, 
               0xFA
           }
       })
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }
   }

 

lastly my BIOS has a C2 to C4 option (C2, C3, C4 and disable).. what will i choose in there?

 

post-563478-1275200336_thumb.jpg

 

Thanks all in advance for the reply and help.

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dh.taran
dh.taran
Posted
Posted

Thanks a tonnn Keeza :D

 

Araxis merge was a life saver.

 

I have my dsdt with audio, video, and networking, thanks to you.

 

One weird issue tho, my audio stutters very bad, cant listen to anything. Did a lil research and it seems liek I need C states...could you confirm that?

 

 

Im attaching my dsdt incase you get time to look if I did something wrong coz of which the audio stutters badly, its a alc889a audio chipset, and I ve tried all combinations of latest AppleHDA and HDAenabler but still the stuttering is very bad. If I use the backup SL copy to boot (without the speedstep code and the SAME * AppleHDA and HDAEnabler kexts) there is no audio stutter....weird speedstep.

 

audio_stutter.dsl.zip

 

Thanks a tonn man, you saved my life with that merge editor. :thumbsup_anim:

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keeza
keeza
Posted
Posted
Thanks a tonnn Keeza :rolleyes:

 

Araxis merge was a life saver.

 

I have my dsdt with audio, video, and networking, thanks to you.

 

One weird issue tho, my audio stutters very bad, cant listen to anything. Did a lil research and it seems liek I need C states...could you confirm that?

 

 

Im attaching my dsdt incase you get time to look if I did something wrong coz of which the audio stutters badly, its a alc889a audio chipset, and I ve tried all combinations of latest AppleHDA and HDAenabler but still the stuttering is very bad. If I use the backup SL copy to boot (without the speedstep code and the SAME * AppleHDA and HDAEnabler kexts) there is no audio stutter....weird speedstep.

 

audio_stutter.dsl.zip

 

Thanks a tonn man, you saved my life with that merge editor. :P

 

Try removing this piece of code from Device_PIC: (line 3171 of your dsdt)

					 IRQNoFlags ()
						 {2}

and report back the result.

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keeza
keeza
Posted
Posted
im sure its working because if i taken out the PSS code and remove NULLCPUPM kext temp is on the 50+.. also its hot from where im from and im also using a stock cooler :P

Are you using a powermanagement disabler kext?? Most have ditched them already if they are using vanilla powermanagement. Go back a few posts of mine, download the html file, read it and make the changes and you should be able to ditch nullcpupm kext (just make sure you have a backup or a separate usb stick with chameleon on it with a copy of your working extra folder just in case :P )

still my concern is am i safe using this code (right now im using it)? do i need to change/remove anything or just use Speedstep via kext :rolleyes:

Follow the instructions at the beginning of this thread for steps required to obtain your pss data and how to incorporate it into your dsdt.

 

Your two options:

Vanilla powermanagement = dsdt edits and no powermanagement kext (my setup)

Kext powermanagement = AICPUPM disabler kext and powermanagement kext (voodoo power or similar) kext.

 

Both seem to work well as far as I know, comes down to your choice. But your dsdt approach will differ slightly depending on which option.

 

 

 

Scope (_PR)
   {
       Name (PSS, Package (0x03)
       {
           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x0825, 
               Zero
           }, 

           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x071E, 
               One
           }, 

           Package (0x06)
           {
               Zero, 
               Zero, 
               0x0A, 
               0x0A, 
               0x0616, 
               0x02
           }
       })
       Name (PSD, Package (0x05)
       {
           0x05, 
           Zero, 
           Zero, 
           0xFC, 
           0x04
       })
       Name (CST, Package (0x04)
       {
           0x03, 
           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x01,               // Bit Width
                       0x02,               // Bit Offset
                       0x0000000000000000, // Address
                       ,)
               }, 

               One, 
               One, 
               0x03E8
           }, 

           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000414, // Address
                       ,)
               }, 

               0x02, 
               One, 
               0x01F4
           }, 

           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000415, // Address
                       ,)
               }, 

               0x03, 
               0x55, 
               0xFA
           }
       })
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }
   }

 

lastly my BIOS has a C2 to C4 option (C2, C3, C4 and disable).. what will i choose in there?

 

post-563478-1275200336_thumb.jpg

 

Thanks all in advance for the reply and help.

 

You have C1-C3 declared in the above code. I'd leave them both in (C1 works by default). The most important thing is that the CState sequential number (i.e. 1,2,3 etc is correct) which appears to be the case for you. If I have C4 declared as 3, 96, 64 and not 4, 96, 64 then it doesn't load.

 

BTW, I've uploaded my current dsdt to my sig. You can add the code for C4 and set bios to C4 or alternatively set BIOS to C3 and leave dsdt as is.

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dh.taran
dh.taran
Posted
Posted

Hi keeza, tried that, but it doesnt help.

 

The backup SL boot dsdt also has the same line IRQ 2, but audio is fine there, I am fairly certain its the spdstep configuration and c states as mentioned in this post on this same thread:

 

Keeza's audio stutter post

 

I'll try to get CStates going. I'll let you know about the stuttering issue.

 

You've actually had the same issue in the past I think :) ..LOL, the funny thing is, just like Eliade described "when I move the mouse really fast while playing some audio file, the audio doesnt stutter anymore"

 

You know what, I think Im going to reinsert the spdstep code following the exact same code from the first post in this thread only adding in my pstates and then give it a go. I think spstp is configured incorrectly in my dsdt, Im attaching my pstates screenshot for you to doublecheck that.

 

Here's what SuperHai said about the stutter issue:

 

There are a few things about C-states that makes issues. Crackled sound is an indication that you are in fact putting the CPU in a lower powered C-state (usually from C2 and lower), as the TSC stops counting. You need HPET or some other timing to be precise, and be sure that TSC is updated when returning to C0.

 

You also need to make the difference between SystemIO and FFixedHW (and other values).

 

post-241229-1275290597_thumb.png

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keeza
keeza
Posted
Posted
Hi keeza, tried that, but it doesnt help.

 

The backup SL boot dsdt also has the same line IRQ 2, but audio is fine there, I am fairly certain its the spdstep configuration and c states as mentioned in this post on this same thread:

Ok just wanted to eliminate the obvious first.

 

You've actually had the same issue in the past I think :P ..LOL, the funny thing is, just like Eliade described "when I move the mouse really fast while playing some audio file, the audio doesnt stutter anymore"

I've had two issues with stuttering audio and video in the past, one was related to my P-State values which I corrected. I also set my V-Core to 1.3v instead of auto. The second issue was the known Quicktime stutter bug. Disabling the AppleUpstreamUserClient.kext fixed that.

 

You know what, I think Im going to reinsert the spdstep code following the exact same code from the first post in this thread only adding in my pstates and then give it a go. I think spstp is configured incorrectly in my dsdt, Im attaching my pstates screenshot for you to doublecheck that.

Good idea, take out C-States for the moment and see if that fixes the problem. Least you'll know where to focus on.

 

Hope you get it sorted.

 

BTW you're overclocking right? Thats an area that I don't know too much about but if so maybe try stock settings first to see if the overclock contributes to the issue.

 

You know what, I think Im going to reinsert the spdstep code following the exact same code from the first post in this thread only adding in my pstates and then give it a go. I think spstp is configured incorrectly in my dsdt, Im attaching my pstates screenshot for you to doublecheck that.

post-241229-1275290597_thumb.png

 

VoodooMonitor should show your different voltages like PState Changer.

 

Have you removed the PState Changer kext?

Tried with DropSSDT=Yes in plist?

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dh.taran
dh.taran
Posted
Posted

@Keeza

 

 

K bro, I got the audio stuttering fixed :D by taking out the old spdstp code and doing it from the beginning by adding my p states. Temp is 52 degree idle. :D with A/C around 48 degrees. In Windows 7, its 34 degrees idle, which brings me to the main question which you all have asked others too...

 

"Why go to the trouble of speedstep when tmp's are still gonna be 50+ idle...Whyyy???"

 

By reading most of this thread, you all seem to have fixed that by putting in "C states" the right way and double checking other things.

 

Apparently Voodoomonitor shows the same voltages for both pstates, I dunno why...I took out pstatechanger's-->voodoopstate kext and added dropssdt-->yes, still no go, it still shows the same voltage like the screenshot in my earlier post, but when I check speedstep via terminal, I get:

 

bash-3.2# ioreg -lw0 |grep CSTInfo	| |   |	 "CSTInfo" = 19136773
bash-3.2# ioreg -lw0 |grep PerformanceStateArray	| |   |	 "PerformanceStateArray" = (<00000000000000000a0000000a0000002a07000000000000>,<00000000000000000a0000000a0000002a06000001000000>)

...which I think means that speedstep is kinda working?

 

The next thing I did was use voodoopowermini, well if it can bring down the temps to 35 degrees, what else do i need?...but that didnt work. I tried loading voodoomini with disable and nullcpu, both the times it failed, same temp, when I load it alone without disable/nullcpu I get the following error (attaching kernel log):

localhost kernel[0]: npvhash=4095
May 31 21:21:00 localhost kernel[0]: PAE enabled
May 31 21:21:00 localhost kernel[0]: 64 bit mode enabled
May 31 21:21:00 localhost kernel[0]: Darwin Kernel Version 10.3.0: Fri Feb 26 11:58:09 PST 2010; root:xnu-1504.3.12~1/RELEASE_I386
May 31 21:21:00 localhost kernel[0]: vm_page_bootstrap: 509342 free pages and 14946 wired pages
May 31 21:21:00 localhost kernel[0]: standard timeslicing quantum is 10000 us
May 31 21:21:00 localhost kernel[0]: mig_table_max_displ = 73
May 31 21:21:00 localhost kernel[0]: AppleACPICPU: ProcessorId=0 LocalApicId=0 Enabled
May 31 21:21:00 localhost kernel[0]: AppleACPICPU: ProcessorId=1 LocalApicId=1 Enabled
May 31 21:21:00 localhost kernel[0]: AppleACPICPU: ProcessorId=2 LocalApicId=2 Disabled
May 31 21:21:00 localhost kernel[0]: AppleACPICPU: ProcessorId=3 LocalApicId=3 Disabled
May 31 21:21:00 localhost kernel[0]: calling mpo_policy_init for Quarantine
May 31 21:21:00 localhost kernel[0]: Security policy loaded: Quarantine policy (Quarantine)
May 31 21:21:00 localhost kernel[0]: calling mpo_policy_init for Sandbox
May 31 21:21:00 localhost kernel[0]: Security policy loaded: Seatbelt sandbox policy (Sandbox)
May 31 21:21:00 localhost kernel[0]: calling mpo_policy_init for TMSafetyNet
May 31 21:21:00 localhost kernel[0]: Security policy loaded: Safety net for Time Machine (TMSafetyNet)
May 31 21:21:00 localhost kernel[0]: Copyright (c) 1982, 1986, 1989, 1991, 1993
May 31 21:21:00 localhost kernel[0]: The Regents of the University of California. All rights reserved.
May 31 21:21:00 localhost kernel[0]: MAC Framework successfully initialized
May 31 21:21:00 localhost kernel[0]: using 10485 buffer headers and 4096 cluster IO buffer headers
May 31 21:21:00 localhost kernel[0]: IOAPIC: Version 0x20 Vectors 64:87
May 31 21:21:00 localhost kernel[0]: ACPI: System State [S0 S3 S4 S5] (S3)
May 31 21:21:00 localhost kernel[0]: Can't get kextd port.
May 31 21:21:00 localhost kernel[0]: RTC: Only single RAM bank (128 bytes)
May 31 21:21:00 localhost kernel[0]: Apple16X50ACPI1: Identified Serial Port on ACPI Device=UAR1
May 31 21:21:00 localhost kernel[0]: Apple16X50UARTSync1: Detected 16550AF/C/CF FIFO=16 MaxBaud=115200
May 31 21:21:00 localhost kernel[0]: netkas presents fakesmc, a kext which emulates smc device
May 31 21:21:00 localhost kernel[0]: Previous Shutdown Cause: 0
May 31 21:21:00 localhost kernel[0]: DSMOS has arrived
May 31 21:21:00 localhost kernel[0]: NVDANV50HAL loaded and registered.
May 31 21:21:00 localhost kernel[0]: VoodooPowerMini 1.2 (C) 2009-10 Superhai, All Rights Reserved. May  1 2010 13:51:28 32 bit
May 31 21:21:00 localhost kernel[0]: mbinit: done (64 MB memory set for mbuf pool)
May 31 21:21:00 localhost kernel[0]: HDAEnabler: Copyright (c) 2008 by Kabyl
May 31 21:21:00 localhost kernel[0]: HDAEnabler: 05/05/2008 Added SPAudio support:Taruga
May 31 21:21:00 localhost kernel[0]: From path: "uuid", 
May 31 21:21:00 localhost kernel[0]: Waiting for boot volume with UUID A19FFE1A-54C7-3303-A8BB-470B2B3E0575
May 31 21:21:00 localhost kernel[0]: Waiting on <dict ID="0"><key>IOProviderClass</key><string ID="1">IOResources</string><key>IOResourceMatch</key><string ID="2">boot-uuid-media</string></dict>
May 31 21:21:00 localhost kernel[0]: com.apple.AppleFSCompressionTypeZlib load succeeded
May 31 21:21:00 localhost kernel[0]: AppleIntelCPUPowerManagementClient: ready
May 31 21:21:00 localhost kernel[0]: identified as RTL8168B/8111B
May 31 21:21:00 localhost kernel[0]: Got boot device = IOService:/AppleACPIPlatformExpert/PCI0@0/AppleACPIPCI/IDE1@1F,2/AppleAHCI/PRIM@0/IOAHCIDevice@0/AppleAHCIDiskDriver/IOAHCIBlockStorageDevice/IOBlockStorageDriver/WDC WD2500KS-00MJB0 Media/IOGUIDPartitionScheme/MAC OSX@2
May 31 21:21:00 localhost kernel[0]: BSD root: disk0s2, major 14, minor 2
May 31 21:21:01 localhost kernel[0]: com_chucko_RealtekR1000: Ethernet address 00:1a:4d:4f:41:e1
May 31 21:21:01 localhost kernel[0]: systemShutdown false
May 31 21:21:02 localhost kernel[0]: AppleIntelCPUPowerManagement: initialization complete
May 31 21:21:09 localhost kernel[0]: FakeSMC: key info not found MSDS, length - 6
May 31 21:21:09 Mac-Pro kernel[0]: FakeSMC: key not found BEMB, length - 1
May 31 21:21:09 Mac-Pro kernel[0]: NTFS driver 3.2 [Flags: R/W].
May 31 21:21:09 Mac-Pro kernel[0]: NTFS volume name Windows 7, version 3.1.
May 31 21:21:09 Mac-Pro kernel[0]: NTFS volume name Program Files, version 3.1.
May 31 21:21:10 Mac-Pro kernel[0]: NTFS volume name Data, version 3.1.
May 31 21:21:12 Mac-Pro kernel[0]: Sound assertion "0 == fMikeyDriver" failed in "/SourceCache/AppleHDA/AppleHDA-162.1.37/AppleHDA/AppleHDADriver.cpp" at line 1063 goto handler
May 31 21:21:15 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:21:16 Mac-Pro kernel[0]: Sound assertion "0 != result" failed in "/SourceCache/AppleHDA/AppleHDA-162.1.37/AppleHDA/AppleHDAWidget.cpp" at line 2508 goto handler
May 31 21:21:16 Mac-Pro kernel[0]: Sound assertion "0 != widget->setUnsolicited ( true )" failed in "/SourceCache/AppleHDA/AppleHDA-162.1.37/AppleHDA/AppleHDACodecGeneric.cpp" at line 850 goto handler
May 31 21:21:22 Mac-Pro kernel[0]: ound IG1C, length - 6
May 31 21:21:22 Mac-Pro kernel[0]: FakeSMC: key info not found IN2R, length - 6
May 31 21:21:22 Mac-Pro kernel[0]: FakeSMC: key info not found VSFC, length - 6// -----a lot of these apparently I havent gotten around to turning debug to false in the kext's info

May 31 21:21:27 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:21:57: --- last message repeated 5 times ---
May 31 21:22:01 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:22:31: --- last message repeated 5 times ---
May 31 21:22:34 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:23:04: --- last message repeated 5 times ---
May 31 21:23:07 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:23:37: --- last message repeated 5 times ---
May 31 21:23:40 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:24:10: --- last message repeated 5 times ---
May 31 21:24:12 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:24:42: --- last message repeated 4 times ---
May 31 21:24:42 Mac-Pro kernel[0]: VoodooPowerMini: Failed to get full power management control of CPU
May 31 21:25:12: --- last message repeated 4 times ---

 

I have the following kexts in my Extra/Extensions:

 

EvOreboot

fakesmc 2.5

AHCIPortInjector

VoodooMonitor

Voodoopowermini

 

I would appreciate any help in getting C states working so that I have bearable temps in this heat, that would be the whole point of getting speedstep in the first place, also any thoughts on Voodoopowermini not being loaded?

 

Thanks man. No one can do this stuff alone...well except assembly language professionals.

 

Im attaching my current dsdt with new speedstep code which fixed the stutter:

 

newssDSDT.dsl.zip

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FKA
FKA
Posted
  • Author
Posted

If you've added cst and PSS data to your DSDT why would you want to also load voodoopowermini ??

 

If you do want to load it try in S/L/E not E/E.

I would also say the same for voodoomonitor - put it in S/L/E

 

EDIT : You have the same VID (voltage ID) for both the pstates you have defined.

 

Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                   0x07[b][color="#ff0000"]2A[/color][/b], 
                    Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x0A, 
                   0x0A, 
                  0x06[b][color="#ff0000"]2A[/color][/b], 
                       One
               }
               })
           }

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keeza
keeza
Posted
Posted
Im attaching my current dsdt with new speedstep code which fixed the stutter:

 

Thats one down, good to hear the stuttering is fixed.

 

As FKA said try this code for the second P-State:

				Package (0x06)
			{
				Zero, 
				Zero, 
				0x0A, 
				0x0A, 
					0x061D, 
					One
			}
			})
		}

 

Voodoo monitor works fine for me in E/E.

Remove VoodooPower, change the voltage ID as above and see how that goes.

 

As FKA said its either VoodooPower and remove P-State and C-State from DSDT or

C-State and P-State in DSDT and no VoodooPower.

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dh.taran
dh.taran
Posted
Posted
If you've added cst and PSS data to your DSDT why would you want to also load voodoopowermini ??

 

To lower the temps, the whole point of me going after speedstep is to bring the temps under control, but I didnt know about the Pstates and Cstate thing being the same as v-mini, thanks for pointing that out.

 

As FKA said its either VoodooPower and remove P-State and C-State from DSDT or

C-State and P-State in DSDT and no VoodooPower.

 

Glad you cleared that keeza. However, the temps are still the same after giving the second p state different voltage. Even after taking out the P states and C states , voodoomini loads up but no temp difference, actually its +3-5 degrees with voodoomini.

 

The pstates calculator and vmonitor kexts have me confused, its quite obvious second p state is being loaded up with 1.187 voltage, but voodoomonitor shows the same for both.

 

Anything else we can try to get the temps down? :wacko:

 

post-241229-1275579889_thumb.png

post-241229-1275579900_thumb.png

 

PS: I tried the Macpro 3.1, 4.1, 5.1 switch in smbios, boots and runs fine in all of them with no temp difference, just thought Id mention this aswell.

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FKA
FKA
Posted
  • Author
Posted
post-241229-1275579900_thumb.png

 

You are still showing VID of 2A for both states.

Have you cleared caches once voodoomini was removed?

 

EDIT - also (sorry if you've already covered this) .. but do you have LPC device in IOReg??

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aliasa_anderson
aliasa_anderson
Posted
Posted

Hi All,

In an attempt to integrate the SSDT tables from Linux i came came across the following piece of code from my first SSDT table :

 

DefinitionBlock ("cpu1.aml", "SSDT", 1, "HP ", "30BC ", 0x00001000)

{

External (GP39)

External (GTF2, IntObj)

External (GTF0, IntObj)

External (\_SB_.PCI0.SATA, DeviceObj)

 

Scope (\_SB.PCI0.SATA)

{

Device (PRT0)

{

Name (_ADR, 0xFFFF)

Method (_SDD, 1, NotSerialized)

{

Name (GBU0, Buffer (0x07)

{

0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x00

})

CreateByteField (GBU0, 0x00, GB00)

CreateByteField (GBU0, 0x01, GB01)

CreateByteField (GBU0, 0x02, GB02)

CreateByteField (GBU0, 0x03, GB03)

CreateByteField (GBU0, 0x04, GB04)

CreateByteField (GBU0, 0x05, GB05)

CreateByteField (GBU0, 0x06, GB06)

If (LEqual (SizeOf (Arg0), 0x0200))

{

CreateWordField (Arg0, 0x9C, W780)

If (And (W780, 0x08))

{

Store (0x10, GB00)

Store (0x03, GB01)

Store (0xEF, GB06)

}

Else

{

Store (0x90, GB00)

Store (0x03, GB01)

Store (0xEF, GB06)

}

}

 

Store (GBU0, GTF0)

}

 

Method (_GTF, 0, NotSerialized)

{

Return (GTF0)

}

}

 

Device (PRT2)

{

Name (_ADR, 0x0002FFFF)

Method (_SDD, 1, NotSerialized)

{

Name (GBU2, Buffer (0x07)

{

0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x00

})

CreateByteField (GBU2, 0x00, GB20)

CreateByteField (GBU2, 0x01, GB21)

CreateByteField (GBU2, 0x02, GB22)

CreateByteField (GBU2, 0x03, GB23)

CreateByteField (GBU2, 0x04, GB24)

CreateByteField (GBU2, 0x05, GB25)

CreateByteField (GBU2, 0x06, GB26)

If (LEqual (SizeOf (Arg0), 0x0200))

{

CreateWordField (Arg0, 0x9C, W782)

If (And (W782, 0x08))

{

Store (0x10, GB20)

Store (0x03, GB21)

Store (0xEF, GB26)

}

Else

{

Store (0x90, GB20)

Store (0x03, GB21)

Store (0xEF, GB26)

}

}

 

Store (GBU2, GTF2)

}

 

Method (_GTF, 0, NotSerialized)

{

Return (GTF2)

}

 

Method (_PS0, 0, Serialized)

{

Store (0x00, GP39)

}

 

Method (_PS3, 0, Serialized)

{

Store (0x01, GP39)

}

 

Method (_PSC, 0, Serialized)

{

If (LNot (GP39))

{

Return (0x00)

}

 

Return (0x03)

}

}

}

}

 

 

I have successfully integrated the rest of the 7 SSDT tables but dont know what the above code is and where to put it.

Could anyone please suggest if it could even be added to the DSDT table ...i mean is it worth it.

 

 

 

Thanks in advance.

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