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DSDT fixes for Gigabyte boards


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#761
kdawg

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Tried this style to use a separate CST table for cpu0 and different for other cores. Didn't take long to remember why I got rid of it earlier. When idling everything seems fine and temps are real low. Then I start doing something that causes a light, let's say for example 10 % cpu load, and temps jump up at least 10 degrees. This always happens when I start using for example MPlayer or XBMC. If I use one common CST table for all cores idling temps are a bit higher but temps on a light load are lower so I prefer the 1 CST table solution.


Yeah I think I'm going to stick with this. Its seems to run the coolest idle and under load. Thanks guys.
Scope (_PR)    {        Name (PSS, Package (0x03)        {            Package (0x06) { Zero, Zero, 10, 10, 0x00000822, Zero },            Package (0x06) { Zero, Zero, 10, 10, 0x0000071E, One },            Package (0x06) { Zero, Zero, 10, 10, 0x0000061A, 2 }        })        Name (PSD, Package (0x05)        {            0x05,Zero,Zero,0xFC,0x04        })        Name (CST, Package (0x04)        {            0x03,            Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x00,)},One,One,0x03E8},             Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000414,    ,)},0x02,One,0x01F4},             Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000415,    ,)},0x03,0x55,0xFA}        })        Processor (CPU0, 0x00, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }        Processor (CPU1, 0x01, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }        Processor (CPU2, 0x02, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }        Processor (CPU3, 0x03, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }    }

EDIT
Couple other questions. Why didn't you change the device ID of LPCB to get AppleLPC.kext to load?
Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", Buffer (0x04){0x18, 0x3A, 0x00, 0x00}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}

And do you think EXPL is necassary? If so why don't they put it with the rest of the devices in Device (PCI0)?

#762
jamonda

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This is what I am using at the moment:


Was already under 900 lines without these EHCI mods ^_^



Amazing DSDT.dsl, for sure. It would be perfect if you could comment each block, name, method an so on, so that people like me could learn faster what they do and why they are necessary and, of course, try to help the community.

#763
mm67

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Yeah I think I'm going to stick with this. Its seems to run the coolest idle and under load. Thanks guys.

Scope (_PR)    {        Name (PSS, Package (0x03)        {            Package (0x06) { Zero, Zero, 10, 10, 0x00000822, Zero },            Package (0x06) { Zero, Zero, 10, 10, 0x0000071E, One },            Package (0x06) { Zero, Zero, 10, 10, 0x0000061A, 2 }        })        Name (PSD, Package (0x05)        {            0x05,Zero,Zero,0xFC,0x04        })        Name (CST, Package (0x04)        {            0x03,            Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x00,)},One,One,0x03E8},             Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000414,    ,)},0x02,One,0x01F4},             Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000415,    ,)},0x03,0x55,0xFA}        })        Processor (CPU0, 0x00, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }        Processor (CPU1, 0x01, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }        Processor (CPU2, 0x02, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }        Processor (CPU3, 0x03, 0x00000410, 0x06)        {            Alias (PSS, _PSS)            Alias (PSD, _PSD)            Alias (CST, _CST)        }    }


Yes, exactly the same setup that I am using now. This runs cool also on load.

#764
kdawg

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Yes, exactly the same setup that I am using now. This runs cool also on load.


Couple other questions. Why didn't you change the device ID of LPCB to get AppleLPC.kext to load?

Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", Buffer (0x04){0x18, 0x3A, 0x00, 0x00}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}

And do you think EXPL is necassary? If so why don't they put it with the rest of the devices in Device (PCI0)?

Sorry you were too quick to answer I had amended my last post.

#765
mm67

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Couple other questions. Why didn't you change the device ID of LPCB to get AppleLPC.kext to load?

Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", Buffer (0x04){0x18, 0x3A, 0x00, 0x00}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}


I don't need to do that since my board has ICH10, not ICH10R as yours. ICH10 has corrrect device-id as default.

And do you think EXPL is necassary? If so why don't they put it with the rest of the devices in Device (PCI0)?


I left it there so I would remember to figure out what it is and if it is necessary ^_^

#766
kdawg

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I don't need to do that since my board has ICH10, not ICH10R as yours. ICH10 has corrrect device-id as default.

Ah ha!

I left it there so I would remember to figure out what it is and if it is necessary ;)

Would you agree it'd be safe to move? I don't understand the logic of keeping it isolated from the rest of the devices.

Also, I think I had mapped SYSR to MacPro3,1's LDRC device.

#767
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Tried this style to use a separate CST table for cpu0 and different for other cores. Didn't take long to remember why I got rid of it earlier. When idling everything seems fine and temps are real low. Then I start doing something that causes a light, let's say for example 10 % cpu load, and temps jump up at least 10 degrees. This always happens when I start using for example MPlayer or XBMC. If I use one common CST table for all cores idling temps are a bit higher but temps on a light load are lower so I prefer the 1 CST table solution.

Interesting. Now read this: "The platform must expose a _CST object for either all or none of its processors.".

And this: "_CST eliminates the ACPI 1.0 restriction that all processors must have C State parity. With _CST, each processor can have its own characteristics independent of other processors. For example, processor 0 can support C1, C2 and C3, while processor 1 supports only C1.".

And the Intel CPU specification, saying that the first core may not enter any C state higher than 1.

#768
mm67

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Interesting. Now read this: "The platform must expose a _CST object for either all or none of its processors.".

And this: "_CST eliminates the ACPI 1.0 restriction that all processors must have C State parity. With _CST, each processor can have its own characteristics independent of other processors. For example, processor 0 can support C1, C2 and C3, while processor 1 supports only C1.".

And the Intel CPU specification, saying that the first core may not enter any C state higher than 1.


I'm not sure if this refers to only real multi cpu systems or is this information valid also with multicore cpu's. Is this even possible since I seem to recall that only Nehalem's have all cores working independently. On my quad core it looks more like 2 + 2 cores are changing states together.




Ah ha!

Would you agree it'd be safe to move? I don't understand the logic of keeping it isolated from the rest of the devices.

Also, I think I had mapped SYSR to MacPro3,1's LDRC device.


Ok, EXPL seems to be pointing to something like this:
http://tldp.org/HOWT...ay-HOWTO-3.html

So in my opinion it should be safe to remove, I will do that now ;)

#769
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I'm not sure if this refers to only real multi cpu systems or is this information valid also with multicore cpu's. Is this even possible since I seem to recall that only Nehalem's have all cores working independently. On my quad core it looks more like 2 + 2 cores are changing states together...

I agree that the ACPI specification is a bit blurry sometimes, to put it mildly. And the only reference to a multiprocessing environment in the specification is this one:

"In a multiprocessing environment, all CPUs must support the same number of performance states and each processor performance state must have identical performance and power-consumption parameters. Performance objects must be present under each processor object in the system for OSPM to utilize this feature.
Processor performance control objects include the ‘_PCT’ package, ‘_PSS’ package, and the ‘_PPC’ method as detailed below.
".

Note the bold part, which is why I stick with the aliases ;)

#770
mm67

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I agree that the ACPI specification is a bit blurry sometimes, to put it mildly. And the only reference to a multiprocessing environment in the specification is this one:

"In a multiprocessing environment, all CPUs must support the same number of performance states and each processor performance state must have identical performance and power-consumption parameters. Performance objects must be present under each processor object in the system for OSPM to utilize this feature.
Processor performance control objects include the ‘_PCT’ package, ‘_PSS’ package, and the ‘_PPC’ method as detailed below.
".

Note the bold part, which is why I stick with the aliases :)


Yes, there sure is no harm in defining all cores. I just wonder why OS X even accepts a setup that is not fully defined for all cores, if I try to use such a dsdt on Linux it gets refused.

#771
kdawg

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Ok, EXPL seems to be pointing to something like this:
http://tldp.org/HOWT...ay-HOWTO-3.html

So in my opinion it should be safe to remove, I will do that now :angel:


IGBE seems to be useless as well. Doesn't even show up in ioreg.

Other than that, the only other one that seems to be useless is PMIO. Which I believe is "Portwell Modules I/O" for handling PCIe or PCI expansion capabilities.

#772
mm67

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IGBE seems to be useless as well. Doesn't even show up in ioreg.

Other than that, the only other one that seems to be useless is PMIO. Which I believe is "Portwell Modules I/O" for handling PCIe or PCI expansion capabilities.


That name IGBE somehow sounds like Gigabit Ethernet and on Windows side it is shown as a network device. Have to look into that PMIO, address range seems to refer to PMBASE ports. Test what happens if you take those out.

#773
archie68

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Help for a an uber-n00b! I have:

Core2Quad
Nvidia 9800 video card
4 GB RAM
ep45-ud3l

I have everything working except sound and some speed step issues (CPU temps are high 50's C at idle). The bootloader seems to be working fine now, although it gave me issues in the beginning (forced a reboot unless the original OSX thumbdrive was plugged in)

I've downloaded the .dsl and .aml files from the first post of this thread and downloaded DSDTPatcherGUI_1.0 but I have NO CLUE on how to apply these patches, and most guides seem to assume a certain amount of previous experience with DSDT patcher. Is there a very basic beginner's guide for this task? I'm worried my Core2Quad is going to overheat on me!

#774
kdawg

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That name IGBE somehow sounds like Gigabit Ethernet and on Windows side it is shown as a network device. Have to look into that PMIO, address range seems to refer to PMBASE ports. Test what happens if you take those out.

I've taken both out and see no impact.

#775
xjasx

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here's mine for ga-ep45-ud3p with all fixes...
shutdown works... sleep works without setting in energy prefs

more can probably be cut...

Attached Files



#776
mm67

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here's mine for ga-ep45-ud3p with all fixes...
shutdown works... sleep works without setting in energy prefs

more can probably be cut...


This CST table doesn't look right:

Method (_CST, 0, NotSerialized)            {                Return (Package (0x04)                {                    0x03,                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (FFixedHW,                                 0x01,               // Bit Width                                0x02,               // Bit Offset                                0x0000000000000000, // Address                                0x01,               // Access Size                                )                        },                         One,                         One,                         0x03E8                    },                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (SystemIO,                                 0x08,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000814, // Address                                ,)                        },                         0x02,                         One,                         0x01F4                    },                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (SystemIO,                                 0x08,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000815, // Address                                ,)                        },                         0x03,                         0x11,                         0xFA                    }                })            }        }

Your PMBASE address is 0x400 so why are you using 0x814 and 0x815 for C2 and C3. But then again again your CPU is Q6600 which doesn't have C2 and C3 states anyway so how about doing some cutting.

#777
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yeah I know i only have C1, probably why I never paid attention to the other part, so after cutting it, looks like:

Method (_CST, 0, NotSerialized)
			{
				Return (Package (0x04)
				{
					0x03, 
					Package (0x04)
					{
						ResourceTemplate ()
						{
							Register (FFixedHW, 
								0x01,			   // Bit Width
								0x02,			   // Bit Offset
								0x0000000000000000, // Address
								0x01,			   // Access Size
								)
						}, 

						One, 
						One, 
						0x03E8
					}
				})
			}
yes?

edit: output gives
./dsdt_fixed.txt 75: Return (Package (0x04)
Remark 5048 - ^ Initializer list shorter than declared package length

what should that package value be

#778
mm67

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yeah I know i only have C1, probably why I never paid attention to the other part, so after cutting it, looks like:

Method (_CST, 0, NotSerialized)
			{
				Return (Package (0x04)
				{
					0x03, 
					Package (0x04)
					{
						ResourceTemplate ()
						{
							Register (FFixedHW, 
								0x01,			   // Bit Width
								0x02,			   // Bit Offset
								0x0000000000000000, // Address
								0x01,			   // Access Size
								)
						}, 

						One, 
						One, 
						0x03E8
					}
				})
			}
yes?


Almost, this will work
Method (_CST, 0, NotSerialized)
			{
				Return (Package (0x02)
				{
					0x01, 
					Package (0x04)
					{
						ResourceTemplate ()
						{
							Register (FFixedHW, 
								0x01,			   // Bit Width
								0x02,			   // Bit Offset
								0x0000000000000000, // Address
								0x01,			   // Access Size
								)
						}, 

						One, 
						One, 
						0x03E8
					}
				})
			}

And of course you only need one these under CPU0. CPU1, CPU2 AND CPU3 can refer to it using Alias

#779
MacUser2525

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Almost, this will work

Method (_CST, 0, NotSerialized)
			   {
				   Return (Package (0x02)
				   {
					   0x01, 
					   Package (0x04)
					   {
						   ResourceTemplate ()
						   {
							   Register (FFixedHW, 
								   0x01,			   // Bit Width
								   0x02,			   // Bit Offset
								   0x0000000000000000, // Address
								   0x01,			   // Access Size
								   )
						   }, 
   
						   One, 
						   One, 
						   0x03E8
					   }
				   })
			   }

And of course you only need one these under CPU0. CPU1, CPU2 AND CPU3 can refer to it using Alias


So which is correct for the Access Size here you have 0x01 and in the earlier post when changing to the Name CST... kdawg has 0x00 in it.

Name (CST, Package (0x04)
		 {
			 0x03,
			 Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x00,)},One,One,0x03E8},
			 Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000414, ,)},0x02,One,0x01F4},
			 Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000415, ,)},0x03,0x55,0xFA}
		 })


#780
mm67

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So which is correct for the Access Size here you have 0x01 and in the earlier post when changing to the Name CST... kdawg has 0x00 in it.

Name (CST, Package (0x04)
		 {
			 0x03,
			 Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x00,)},One,One,0x03E8},
			 Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000414, ,)},0x02,One,0x01F4},
			 Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000415, ,)},0x03,0x55,0xFA}
		 })


Bit 0: Set to 1 if HW-coordinated
Bit 1: Set to 1 if OSPM should use Bus Master avoidance for this C-state

That it what Intel Processor Vendor-Specific ACPI says about that value. I think 0 or blank would be correct, blank is what my original SSDT uses. 0 equals blank here.





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