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DSDT fixes for Gigabyte boards


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#741
Master Chief

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Nope, ICH10 datasheet has this note under description:
Normally, this register is read-only to report capabilities to the power management software. To report different power management capabilities, depending on the system in which the ICH10 is used, bits 15:11 and 8:6 in this register are writable when the WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set. The value written to this register does not affect the hardware other than changing the value returned during a read.

That's is exactly the same note I have for register 0x52, for my ICH9. And something is initializing this register. Or should I say should as it doesn't appear to work on GB boards :P

So this register really isn't needed for anything, it's just that because Gigabyte writes a stupid value there OS X is fooled into thinking that EHCI device has no PME capabilities.

You think? So tell me; Why did Apple include this snippet:
OperationRegion (U7CS, PCI_Config, 0x54, 0x02)
				Field (U7CS, WordAcc, NoLock, Preserve)
				{
						,   15, 
					PMES,   1
				}
Why did they, when they don't need it? Again: Is bit 8 set, and if not, what happens when you set it? I mean the note: "This bit (8 and 15) must be explicitly cleared by the operating system each time it is initially loaded." can't be there too for nothing! What if bit 8 and/or 15 are not cleared at boot time?

#742
mm67

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That's is exactly the same note I have for register 0x52, for my ICH9. And something is initializing this register. Or should I say should as it doesn't appear to work on GB boards :P


You think? So tell me; Why did Apple include this snippet:

OperationRegion (U7CS, PCI_Config, 0x54, 0x02)
				Field (U7CS, WordAcc, NoLock, Preserve)
				{
						,   15, 
					PMES,   1
				}
Why did they, when they don't need it? Again: Is bit 8 set, and if not, what happens when you set it? I mean the note: "This bit (8 and 15) must be explicitly cleared by the operating system each time it is initially loaded." can't be there too for nothing! What if bit 8 and/or 15 are not cleared at boot time?


Bit 8 of register 54 is set if I boot without my patch and I don't know why Apple added that register to their DSDT. What I do know is that my MSI board has no such stuff in DSDT and value of register 52 is always C9C2 so I assume that bios is putting that value there.

/edit
With my patch bit 8 of register 54 is not set. Without patch value is 0x0100 and with patch 0x0000

#743
keeza

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Bit 8 of register 54 is set if I boot without my patch and I don't know why Apple added that register to their DSDT. What I do know is that my MSI board has no such stuff in DSDT and value of register 52 is always C9C2 so I assume that bios is putting that value there.

/edit
With my patch bit 8 of register 54 is not set. Without patch value is 0x0100 and with patch 0x0000


I'll try this patch when I get back from a short break to see if it'll work with my white apple keyboard connected to my hub on my cinema display.

Nice work mm67!!!

p.s. care to share your latest and greatest?

#744
mm67

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I'll try this patch when I get back from a short break to see if it'll work with my white apple keyboard connected to my hub on my cinema display.

Nice work mm67!!!

p.s. care to share your latest and greatest?


This is what I am using at the moment:
Attached File  dsdt.dsl.zip   4.21KB   629 downloads

Was already under 900 lines without these EHCI mods :)

#745
blackosx

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Great work with your fix mm67 and I enjoyed your open discussion with MasterChief about it as it gives an insight in to the whole development process. Thanks

This is what I am using at the moment:

Was already under 900 lines without these EHCI mods :(

And your DSDT is amazing, as for me, it throws a whole new angle on this subject. It's as if you have started with a blank DSDT and only added what you've needed?

Thanks for sharing.

#746
FKA

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This is what I am using at the moment:
Attached File  dsdt.dsl.zip   4.21KB   629 downloads

Was already under 900 lines without these EHCI mods :(


I'd love to know why I can't get speedstep working with these mods.

Here's mm67's dsdt patched up for my p35 board - speedstep NOT working!

D.

Attached File  DSDT08_12_09.dsl.zip   5.62KB   64 downloads

#747
blackosx

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I'd love to know why I can't get speedstep working with these mods.

Here's mm67's dsdt patched up for my p35 board - speedstep NOT working!

It worked for me, so I have done what I did for mine, with your data. Have a look at the attached and see if that works for you? (You might need other bits for your setup, but this is using just what I know)..

Attached Files



#748
mm67

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It worked for me, so I have done what I did for mine, with your data. Have a look at the attached and see if that works for you? (You might need other bits for your setup, but this is using just what I know)..


Do you now have method PTS setup like mine, if you do then could you try some shutdowns without OHR.kext.

#749
blackosx

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Do you now have method PTS setup like mine, if you do then could you try some shutdowns without OHR.kext.

I am testing with your DSDT with only my data in Scope (_PR). Here it is...
Attached File  dsdt.dsl.zip   4.31KB   87 downloads

As for Shutdowns, I can report 5 out of 5 so far :(

#750
mm67

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I am testing with your DSDT with only my data in Scope (_PR). Here it is...
Attached File  dsdt.dsl.zip   4.31KB   87 downloads

As for Shutdowns, I can report 5 out of 5 so far :(


That's good, I have now been using shutdown without OHR for almost two weeks, haven't seen it fail even once.

#751
kdawg

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That's good, I have now been using shutdown without OHR for almost two weeks, haven't seen it fail even once.

I know this is a lot to ask but would you happen to have your original unedited DSDT for comparison?

#752
mm67

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I know this is a lot to ask but would you happen to have your original unedited DSDT for comparison?


Sure, here you go, totally vanilla
Attached File  DSDT_r1_GBT_GBTUACPI_1000_MSFT_100000C.dsl.zip   12.92KB   94 downloads

#753
Aargh-a-Knot

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@mm67

Yes, truly a work of art! Definitely gives me something to aspire for.

Only, I wish I could see your thoughts behind every change and removal...

#754
sk1nhead

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Do you now have method PTS setup like mine, if you do then could you try some shutdowns without OHR.kext.

That's good, I have now been using shutdown without OHR for almost two weeks, haven't seen it fail even once.

unfortunately OSXRestart doesn't work on my board 100%, sometimes it shutdown- sometimes it wont, so Ev0reboot for now.


woohoo! mm67 you're a genius, you nailed 2 problems (aluminum kb and shutdown) of mine in one stone! Goodbye ev0 and OHR and finally for the first time i am using OSXRestart by MC..

Shutdown is 4 out of 4 already. Thanks Thanks. Excellent job. :)

#755
kdawg

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Sure, here you go, totally vanilla
Attached File  DSDT_r1_GBT_GBTUACPI_1000_MSFT_100000C.dsl.zip   12.92KB   94 downloads


Just so you know I'm getting temperatures 3-5 degrees cooler with this Scope (_PR):
Scope (_PR)    {		Processor (CPU0, 0x00, 0x00000410, 0x06)		{			Method (_PSS, 0, NotSerialized)			{				Return (Package(0x03)				{					Package (0x06) { 0x00, 0x00, 10, 10, 0x00000822, 0 },					Package (0x06) { 0x00, 0x00, 10, 10, 0x0000071E, 1 },					Package (0x06) { 0x00, 0x00, 10, 10, 0x0000061A, 2 }				})			}            Method (_PSD, 0, NotSerialized)            {                Return (Package (0x05) {0x05, 0x00, 0x00, 0xFC, 0x04})            }			Method (_CST, 0, NotSerialized)			{				Return (Package (0x02)				{					0x01, 					Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, 0x01, )}, 0x01, 0x05A, 0x0384} 				})			}		}		Processor (CPU1, 0x01, 0x00000410, 0x06)		{			Alias (\_PR.CPU0._PSS, _PSS)                        Alias (\_PR.CPU0._PSD, _PSD)			Method (_CST, 0, NotSerialized)			{				Return (Package (0x04)				{					0x03, 					Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, ,)}, 0x01, 0x00, 0x0384}, 					Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x414, ,)}, 0x02, 0x01, 0x01F4}, 					Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x415, ,)}, 0x03, 0x55, 0xFA} 				})			}		}		Processor (CPU2, 0x02, 0x00000410, 0x06)		{			Alias (\_PR.CPU0._PSS, _PSS)                        Alias (\_PR.CPU0._PSD, _PSD)			Alias (\_PR.CPU1._CST, _CST)		}    		Processor (CPU3, 0x03, 0x00000410, 0x06)		{			Alias (\_PR.CPU0._PSS, _PSS)                        Alias (\_PR.CPU0._PSD, _PSD)			Alias (\_PR.CPU1._CST, _CST)		}	}

Using your interpretation my temps were higher.
Scope (_PR)    {        Processor (CPU0, 0x00, 0x00000410, 0x06)         {			Method (_PSS, 0, NotSerialized)			{				Return (Package (0x03)				{					Package (0x06) { 0x00, 0x00, 10, 10, 0x00000822, 0 },					Package (0x06) { 0x00, 0x00, 10, 10, 0x0000071E, 1 },					Package (0x06) { 0x00, 0x00, 10, 10, 0x0000061A, 2 }				})			}			Method (_CST, 0, NotSerialized)			{				Return (Package (0x4)				{					0x03, 					Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, ,)}, 0x01, 0x00, 0x0384}, 					Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x414, ,)}, 0x02, 0x01, 0x01F4}, 					Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x415, ,)}, 0x03, 0x55, 0xFA} 				})			}        }        Processor (CPU1, 0x01, 0x00000410, 0x06) {}        Processor (CPU2, 0x02, 0x00000410, 0x06) {}        Processor (CPU3, 0x03, 0x00000410, 0x06) {}    }


#756
mm67

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Just so you know I'm getting temperatures 3-5 degrees cooler with this Scope (_PR):


Yes, I have seen that my self. I'm just not sure if it is a good a idea to use latency value 0 in CST

#757
Master Chief

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Just so you know I'm getting temperatures 3-5 degrees cooler with this Scope (_PR) ...

Now move the methods: _PSS, _PSD and _CST out of CPU1 into the _PR scope and use this:
Processor (CPUn, 0x02, 0x00000410, 0x06)
{
	Alias (PSS, _PSS)
	Alias (PSD, _PSD)
	Alias (CST, _CST)
}
For CPU2, CPU3 and CPU4. See how many bytes you get off of dsdt.aml And not only that, because this way it is also faster ;)

woohoo! mm67 you're a genius, you nailed 2 problems (aluminum kb and shutdown) of mine in one stone! Goodbye ev0 and OHR and finally for the first time i am using OSXRestart by MC..

Shutdown is 4 out of 4 already. Thanks Thanks. Excellent job. :)

I second that!

I knew that he was working on getting shutdown fixed, and not only that but he also nailed the Alu Apple keyboard wake. Which is fantastic news for GB users and the like. Again, great job mm67!!!

#758
kdawg

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Now move the methods: _PSS, _PSD and _CST out of CPU1 into the _PR scope and use this:

Processor (CPUn, 0x02, 0x00000410, 0x06)
{
	Alias (PSS, _PSS)
	Alias (PSD, _PSD)
	Alias (CST, _CST)
}
For CPU2, CPU3 and CPU4. See how many bytes you get off of dsdt.aml And not only that, because this way it is also faster ;)

Worked like a charm. My temps are even a couple degrees lower now. I also took out the zero latency value in my CST.


I second that!

I knew that he was working on getting shutdown fixed, and not only that but he also nailed the Alu Apple keyboard wake. Which is fantastic news for GB users and the like. Again, great job mm67!!!

Yeah I agree. This community is lucky to have a few pioneers (Master Chief and mm67 to name just two) willing to take the time AND share their work.

Thanks!

#759
thiagomorales

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Amazing guys! Great work MC and mm67..
Regards

#760
mm67

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Worked like a charm. My temps are even a couple degrees lower now. I also took out the zero latency value in my CST.


Yeah I agree. This community is lucky to have a few pioneers (Master Chief and mm67 to name just two) willing to take the time AND share their work.

Thanks!


Tried this style to use a separate CST table for cpu0 and different for other cores. Didn't take long to remember why I got rid of it earlier. When idling everything seems fine and temps are real low. Then I start doing something that causes a light, let's say for example 10 % cpu load, and temps jump up at least 10 degrees. This always happens when I start using for example MPlayer or XBMC. If I use one common CST table for all cores idling temps are a bit higher but temps on a light load are lower so I prefer the 1 CST table solution.





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