571 replies to this topic

[juanerson]

Exactly same Kernel Panic as Mohamed Khairy here in 10.7.4 (11E46), booting with "UseKernelCache=No" to prevent instant reboot... So, at this point the Patch seems to be insufficient. Maybe a new parts to write operations (MSR registers) are blocked in AICPM.kext (versions 193.0 = 10.7.4 and 196.0 = DP3) or something else about it?

[juanerson]

Well. Now is working partially fine. At least the system boots without NullCPU.

I need to correct my opinion about the AICPMPatch, please sorry guys. Because the Patcher - Script by oldnapalm is working very well, as expected... my respect to him and of course to all the people involved in this project. The problem seems coming from the SSDT tables, so now I have NO tables from /Extra, it booting fine, using GenerateCStates=Yes and DropSSDT=Yes to avoid LPC errors. But I have NO readings of P-States, even using GeneratePStates=Yes is NOT working this flag right now. So, I have NO native SpeedStep (EIST) support, but fortunately C1E (Max / min multipliers) is running. I will do more tests with some custom/compatibles SSDT table(s) for P-States. Please sorry my English, and Good Luck.

[Mohamed Khairy]

i was using
GenerateCStates=Yes
GeneratePStates=Yes
only
and this cause panic to the new kext

now added
DropSSDT=Yes

and this pass with out panic

thanks
juanerson

special thanks to oldnapalm whom helped me on this forum many times

[Mohamed Khairy]

but

with out DropSSDT=Yes i got more pstates
MSRDumper PStatesReached: 8 10 11 13 14 17 18 19 22 23
and under ACPI_SMC_Platformplugin got performance state arrey

with DropSSDT=Yes

MSRDumper PStatesReached: 8 11 12 16 26 27 29

i got turbo post but less pstates
and under acpi_smc ..... there is no performance state arrey

[juanerson]

This definitely SOLVED my problem with native Speedstep. Now, all multipliers - PStates are working from the corrected SSDT table. Try it.

[Mohamed Khairy]

This definitely SOLVED my problem with native Speedstep. Now, all multipliers - PStates are working from the corrected SSDT table. Try it.

i tried revoboot with


#define MAX_NUMBER_OF_P_STATES 19


and comiped it but after restart it stop on /boot nearly boot file is not functioning

[juanerson]

Revoboot is NOT a requirement FOR THIS PROCEDURE, at all.

I have installed Chameleon 2.1svn 1925, all my SSDT tables in /Extra for C&PStates (named and loading like SSDT.aml, SSDT-1.aml, SSDT-2.aml... etc).
 Captura de pantalla 2012-04-24 a la(s) 17.57.59.png   102.79KB   179 downloads
But If you prefer, the C-States table can be generated automatically by the flag "GenerateCStates=Yes". So, one less table from /Extra, for you.

The fix must be applied into the SSDT table of P-States (is just one table for sandy bridge). And, of course "DropSSDT=Yes" to avoid the bad factory one(s).

THE SSDT TABLE UPLOADED BY VCH888 IS A VERY GOOD EXAMPLE (GIGABYTE MOTHERBOARD AND i5-2500K).

PLEASE, DO NOT USE THE ATTACHED TO LOAD ANYTHING. I WANT TO BE CLEAR... THAT'S MY OWN TABLE, EXTRACTED FROM MY OWN BIOS - FIRMWARE, FOR MY OWN CPU (LITERALLY). JUST COMPARE THE IMPORTANT "_PSS" OR "APSS" SECTIONS WITH YOURS, AND MAKE YOUR OWN CHANGES. APART TO THAT SECTION, YOUR TABLE(S) COULD BE VERY DIFFERENT IN SOME OTHER ASPECTS, FOR SURE.

Attached Files

•  TABLES ONLY FOR REFERENCE.zip   2.03KB   119 downloads

Edited by juanerson, 24 April 2012 - 11:30 PM.

[Mohamed Khairy]

Revoboot is NOT a requirement at all.

I have installed Chameleon 2.1svn 1925, all my SSDT tables in /Extra for C&PStates (named and loading like SSDT.aml, SSDT-1, SSDT-2.. etc).
 Captura de pantalla 2012-04-24 a la(s) 17.57.59.png   102.79KB   179 downloads
The fix must be applied into the SSDT table for P-States (is just one table for sandy bridge). And of course "DropSSDT=Yes" to avoid the bad factory ones.

can you share your original ssdt tables and edited ones
so i can do one for me

thanks

[Mohamed Khairy]

edit i used the ssdt.dsl of Z68XP-UD3R_i2500K that was on topic
and edited frequency to begin from 800 to 2900

and this worked fine to me

MSRDumper PStatesReached: 8 11 12 13 16 18 19 21 22 25 26 27 29

there is 22 state on ioregistry

didn't notice that you edited your post will try to use mine ssdt and edit it like yours one


thanks again


 SSDT.aml.zip   419bytes   41 downloads

[Mohamed Khairy]

question


Package (0x06)
{
0x000008FD,
0x000088B8,
0x0000006E,
0x0000000A,
0x00000083,
0x00000000
},

how to calculate this value for every frequency ?

[juanerson]

That specific value should coming in your factory table, which can be extracted in windows with AIDA64. But there is not the important part of the fix... look in the ioreg. Then, you don't need calculate it... please see the other example and compare, is more simple.

[Mohamed Khairy]

That specific value should coming in your factory table, extracted in windows with AIDA64. You don't need calculate it... see the other example, is more simple.

thanks my table only contain 8 states

any way i got values from macbookpro 8.1 io registry that came with Intel® Core™ i5-2415M CPU @ 2.30GHz
and there is 22 state and values is typical to my cpu

will put this the rest of values

-----------------------------------------------
just done
 pstate.png   64.99KB   116 downloads

 SSDT.aml.zip   735bytes   27 downloads

[kounelos]

If someone got native speedstep in mountain lion could you please post some info like:

MSRDumper results
Mac Model used in SMBios (pathced or stock stepper)
Bootloader Used
CPU model

[XLR]

@ Developers:

Is it theoretically possible to implement automatic AICPM injection into Chameleon?

[asstastic]

DropSSDT=Yes fixed kernel panics on boot with 10.7.3 for me.

Update: Only get 2 p-states. I noticed in my IOReg PerformanceStateArray that p-state values jump from 0x14 to 0x1d
 SpeedStep.tiff   143.9KB   45 downloads


I experimented with several versions of MacBookPro8_2.plist in ACPI_SMC_PlatformPlugin.kext

10.6.7 plist: 2 p-ststes
No plist: 2 p-states
10.7.0 plist: System lockup and CMOS corruption, could not test p-states

Attached Files

•  SpeedStep.tiff   143.9KB   45 downloads

[rama]

I'm trying to get this patch to work on a Dell vostro 3550 laptop. I have 10.7.3 installed (aicpupm ver. 167.3.0) The patch has gone successfully, but when I boot without Nullcpupm or with the -allowCPUPM flag, I get all the way to the osx GUI, but then the laptop goes to sleep, If I press the power button it almost boots, then goes back to sleep and I can't get it to come back, It just loops like this endlessly. Is this likely a DSDT issue with sleep functions? is there any know workaround?
thanks.

[kounelos]

I'm trying to get this patch to work on a Dell vostro 3550 laptop. I have 10.7.3 installed (aicpupm ver. 167.3.0) The patch has gone successfully, but when I boot without Nullcpupm or with the -allowCPUPM flag, I get all the way to the osx GUI, but then the laptop goes to sleep, If I press the power button it almost boots, then goes back to sleep and I can't get it to come back, It just loops like this endlessly. Is this likely a DSDT issue with sleep functions? is there any know workaround?
thanks.

i don't think your problem is related to speedstepper.since you don't get a KP then the patch works fine..
Could you give us some details?
Which bootloader - custom SSDT or pstates auto generation?
Have you tried to boot with -x ?

[beta992]

Could somebody please let me show to generate a SSDT for my i5-2400 CPU? I'm trying to read the instructions given here, but I don't understand the edits.
I have already patch ACPM, and I can boot without any problems on ML DP3.

Chameleon generates C&P-states:

5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 1
5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 0
5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 2
5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 3

Do I need any edit in my DSDT? Do I need to paste a plist file into ACPM? How can I create a SSD?

Hope someone can help me,

Thanks.

[kounelos]

Could somebody please let me show to generate a SSDT for my i5-2400 CPU? I'm trying to read the instructions given here, but I don't understand the edits.
I have already patch ACPM, and I can boot without any problems on ML DP3.

Chameleon generates C&P-states:

5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 1
5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 0
5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 2
5/3/12 5:24:22.000 PM kernel[0]: P-State Stepper Error 18 at step 2 in context 2 on CPU 3

Do I need any edit in my DSDT? Do I need to paste a plist file into ACPM? How can I create a SSD?

Hope someone can help me,

Thanks.

First of all don't let chameleon generate anything in ML and since you have pathced successfully your ACPM you don't need to do anything else to it.The reason we patch ACPM is because we don't have a gigabyte board and we wanna avoid KP on boot.
Since your system boots you are good. Now, in order to get proper speedstep you need CPU definitions in your DSDT for your cpu like:

	Scope (_PR)
	{
		Processor (P000, 0x01, 0x00000410, 0x06)
		{
		}
		Processor (P001, 0x02, 0x00000410, 0x06)
		{
		}
		Processor (P002, 0x03, 0x00000410, 0x06)
		{
		}
		Processor (P003, 0x04, 0x00000410, 0x06)
		{
		}
	}

and a proper SSDT for your cpu.Since we have the same cpu you could test mine.

 ssdt.aml.zip   752bytes   33 downloads

You can also read here http://www.insanelym...howtopic=278374

[beta992]

First of all don't let chameleon generate anything in ML and since you have pathced successfully your ACPM you don't need to do anything else to it.The reason we patch ACPM is because we don't have a gigabyte board and we wanna avoid KP on boot.
Since your system boots you are good. Now, in order to get proper speedstep you need CPU definitions in your DSDT for your cpu like:

	Scope (_PR)
	{
		Processor (P000, 0x01, 0x00000410, 0x06)
		{
		}
		Processor (P001, 0x02, 0x00000410, 0x06)
		{
		}
		Processor (P002, 0x03, 0x00000410, 0x06)
		{
		}
		Processor (P003, 0x04, 0x00000410, 0x06)
		{
		}
	}

and a proper SSDT for your cpu.Since we have the same cpu you could test mine.

 ssdt.aml.zip   752bytes   33 downloads

You can also read here http://www.insanelym...howtopic=278374

Thanks! Going to test this.

EDIT tested:

5/4/12 10:51:06.000 PM kernel[0]: MSRDumper CoreMulti(33) 
5/4/12 10:51:06.000 PM kernel[0]: MSRDumper PStatesReached: 16 32 33 34 
5/4/12 10:51:07.000 PM kernel[0]: MSRDumper CoreMulti(33) 
5/4/12 10:51:07.000 PM kernel[0]: MSRDumper PStatesReached: 16 32 33 34 
5/4/12 10:51:07.000 PM kernel[0]: MSRDumper CoreMulti(32) 
5/4/12 10:51:07.000 PM kernel[0]: MSRDumper PStatesReached: 16 32 33 34 
5/4/12 10:51:08.000 PM kernel[0]: MSRDumper CoreMulti(32) 
5/4/12 10:51:08.000 PM kernel[0]: MSRDumper PStatesReached: 16 32 33 34 
5/4/12 10:51:08.000 PM kernel[0]: MSRDumper CoreMulti(32) 
5/4/12 10:51:08.000 PM kernel[0]: MSRDumper PStatesReached: 16 32 33 34

It seems that it works, but how to calculate your PStates? Is there an app or some (easy) method to do that?
It never hits 34 btw, is this normal? Could you show me how to generate a SSDT?

I have GenerateCStates=Yes & DropSSDT=Yes in boot.plist to boot successfully.

Thanks for helping me with this.