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DSDT - Vanilla Speedstep - Generic Scope (_PR)


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#421
oldnapalm

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Have you tried to run AppleIntelCPUPowerManagement without any changes to DSDT? I have an Acer Aspire 5920 which also has _CST in SSDT, and SpeedStep works in 10.5.8 with no changes to DSDT, just removing Disabler kext. I tried to copy _CST and _PSS from SSDT dump to DSDT.aml but noticed no difference.

#422
mm67

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This way I can get P-states and C-states working even if EIST and C-states are disabled in bios.
This P-state table is for Q9550.

Scope (_PR)    {        Processor (CPU0, 0x00, 0x00000410, 0x06) {}        Processor (CPU1, 0x01, 0x00000410, 0x06) {}        Processor (CPU2, 0x02, 0x00000410, 0x06) {}        Processor (CPU3, 0x03, 0x00000410, 0x06) {}        Name (CFGD, 0x040383F2)        Name (PDC0, 0x80000000)    }    Scope (_PR.CPU0)    {        Method (_CST, 0, NotSerialized)        {            If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10                ))))            {                Return (Package (0x02)                {                    One,                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (FFixedHW,                                 0x00,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000000, // Address                                ,)                        },                        One,                         0x9D,                         0x03E8                    }                })            }            If (And (PDC0, 0x0300))            {                If (And (CFGD, 0x20))                {                    Return (Package (0x03)                    {                        0x02,                         Package (0x04)                        {                            ResourceTemplate ()                            {                                Register (FFixedHW,                                     0x01,               // Bit Width                                    0x02,               // Bit Offset                                    0x0000000000000000, // Address                                    ,)                            },                             One,                             One,                             0x03E8                        },                         Package (0x04)                        {                            ResourceTemplate ()                            {                                Register (FFixedHW,                                     0x01,               // Bit Width                                    0x02,               // Bit Offset                                    0x0000000000000010, // Address                                    ,)                            },                             0x02,                             One,                             0x01F4                        }                    })                }            }            If (And (CFGD, 0x20))            {                Return (Package (0x03)                {                    0x02,                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (FFixedHW,                                 0x01,               // Bit Width                                0x02,               // Bit Offset                                0x0000000000000000, // Address                                ,)                        },                         One,                         One,                         0x03E8                    },                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (SystemIO,                                 0x08,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000414, // Address                                ,)                        },                         0x02,                         One,                         0x01F4                    }                })            }            Return (Package (0x02)            {                One,                 Package (0x04)                {                    ResourceTemplate ()                    {                        Register (FFixedHW,                             0x01,               // Bit Width                            0x02,               // Bit Offset                            0x0000000000000000, // Address                            ,)                    },                     One,                     One,                     0x03E8                }            })        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {          Return (Package (0x02)          {            ResourceTemplate ()            {                Register (FFixedHW,                     0x10,                    0x00,                    0x0000000000000199,                    ,)            },             ResourceTemplate ()            {                Register (FFixedHW,                     0x10,                    0x00,                    0x0000000000000198,                    ,)            }          })        }        Method (_PSS, 0, NotSerialized)        {          Return (Package (0x06)           {            Package (0x06)            {                0xB0F,                 Zero,                 0xA,                 0xA,                 0x4820,                 0x4820            },             Package (0x06)            {                0xA68,                 Zero,                 0xA,                 0xA,                 0x81E,                 0x81E            },             Package (0x06)            {                0x9C2,                 Zero,                 0xA,                 0xA,                 0x471C,                 0x471C            },             Package (0x06)            {                0x91B,                 Zero,                 0xA,                 0xA,                 0x71A,                 0x71A            },             Package (0x06)            {                0x875,                 Zero,                 0xA,                 0xA,                 0x4618,                 0x4618            },             Package (0x06)            {                0x7CE,                 Zero,                 0xA,                 0xA,                 0x616,                 0x616            }        })      }    }    Scope (_PR.CPU1)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }    Scope (_PR.CPU2)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }    Scope (_PR.CPU3)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }


With EIST and C-states disabled Windows makes cpu run hot (idling around 50) but in OSX cpu is idling around 35 degrees.

Hi William

I'm idling at around 40-43 degrees.

Also you have your own CST tables you'd be best using them instead of the MP3,1 tables used in your 3rd mod.
I'd stick with the 2nd Mod then see if you can follow ab__73's post#71 here to get C states working.

D.


I get same temperatures when I am using CST tables from my own bios. If I use MP 3,1 CST tables temps go down to 35 and IOrRegistryExplorer has CSTInfo key which is missing when using my own tables.

#423
FKA

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Hi again!

This is the "better" I made

I insert last SSDT Table value next the CPU data

I use dropssdt=yes in com.apple.Boot.plist

but notthing change.. :(

I'm sure I make some error.

Fabio


Hi Fabio

I only had success with this by adding ALL of the SSDT tables to the DSDT. For speedstep you will need to edit the values in the NPSS and SPSS sections.

In your case this means adding all 16 SSDT tables. I'm sure you can leave out the information for CPU cores that are not in use but to make it as easy as possible for you, simply append the SSDT tables to the end of your DSDT starting with SSDT 0 then SSDT 1 .... etc

As oldnapalm says - some people don't need to add SSDT tables at all as that information must already be being passed to the OS.

D

#424
mm67

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Same dsdt.aml works great even on Ubuntu, gives 6 P-states and C-states 1 and 2 even when with EIST and all C-states disabled from bios. Just noticed that with linux dmesg one can see which C-states are loaded.

#425
William Parker

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@mm67

This way I can get P-states and C-states working even if EIST and C-states are disabled in bios.
This P-state table is for Q9550.

Scope (_PR)    {        Processor (CPU0, 0x00, 0x00000410, 0x06) {}        Processor (CPU1, 0x01, 0x00000410, 0x06) {}        Processor (CPU2, 0x02, 0x00000410, 0x06) {}        Processor (CPU3, 0x03, 0x00000410, 0x06) {}        Name (CFGD, 0x040383F2)        Name (PDC0, 0x80000000)    }    Scope (_PR.CPU0)    {        Method (_CST, 0, NotSerialized)        {            If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10                ))))            {                Return (Package (0x02)                {                    One,                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (FFixedHW,                                 0x00,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000000, // Address                                ,)                        },                        One,                         0x9D,                         0x03E8                    }                })            }            If (And (PDC0, 0x0300))            {                If (And (CFGD, 0x20))                {                    Return (Package (0x03)                    {                        0x02,                         Package (0x04)                        {                            ResourceTemplate ()                            {                                Register (FFixedHW,                                     0x01,               // Bit Width                                    0x02,               // Bit Offset                                    0x0000000000000000, // Address                                    ,)                            },                             One,                             One,                             0x03E8                        },                         Package (0x04)                        {                            ResourceTemplate ()                            {                                Register (FFixedHW,                                     0x01,               // Bit Width                                    0x02,               // Bit Offset                                    0x0000000000000010, // Address                                    ,)                            },                             0x02,                             One,                             0x01F4                        }                    })                }            }            If (And (CFGD, 0x20))            {                Return (Package (0x03)                {                    0x02,                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (FFixedHW,                                 0x01,               // Bit Width                                0x02,               // Bit Offset                                0x0000000000000000, // Address                                ,)                        },                         One,                         One,                         0x03E8                    },                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (SystemIO,                                 0x08,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000414, // Address                                ,)                        },                         0x02,                         One,                         0x01F4                    }                })            }            Return (Package (0x02)            {                One,                 Package (0x04)                {                    ResourceTemplate ()                    {                        Register (FFixedHW,                             0x01,               // Bit Width                            0x02,               // Bit Offset                            0x0000000000000000, // Address                            ,)                    },                     One,                     One,                     0x03E8                }            })        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {          Return (Package (0x02)          {            ResourceTemplate ()            {                Register (FFixedHW,                     0x10,                    0x00,                    0x0000000000000199,                    ,)            },             ResourceTemplate ()            {                Register (FFixedHW,                     0x10,                    0x00,                    0x0000000000000198,                    ,)            }          })        }        Method (_PSS, 0, NotSerialized)        {          Return (Package (0x06)           {            Package (0x06)            {                0xB0F,                 Zero,                 0xA,                 0xA,                 0x4820,                 0x4820            },             Package (0x06)            {                0xA68,                 Zero,                 0xA,                 0xA,                 0x81E,                 0x81E            },             Package (0x06)            {                0x9C2,                 Zero,                 0xA,                 0xA,                 0x471C,                 0x471C            },             Package (0x06)            {                0x91B,                 Zero,                 0xA,                 0xA,                 0x71A,                 0x71A            },             Package (0x06)            {                0x875,                 Zero,                 0xA,                 0xA,                 0x4618,                 0x4618            },             Package (0x06)            {                0x7CE,                 Zero,                 0xA,                 0xA,                 0x616,                 0x616            }        })      }    }    Scope (_PR.CPU1)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }    Scope (_PR.CPU2)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }    Scope (_PR.CPU3)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }


With EIST and C-states disabled Windows makes cpu run hot (idling around 50) but in OSX cpu is idling around 35 degrees.



I get same temperatures when I am using CST tables from my own bios. If I use MP 3,1 CST tables temps go down to 35 and IOrRegistryExplorer has CSTInfo key which is missing when using my own tables.



Hi, Have you seen the post AB__75 post #71 that FormerlyKnownAs suggested? Maybe because of the hardcoded memory addresses the C-states do not reflect in the ioregexplorer. I tried making a fresh 10.5.4 install to run the Voodoo Kernel. Did not work. So presently exploring alternative ways to find hardcoded addresses of the C-states. Will be grateful if you share some insight.
Thank you.

#426
keeza

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First my heartfelt gratitude goes out to all the forum members here, whose help has been invaluable, especially Master Chief & FormerlyKnownAs.
I have attached here 3 variants of DSDT mods. The first one was done following FormerlyKnownAs first post here. I had no CST evaluation errors to start with & my ACPI dumps yielded 5 SSDTs of which 4 were CPUcXst and the fifth one was CpuPm. I also had the FACP table with _CST support : 00 & C2 Latency : 005A & C3 Latency : 0384.
Frankly the high temps were bothering me 60 deg. C on load. I could see stepping in CPU-i. So that was some relief. After a second read through I understood that I needed to enter the latencies from the FACP into the SPSS part. Which is what I did in the Second mod. which brought temps down to 40 on idle and about 50 on load.
But I had seen members on this thread getting temps in their 30s. I preferred not to replace ROISOFT's MacPro 3,1 code into my DSDT but I tried just to see and it works with idle temps down to about 34.
Am I doing anything wrong by replacing my obtained SSDT tables with these?
I see FormerlyKnownAs DSDT attached in the first post have "Method (_PPC, 0, NotSerialized)". Can it be ignored because it returns Zero?
Also it has Method (_PCT, 0, NotSerialized) which I don't. Should it be there?
And among other things I will be very grateful if someone could point errors in the Speed stepping and related parts, and how to set them right.
My sincerest thanks to all who have shared their knowledge here. ;)


Check out my previous post #335. I used my own dumps with Macpro3,1 additions where I have mentioned. I wanted to keep my dsdt additions relating to speedstep and CST as close to my original dumps as poss.
My idles are around 35 degrees and seems to run fine.

Also, do you have AppleLPC loading - run kextstat in terminal to find out. There is a previous post from member Beerkexd relating to this. There doesnt seem to be a device id fix in your dsdt for your LPC device (you may have addressed this using another method). My understanding is that AppleLPC kext needs to load in order for C-States to work.


...and by the way line 3307 and 3316 of your dsdt need to have the same value for the cmos fix for SL

#427
William Parker

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@keeza
Thanks friend. I will look at your dsdt and see what I have mucked up in mine, and try set it right including cmos fix. But I too am idling around 34 no problems. As for the LPC I have edited it's plist because I was unaware of the dsdt patch for it. I will do it soon.
Another thing - 2 days earlier on moofspeak irc I met mojodojo and he said that his CPU-i app works in 64 bit kernel & also provided a link on applelife russian site for it. I somehow lost the link. It was a version much greater than 1.0.3. Any clues? Coolbook does not work, shows all freq as 0. I simply use temperature monitor to guess what's happening.
Thanks a ton

(Edit)
Your SPSS Package should have the latency values from your FACP table which are presently A0 & 0A. This was input by fromerlyKA because he did not have meaningful latency values. Probably you do (almost my MB). Your comments?

#428
FKA

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This way I can get P-states and C-states working even if EIST and C-states are disabled in bios.
This P-state table is for Q9550.

Scope (_PR)    {        Processor (CPU0, 0x00, 0x00000410, 0x06) {}        Processor (CPU1, 0x01, 0x00000410, 0x06) {}        Processor (CPU2, 0x02, 0x00000410, 0x06) {}        Processor (CPU3, 0x03, 0x00000410, 0x06) {}        Name (CFGD, 0x040383F2)        Name (PDC0, 0x80000000)    }    Scope (_PR.CPU0)    {        Method (_CST, 0, NotSerialized)        {            If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10                ))))            {                Return (Package (0x02)                {                    One,                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (FFixedHW,                                 0x00,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000000, // Address                                ,)                        },                        One,                         0x9D,                         0x03E8                    }                })            }            If (And (PDC0, 0x0300))            {                If (And (CFGD, 0x20))                {                    Return (Package (0x03)                    {                        0x02,                         Package (0x04)                        {                            ResourceTemplate ()                            {                                Register (FFixedHW,                                     0x01,               // Bit Width                                    0x02,               // Bit Offset                                    0x0000000000000000, // Address                                    ,)                            },                             One,                             One,                             0x03E8                        },                         Package (0x04)                        {                            ResourceTemplate ()                            {                                Register (FFixedHW,                                     0x01,               // Bit Width                                    0x02,               // Bit Offset                                    0x0000000000000010, // Address                                    ,)                            },                             0x02,                             One,                             0x01F4                        }                    })                }            }            If (And (CFGD, 0x20))            {                Return (Package (0x03)                {                    0x02,                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (FFixedHW,                                 0x01,               // Bit Width                                0x02,               // Bit Offset                                0x0000000000000000, // Address                                ,)                        },                         One,                         One,                         0x03E8                    },                     Package (0x04)                    {                        ResourceTemplate ()                        {                            Register (SystemIO,                                 0x08,               // Bit Width                                0x00,               // Bit Offset                                0x0000000000000414, // Address                                ,)                        },                         0x02,                         One,                         0x01F4                    }                })            }            Return (Package (0x02)            {                One,                 Package (0x04)                {                    ResourceTemplate ()                    {                        Register (FFixedHW,                             0x01,               // Bit Width                            0x02,               // Bit Offset                            0x0000000000000000, // Address                            ,)                    },                     One,                     One,                     0x03E8                }            })        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {          Return (Package (0x02)          {            ResourceTemplate ()            {                Register (FFixedHW,                     0x10,                    0x00,                    0x0000000000000199,                    ,)            },             ResourceTemplate ()            {                Register (FFixedHW,                     0x10,                    0x00,                    0x0000000000000198,                    ,)            }          })        }        Method (_PSS, 0, NotSerialized)        {          Return (Package (0x06)           {            Package (0x06)            {                0xB0F,                 Zero,                 0xA,                 0xA,                 0x4820,                 0x4820            },             Package (0x06)            {                0xA68,                 Zero,                 0xA,                 0xA,                 0x81E,                 0x81E            },             Package (0x06)            {                0x9C2,                 Zero,                 0xA,                 0xA,                 0x471C,                 0x471C            },             Package (0x06)            {                0x91B,                 Zero,                 0xA,                 0xA,                 0x71A,                 0x71A            },             Package (0x06)            {                0x875,                 Zero,                 0xA,                 0xA,                 0x4618,                 0x4618            },             Package (0x06)            {                0x7CE,                 Zero,                 0xA,                 0xA,                 0x616,                 0x616            }        })      }    }    Scope (_PR.CPU1)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }    Scope (_PR.CPU2)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }    Scope (_PR.CPU3)    {        Method (_CST, 0, NotSerialized)        {            Return (^^CPU0._CST ())        }        Method (_PPC, 0, NotSerialized)        {            Return (Zero)        }        Method (_PCT, 0, NotSerialized)        {            Return (^^CPU0._PCT ())        }        Method (_PSS, 0, NotSerialized)        {            Return (^^CPU0._PSS ())        }    }


With EIST and C-states disabled Windows makes cpu run hot (idling around 50) but in OSX cpu is idling around 35 degrees.



I get same temperatures when I am using CST tables from my own bios. If I use MP 3,1 CST tables temps go down to 35 and IOrRegistryExplorer has CSTInfo key which is missing when using my own tables.


Hi mm67

I've adapted your code with MP3,1 _cst for my Q9450 with 3 steps. I works just fine and is much tidier than the code I was using. Still no c-states for me although I still have cst info in ioreg.

{Processor (CPU0, 0x00, 0x00000410, 0x06) {}Processor (CPU1, 0x01, 0x00000410, 0x06) {}Processor (CPU2, 0x02, 0x00000410, 0x06) {}Processor (CPU3, 0x03, 0x00000410, 0x06) {}Name (CFGD, 0x040383F2)Name (PDC0, 0x80000000)}Scope (_PR.CPU0){Method (_CST, 0, NotSerialized){If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10)))){Return (Package (0x02){One,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x00, // Bit Width0x00, // Bit Offset0x0000000000000000, // Address,)},One,0x9D,0x03E8}})}If (And (PDC0, 0x0300)){If (And (CFGD, 0x20)){Return (Package (0x03){0x02,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000000, // Address,)},One,One,0x03E8},Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000010, // Address,)},0x02,One,0x01F4}})}}If (And (CFGD, 0x20)){Return (Package (0x03){0x02,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000000, // Address,)},One,One,0x03E8},Package (0x04){ResourceTemplate (){Register (SystemIO,0x08, // Bit Width0x00, // Bit Offset0x0000000000000414, // Address,)},0x02,One,0x01F4}})}Return (Package (0x02){One,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000000, // Address,)},One,One,0x03E8}})}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (Package (0x02){ResourceTemplate (){Register (FFixedHW,0x10,0x00,0x0000000000000199,,)},ResourceTemplate (){Register (FFixedHW,0x10,0x00,0x0000000000000198,,)}})}Method (_PSS, 0, NotSerialized){Return (Package (0x03){            Package (0x06)            {                0x0C20,                 0x000124F8,                 0xA0,                 0x0A,                 0x0820,                 0x0820            },             Package (0x06)            {                0x0A9C,                 0xFDE8,                 0xA0,                 0x0A,                 0x071C,                 0x071C            },             Package (0x06)            {                0x0918,                 0xEA60,                 0xA0,                 0x0A,                 0x061A,                 0x061A            }})}}Scope (_PR.CPU1){Method (_CST, 0, NotSerialized){Return (^^CPU0._CST ())}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (^^CPU0._PCT ())}Method (_PSS, 0, NotSerialized){Return (^^CPU0._PSS ())}}Scope (_PR.CPU2){Method (_CST, 0, NotSerialized){Return (^^CPU0._CST ())}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (^^CPU0._PCT ())}Method (_PSS, 0, NotSerialized){Return (^^CPU0._PSS ())}}Scope (_PR.CPU3){Method (_CST, 0, NotSerialized){Return (^^CPU0._CST ())}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (^^CPU0._PCT ())}Method (_PSS, 0, NotSerialized){Return (^^CPU0._PSS ())}}

D

#429
mm67

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Hi mm67

I've adapted your code with MP3,1 _cst for my Q9450 with 3 steps. I works just fine and is much tidier than the code I was using. Still no c-states for me although I still have cst info in ioreg.


How does one know if C-states are working or not. Is there some tool for OSX that shows it ?
I verified that this gives working C-states by loading this to Ubuntu and running cat /proc/acpi/processor/CPU0/power but I have no idea how to check this in OSX.

#430
FKA

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How does one know if C-states are working or not. Is there some tool for OSX that shows it ?
I verified that this gives working C-states by loading this to Ubuntu and running cat /proc/acpi/processor/CPU0/power but I have no idea how to check this in OSX.


Firstly - I have no cst tables and FACP states cst support - 0 so don't expect to get c-states working even uisng ab__73's method to find the hard coded memory addresses for cst.

using mark-i I'd expect if I entered a C1 or 2 state, to see any of the following - a voltage drop, cpu fan speed drop or CPU temp drop - beyond the level of my lowest P state multi.

It's not too scientific and I'd like a better method if anybody has one!

D.

#431
mm67

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Firstly - I have no cst tables and FACP states cst support - 0 so don't expect to get c-states working even uisng ab__73's method to find the hard coded memory addresses for cst.

using mark-i I'd expect if I entered a C1 or 2 state, to see any of the following - a voltage drop, cpu fan speed drop or CPU temp drop - beyond the level of my lowest P state multi.

It's not too scientific and I'd like a better method if anybody has one!

D.


Only difference that I can see is that temps drop from 40 to 35 degrees when cst is working.

#432
yeehaa

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Another thing - 2 days earlier on moofspeak irc I met mojodojo and he said that his CPU-i app works in 64 bit kernel & also provided a link on applelife russian site for it. I somehow lost the link. It was a version much greater than 1.0.3. Any clues? Coolbook does not work, shows all freq as 0. I simply use temperature monitor to guess what's happening.
Thanks a ton


cpu-i is now called voodoomonitor and is on version 1.0.7 now. head over to applelife n do a search there..

#433
mm67

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Firstly - I have no cst tables and FACP states cst support - 0 so don't expect to get c-states working even uisng ab__73's method to find the hard coded memory addresses for cst.

using mark-i I'd expect if I entered a C1 or 2 state, to see any of the following - a voltage drop, cpu fan speed drop or CPU temp drop - beyond the level of my lowest P state multi.

It's not too scientific and I'd like a better method if anybody has one!

D.


You mean your FACP looks like this ?

[000h 0000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */[004h 0004  4]                 Table Length : 00000074[008h 0008  1]                     Revision : 01[009h 0009  1]                     Checksum : 1B[00Ah 0010  6]                       Oem ID : "GBT   "[010h 0016  8]                 Oem Table ID : "GBTUACPI"[018h 0024  4]                 Oem Revision : 42302E31[01Ch 0028  4]              Asl Compiler ID : "GBTU"[020h 0032  4]        Asl Compiler Revision : 01010101[024h 0036  4]                 FACS Address : DFEE0000[028h 0040  4]                 DSDT Address : DFEE2180[02Ch 0044  1]                        Model : 01[02Dh 0045  1]                   PM Profile : 01 (Desktop)[02Eh 0046  2]                SCI Interrupt : 0009[030h 0048  4]             SMI Command Port : 000000B2[034h 0052  1]            ACPI Enable Value : A1[035h 0053  1]           ACPI Disable Value : A0[036h 0054  1]               S4BIOS Command : 00[037h 0055  1]              P-State Control : 34[038h 0056  4]     PM1A Event Block Address : 00000400[03Ch 0060  4]     PM1B Event Block Address : 00000000[040h 0064  4]   PM1A Control Block Address : 00000404[044h 0068  4]   PM1B Control Block Address : 00000000[048h 0072  4]    PM2 Control Block Address : 00000450[04Ch 0076  4]       PM Timer Block Address : 00000408[050h 0080  4]           GPE0 Block Address : 00000420[054h 0084  4]           GPE1 Block Address : 00000000[058h 0088  1]       PM1 Event Block Length : 04[059h 0089  1]     PM1 Control Block Length : 02[05Ah 0090  1]     PM2 Control Block Length : 01[05Bh 0091  1]        PM Timer Block Length : 04[05Ch 0092  1]            GPE0 Block Length : 10[05Dh 0093  1]            GPE1 Block Length : 00[05Eh 0094  1]             GPE1 Base Offset : 00[05Fh 0095  1]                 _CST Support : 00[060h 0096  2]                   C2 Latency : 005A[062h 0098  2]                   C3 Latency : 0384[064h 0100  2]               CPU Cache Size : 0000[066h 0102  2]           Cache Flush Stride : 0000[068h 0104  1]            Duty Cycle Offset : 01[069h 0105  1]             Duty Cycle Width : 03[06Ah 0106  1]          RTC Day Alarm Index : 0D[06Bh 0107  1]        RTC Month Alarm Index : 00[06Ch 0108  1]            RTC Century Index : 00[06Dh 0109  2]   Boot Flags (decoded below) : 0010              Legacy Devices Supported (V2) : 0           8042 Present on ports 60/64 (V2) : 0                       VGA Not Present (V4) : 0                     MSI Not Supported (V4) : 0               PCIe ASPM Not Supported (V4) : 1[06Fh 0111  1]                     Reserved : 00[070h 0112  4]        Flags (decoded below) : 000004A5     WBINVD instruction is operational (V1) : 1             WBINVD flushes all caches (V1) : 0                   All CPUs support C1 (V1) : 1                 C2 works on MP system (V1) : 0           Control Method Power Button (V1) : 0           Control Method Sleep Button (V1) : 1       RTC wake not in fixed reg space (V1) : 0           RTC can wake system from S4 (V1) : 1                       32-bit PM Timer (V1) : 0                     Docking Supported (V1) : 0              Reset Register Supported (V2) : 1                           Sealed Case (V3) : 0                   Headless - No Video (V3) : 0       Use native instr after SLP_TYPx (V3) : 0             PCIEXP_WAK Bits Supported (V4) : 0                    Use Platform Timer (V4) : 0              RTC_STS valid on S4 wake (V4) : 0               Remote Power-on capable (V4) : 0                Use APIC Cluster Model (V4) : 0    Use APIC Physical Destination Mode (V4) : 0

I get this when I disable C-states from bios, but cst works anyway using dsdt.aml, both in OSX and Linux.

/edit

Checked again, FACP table stays the same when disabling cst from bios but RSDT looses SSDT table addresses.

#434
FKA

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You mean your FACP looks like this ?

[000h 0000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */[004h 0004  4]                 Table Length : 00000074[008h 0008  1]                     Revision : 01[009h 0009  1]                     Checksum : 1B[00Ah 0010  6]                       Oem ID : "GBT   "[010h 0016  8]                 Oem Table ID : "GBTUACPI"[018h 0024  4]                 Oem Revision : 42302E31[01Ch 0028  4]              Asl Compiler ID : "GBTU"[020h 0032  4]        Asl Compiler Revision : 01010101[024h 0036  4]                 FACS Address : DFEE0000[028h 0040  4]                 DSDT Address : DFEE2180[02Ch 0044  1]                        Model : 01[02Dh 0045  1]                   PM Profile : 01 (Desktop)[02Eh 0046  2]                SCI Interrupt : 0009[030h 0048  4]             SMI Command Port : 000000B2[034h 0052  1]            ACPI Enable Value : A1[035h 0053  1]           ACPI Disable Value : A0[036h 0054  1]               S4BIOS Command : 00[037h 0055  1]              P-State Control : 34[038h 0056  4]     PM1A Event Block Address : 00000400[03Ch 0060  4]     PM1B Event Block Address : 00000000[040h 0064  4]   PM1A Control Block Address : 00000404[044h 0068  4]   PM1B Control Block Address : 00000000[048h 0072  4]    PM2 Control Block Address : 00000450[04Ch 0076  4]       PM Timer Block Address : 00000408[050h 0080  4]           GPE0 Block Address : 00000420[054h 0084  4]           GPE1 Block Address : 00000000[058h 0088  1]       PM1 Event Block Length : 04[059h 0089  1]     PM1 Control Block Length : 02[05Ah 0090  1]     PM2 Control Block Length : 01[05Bh 0091  1]        PM Timer Block Length : 04[05Ch 0092  1]            GPE0 Block Length : 10[05Dh 0093  1]            GPE1 Block Length : 00[05Eh 0094  1]             GPE1 Base Offset : 00[05Fh 0095  1]                 _CST Support : 00[060h 0096  2]                   C2 Latency : 005A[062h 0098  2]                   C3 Latency : 0384[064h 0100  2]               CPU Cache Size : 0000[066h 0102  2]           Cache Flush Stride : 0000[068h 0104  1]            Duty Cycle Offset : 01[069h 0105  1]             Duty Cycle Width : 03[06Ah 0106  1]          RTC Day Alarm Index : 0D[06Bh 0107  1]        RTC Month Alarm Index : 00[06Ch 0108  1]            RTC Century Index : 00[06Dh 0109  2]   Boot Flags (decoded below) : 0010              Legacy Devices Supported (V2) : 0           8042 Present on ports 60/64 (V2) : 0                       VGA Not Present (V4) : 0                     MSI Not Supported (V4) : 0               PCIe ASPM Not Supported (V4) : 1[06Fh 0111  1]                     Reserved : 00[070h 0112  4]        Flags (decoded below) : 000004A5     WBINVD instruction is operational (V1) : 1             WBINVD flushes all caches (V1) : 0                   All CPUs support C1 (V1) : 1                 C2 works on MP system (V1) : 0           Control Method Power Button (V1) : 0           Control Method Sleep Button (V1) : 1       RTC wake not in fixed reg space (V1) : 0           RTC can wake system from S4 (V1) : 1                       32-bit PM Timer (V1) : 0                     Docking Supported (V1) : 0              Reset Register Supported (V2) : 1                           Sealed Case (V3) : 0                   Headless - No Video (V3) : 0       Use native instr after SLP_TYPx (V3) : 0             PCIEXP_WAK Bits Supported (V4) : 0                    Use Platform Timer (V4) : 0              RTC_STS valid on S4 wake (V4) : 0               Remote Power-on capable (V4) : 0                Use APIC Cluster Model (V4) : 0    Use APIC Physical Destination Mode (V4) : 0

I get this when I disable C-states from bios, but cst works anyway using dsdt.aml, both in OSX and Linux.

/edit

Checked again, FACP table stays the same when disabling cst from bios but RSDT looses SSDT table addresses.


Something along those lines - but I have no cst tables in SSDT (hence borrowing from MP3,1) and the only option in BIOS is for C1E ..

Only difference that I can see is that temps drop from 40 to 35 degrees when cst is working.


I've never got below 40 degrees - so a deffinate sign you've entered a c-state if your getting 35.C

EDIT## do you notice any cst entry present/ not present under ACPI_SMC in ioreg when you change cst tables from your own to MP3,1 in DSDT and switch between 40.C and 35.C idle??

D

#435
mm67

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Something along those lines - but I have no cst tables in SSDT (hence borrowing from MP3,1) and the only option in BIOS is for C1E ..



I've never got below 40 degrees - so a deffinate sign you've entered a c-state if your getting 35.C

EDIT## do you notice any cst entry present/ not present under ACPI_SMC in ioreg when you change cst tables from your own to MP3,1 in DSDT and switch between 40.C and 35.C idle??

D


I get the CSTInfo key only with MP3.1 cst, if I try to use my own tables then I have no cst entries.

#436
FKA

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I get the CSTInfo key only with MP3.1 cst, if I try to use my own tables then I have no cst entries.


A Guess - if you found the hard coded memory addresses using your own cst I presume they'd work for you also!


mark-i
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Attached File  mark_i_custom.w.kext.zip   302.46KB   11 downloads
Attached File  mark_i.force_nehalem.zip   299.51KB   7 downloads - Still testing

curt' - mark @the project
http://www.insanelym...p;#entry1287585

#437
Master Chief

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Give me some time and I'll add part two, showing C-States working, lowering the CPU temperature by almost 25 degrees centigrade!

I get the CSTInfo key only with MP3.1 cst, if I try to use my own tables then I have no cst entries.


ACPI_SMC_PlatformPlugin.kext adds this property after evaluating your _CST object i.e. it has to be properly formatted and valid before this shows up.

#438
keeza

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(Edit)
Your SPSS Package should have the latency values from your FACP table which are presently A0 & 0A. This was input by fromerlyKA because he did not have meaningful latency values. Probably you do (almost my MB). Your comments?


Interesting. Would you happen to know the post number from FKA that you refer to?

Speedstepping and CStates seem to be working perfectly for me at the moment.

#439
Beerkex'd

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Here's what I got with LegacyAGPM.kext, LegacyACPI_SMC_PP.kext + adding the SBUS device to my DSDT. And of course the C/P-states. I'm still using iMac9,1 as model identifier - And so Snow Leopard thinks my E8500 is a Penryn CPU, which, being the mobile version of Wolfdale, is reasonably close.

/EDIT - It was discussed earlier in this thread but for those who missed it, you need to insert the device ID of your video card in LegacyAGPM.kext for it to work.
The motherboard SBUS device must match the device ID in LegacyACPI_SMC_PP.kext - if it doesn't, you have to patch it in the DSDT - see Master Chief's P5K Pro thread.
I use iMac9,1 as model identifier, so I've replaced P5K Pro with iMac9,1 in the two kexts.
Attached File  AGPM.png   61.14KB   128 downloadsAttached File  GPU_Sensor.png   41.61KB   116 downloadsAttached File  IOHWControl.png   61.78KB   116 downloads
Attached File  SBUS.png   124.39KB   114 downloadsAttached File  CPU_i.png   39.68KB   86 downloadsAttached File  Penryn.png   53.62KB   81 downloads
Thanks Master Chief, for all your awesome work and research.

I still have some testing to do to see if it really works. So far P-States and S3 sleep/wake from USB/PWRB is still working.

I have a rarely occurring issue where the 9800 GTX+ fan will spin up to full speed, followed by instant reboot.
I want to see if that still happens but I haven't figured out how to trigger it (EDIT - yay, it seems to be gone for good)

btw if you keep the SPKR device in the DSDT, Parallels will use it when it boots a virtual machine! I guess they must have left the code in from the PC version.
I didn't have to patch the device ID of the SBUS device.

Here's my DSDT if you want to see how it works on ASUS P5Q-E.
(/EDIT - removed - go here: http://www.insanelym...p...t&p=1299409 )

/EDIT 24/10 (fixed some stupid mistakes) - Here are my modified LegacyAGPM.kext and LegacyACPI_SMC_PP.kexts, I've changed model identifier to iMac9,1 in both and in LegacyAGPM.kext I've replaced device ID of the Geforce 9400 (used in iMac9,1) with 0x612 of my 9800GTX+.
Both load from /EFI/Extra/Extensions.mkext.
Attached File  iMac9_1_GF9800GTX_LegacyKexts.zip   4.26KB   32 downloads

#440
William Parker

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Interesting. Would you happen to know the post number from FKA that you refer to?

Speedstepping and CStates seem to be working perfectly for me at the moment.


Sorry, My bad. The post #83 is by Master Chief
Thanks





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