DSDT - Vanilla Speedstep - Generic Scope (_PR)

[Matthew L.]

At first, thanks for working on the vanilla speedstepping so hard, thanks for the ton of collected info!

 

I've jumped into making my system speedstep-capable too, but I've hit some walls (or not). Let me tell everything about the process.

 

I have tried to append my SSDT tables to my DSDT, but while I was doing it, I noticed that everything I have in my IST and PM tables aren't supposed to be used. (The post #443.) Then I've noticed some using VoodooMonitor and I've tried the app, well, why not. I was surprised: I've had 4 P-States and speedstepping (but no voltage changing) w/o any work on the DSDT. Okay, then I've tried to use the AppleIntelCPUPM kext, but I've got some errors about missing _CST. I've re-read the instructions, appended the MacPro3,1 _CST tables to my CPU's + the CFGD and PDC0 addresses in DSDT, and done, no _CST errors at boot, but in VoodooMonitor I get jumping voltages of 1.212V and 1.116V, with 1.212V dominating at a fixed, 6x multiplier, which is strange (and temperature is low, 30 and 32-33C idle). Is it normal, or is there something wrong in my DSDT? (If this is relevant: I have EIST and C1E enabled in BIOS.)

 

Thanks in advance!

(And sorry for the not-so-shiny-language-knowledge. )

 

EDIT: About the 1.116V: there is no 1.116V, but 1.132 at the lowest P-State...weird.

Archive.zip

[Master Chief]

At first, thanks for working on the vanilla speedstepping so hard, thanks for the ton of collected info!

 

I've jumped into making my system speedstep-capable too, but I've hit some walls (or not). Let me tell everything about the process.

 

I have tried to append my SSDT tables to my DSDT, but while I was doing it, I noticed that everything I have in my IST and PM tables aren't supposed to be used. (The post #443.)...

The attached archive contains only four files, but your SSDT shows 4 IST and 4 CST tables. Please include all files in a new archive. Now. I take it that you had something like this in your original DSDT:

		Processor (CPU0, 0x00, 0x00000410, 0x06 {}
	Processor (CPU1, 0x01, 0x00000410, 0x06 {}
	Processor (CPU2, 0x02, 0x00000410, 0x06 {}
	Processor (CPU3, 0x03, 0x00000410, 0x06 {}

If yes, then please also include your original/unmodified DSDT so that I can look into loading your CPUPM table – which is responsible for loading your IST/CST tables and without this table... there is no support for Intel SpeedStep Technology.

 

You may want to try something like this to remedy it:

	Scope (_PR)
{
Processor (CPU0, 0x00, 0x00000410, 0x06)
{
	OperationRegion (PMBL, SystemMemory, [color="#FF0000"][b]0x00000000[/b][/color], [color="#FF0000"][b]0x0000[/b][/color])
	Name (HNDL, 0x80000000)
	Name (TBLD, 0x80)

	Method (_INI, 0, NotSerialized)
	{
		if (LNot (And (TBLD, One)))
		{
			Or (TBLD, One, TBLD)
			Load (PMBL, HNDL)
		}
	}
}
Processor (CPU1, 0x01, 0x00000410, 0x06) {}
Processor (CPU2, 0x02, 0x00000410, 0x06) {}
Processor (CPU3, 0x03, 0x00000410, 0x06) {}
.....

But don't forget to fill in the correct address and table length (both in red) because this stub will not initialize properly without the right address and length specified!

 

This way you only need to add a customized _PSS() Method – your motherboard already includes a _CST method – with data for say an OC'ed Intel CPU or when the P-States are not what you want them to be. Have fun now

 

p.s. You only need to add this new method when that table isn't loading, which I can't tell now since I don't have access to all the required information/data.

[Matthew L.]

I'll attach everything about my DSDT-patching project in this post.

I promise, these were the only related SSDT tables that I could rip through Everest, just like FormerlyKnownAs with his mobo I couldn't get any CST tables. About the number of 4, I'm sure this is because of the max. supported cores, because as I've stated earlier, no other ACPI tables were available for dump, and at the time of writing the post, I've double-checked with the newest version of Everest.

BTW, at the time of seeing p-states and speedstepping w/o voltage changes I was using the dsdt_fix_f8d.dsl.

About the archive: the dsdt with appended MP3,1 _CST tables is the one with the _mp31 ending, and the dsdt_f8d is the virgin, untouched, straight-from-bios DSDT table, and the one with the _fix_ is without any speedstep-related modifications. (From koalala's ACPI patcher v0.2 b5 IIRC.)

About the maybe-fix, which table's address should I provide there?

 

n' of course, thanks for helping a newbie!

 

By looking at the VoodooMonitor the p-states for me seem correct, it looks exactly like what it should do (reflects the Windows-stepping, with proper voltages), so I don't have to add a _PSS table, right? And which table should your code load for me?

'bout data, I've provided everything I could get from my PC, for sure, so I'll wait your answer, because I'm curious about what can be missing.

Archive.zip

[verdant]

@ Master Chief

 

I have yet to patch my DSDT with C-state objects, as I am still uncertain about determining/calculating my exact P-states data for Name (_PSS, Package () given the difference of opinion between yourself and FormerlyKnownAs.....I do not want to damage my CPU by using any incorrect values.....

 

However, I wanted to report that my current DSDT is only fixed for RTC (for CMOS reset fix) and HDEF (for audio with AD1988b legacy kext) and find that without OpenHaltRestart.kext in /Extra, I can cold start and shutdown without any problem but selecting Restart (warm boot) in the Apple menu gives me the same result selecting Sleep.....i.e. the display goes black but the PC fans stay on and then the display cannot be woken up.......I need to reboot to get the display back.......I find this interesting......

 

FYI in /S/L/E I have no additional kexts (Legacy or other non-Apple 10.6.x kexts) and in /Extra I only have:

 

VoodooMonitor.kext

nForceIOATAFamily.kext

AppleNForceATA.kext

AD1988bFix.kext

lspcidrv.kext

 

with optionally OpenHaltRestart.kext for warm boot (Restart) capability......I used to have PlatformUUID too.....but have encountered no problems so far in not using it......but I can always drop it back in if I do......

 

I would like to test your "I think that warm boot (restarts) can be achieved with a simple DSDT patch because all this kext does, really, is to store 0xfe in the keyboard controller (port 64)" idea by modding my DSDT.aml as you suggest......to see if it has any effect on Sleep as well.....

 

I do not want to take this thread off-topic, so please PM me about it......

 

Cheers

verdant

[Master Chief]

I'll attach everything about my DSDT-patching project in this post.

I promise, these were the only related SSDT tables that I've ripped through Everest, just like FormerlyKnownAs states in the thread's first post, I couldn't get any CST tables. About the number of 4, I'm sure this is because of the max. supported cores, because as I've stated earlier, no other ACPI tables were available for dump, and at the time of writing the post, I've double-checked with the newest version of Everest.

Never mind. My error. I need glasses. Or I shouldn't try to do two different things, when also a power failure hits the building. Actually the guard was unaware of my presence (I never left the building) when the maintenance crew started to work on the grid. Leaving me in the dark. I'll be good for another 12-24 hours on battery power though.

 

About the maybe-fix, which table's address should I provide there?

The address and length of the CpuPm table.

 

n' of course, thanks for helping a newbie!

Right, but next time hopefully better I hope.

 

The P-states for me seem correct, it looks exactly like what it should do (reflects the Windows-stepping, with proper voltages and no jumping around), so I don't have to add a _PSS table, right? And which table should your code load for me?

When P-State stepping works... none. But your _PSS Method has only two states in SPSS/NPSS in cpu0ist; one for 3.2GHz and one for 2.4GHz so how many do you get in CPU-i / VoodooMonitor (or whatever you are using).

[Matthew L.]

Hehe, nice story! (BTW, 12-24 hrs of battery power? )

 

There may be something you've shed some light on...it's possible that I've made my dumps with clocks on 8.5x400 instead of the currently used 9x333...I'll redo the dumps tomorrow.

About p-states: it's really strange. In VoodooMonitor I get 4 for the multipliers across 6-9 (with voltages, of course), but Windows uses only 2, 6 and 9. And +1 question: so if p-states appear in VoodooMonitor without DSDT patching it cannot be considered working yet? (It did the multiplier switching without patching, but not voltage changing, because of the missing _CST. Ah, and one more: when I've seen the mult. switching (9 to 6 and 6 to 9 like in Windows) NullCPUPM was loaded, so as SleepEnabler, so AICPUPM wasn't running. Now that's strange! Or I'm stupid and missing something?)

 

But let's leave it for tomorrow, I'm tired now, was a hard week at school. Thanks again!

[Beerkex'd]

Being a developer (and ACPI language superhero) I'm sure Master Chief keeps one or more spare batteries charged and ready.

[oldnapalm]

Oh yeah. Like I said: FakeSMS sucks (it's far to limited). And please share what you did with the rest of the peeps here. I tell you this: Experimenting is good – and you showed it – even if it makes your head spin!

 

p.s. There's a small hit yes, but who cares if you care about these values.

 

I'm sure I didn't do it the proper way and it's off topic here, but you asked, so it's here

http://www.insanelymac.com/forum/index.php?showtopic=192517

If you have time please take a look, maybe you can help me to do it right.

Thanks.

[iSoprano]

What Beerke'ed said. And the reason for this is simple; text files are known to add invisible characters, making it impossible to compile without fixing the errors first. Now help others to help you. Start by attaching a correctly formatted ZIP file and who know what might happen tonight

Light bulb: I am going to help some of you GB users. Not here of course, so feel free to open a new topic and let's get cracking. A one time only offer of course!

 

Master Chief, I'm a total noab when it comes to DSDT editing and didn't realise about uploading in txt. As per your suggestions I've opened a new topic for Gigabyte users and who wouldn't want to take up the offer from Master Chief

 

http://www.insanelymac.com/forum/index.php?showtopic=192518

[Master Chief]

Master Chief, I'm a total noab when it comes to DSDT editing and didn't realise about uploading in txt. As per your suggestions I've opened a new topic for Gigabyte users and who wouldn't want to take up the offer from Master Chief

 

http://www.insanelymac.com/forum/index.php?showtopic=192518

LOL I just got a PM from Keeza about this. I guess that I have to fix PC insomnia and as a result.. I can't go to bed anymore. Oh well. Here we go!!!

 

Edit: Part I is all about the USB devices and is Done!

 

Being a developer (and ACPI language superhero) I'm sure Master Chief keeps one or more spare batteries charged and ready.

Yes sir. Mainly to compile the Mozilla (currently compiling Firefox 3.6) code base (24/365) which takes about five minutes per product, and that's when I join you guys

 

My twin 30" monitors are the bad guys here (still waiting for Apple to produce new LED replacements, which I think should be available any time soon now) but with LED lighting and a single monitor I can keep working around the clock (that's when the the generator kicks in). Well the hardware can because I am going to have some other fun now

[Matthew L.]

I've uploaded my new SSDT tables (correct frequencies should appear now), and the DSDT table with the appended SSDT loading code. Well, it doesn't work, I'm getting _CST errors at boot with it. Can you please check it?

 

EDIT: FYI, I've acquired the loading address from Everest in windows of course, it's always at the same address, isn't it?

Archive.zip

[FKA]

Righty Hoe!

 

I've got as far as changing the P and C state parts as per MC's v2.8.

 

Please note I edited and checked that it compiles on XP (Quite day at work!) - I have NOT tested this yet !

 

Chief can you please have a wee look for me - see what you think?

 

{
   Scope (_PR)
   {
       Name (NCPU, 0x04)
       Name (CFGD, 0x040383F2)
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE7F00, 0x022A)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP0)
               Or (And (TYPE, 0x7FFFFFFF), CAP0, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, One, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Name (_PSS, Package (0x03)
           {
               Package (0x06)
               {
                   0x0C20, 
                   0x000124F8, 
                   0xA0, 
                   0x0A, 
                   0x0820, 
                   0x0820
               }, 

               Package (0x06)
               {
                   0x0A9C, 
                   0xFDE8, 
                   0xA0, 
                   0x0A, 
                   0x071C, 
                   0x071C
               }, 

               Package (0x06)
               {
                   0x0918, 
                   0xEA60, 
                   0xA0, 
                   0x0A, 
                   0x061A, 
                   0x061A
               }
           })
           Method (_CST, 0, NotSerialized)
           {
               If (And (TYPE, 0x18))
               {
                   Return (^^CPU1._CST ())
               }
               Else
               {
                   Return (Package (0x02)
                   {
                       One, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x00,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000000, // Address
                                   ,)
                           }, 

                           One, 
                           0x9D, 
                           0x03E8
                       }
                   })
               }
           }
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE83C0, 0x0152)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP1)
               Or (And (TYPE, 0x7FFFFFFF), CAP1, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, 0x03, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x04)
               {
                   0x03, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               0x01,               // Access Size
                               )
                       }, 

                       One, 
                       One, 
                       0x03E8
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000814, // Address
                               ,)
                       }, 

                       0x02, 
                       One, 
                       0x01F4
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000815, // Address
                               ,)
                       }, 

                       0x03, 
                       0x11, 
                       0xFA
                   }
               })
           }
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE8520, 0x0152)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP2)
               Or (And (TYPE, 0x7FFFFFFF), CAP2, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, 0x03, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE8680, 0x0152)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP3)
               Or (And (TYPE, 0x7FFFFFFF), CAP3, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, 0x03, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
   }

 

DSDT17_10_09.dsl.zip

 

**EDIT** this is in vein and last ditch attempt to get C-states working !

 

I stopped at the SMBUS changes .... I'm saving this for another day

[Master Chief]

I've uploaded my new SSDT tables (correct frequencies should appear now), and the DSDT table with the appended SSDT loading code. Well, it doesn't work, I'm getting _CST errors at boot with it. Can you please check it?

Done. See attachments.

dsdt_pcst.dsl.zip

[h.M.M]

I just finnished extracting the SSDT in linux (Using this) which gave me 5 .aml relating SSDT.

But I couldn't make any sense of the linux howto. :/

So if someone could point me in the right direction it would be much appreciated.

 

PS. added the SSDT from my Q6600 if someone need it.

[Matthew L.]

Done. See attachments.

 

Thank You, Sir! I owe you much! I had to add a Name (TYPE, 0x80000000) (renamed later) and calculate my P-States (P-state calc gives the same values to status as control values, should I use 0-1-2-3 instead, like in the dsdt you've supplied?), but it's working! (Later added LPC dev-id patch too while searching for a solution to higher temps.) Thank You, it's just made my day!

 

I have two one questions left: my temps are a tad higher than before, so AppleIntelCPUPM makes my cores run a bit hotter, is there any fix for this? Corrected it by renaming TYPE to PDC0. And the second one: even in idle, by the time of writing this post and listening to some MP3 music through iTunes my pstates change from the lowest to the 2nd lowest frequently, is it normal, or how can I change some parameters of moving 1 state higher?

 

Dsdt.dsl attached for reference.

Edited, added some comments.

Edited once more, commented custom P-states to avoid disaster among the people willing to try this.

dsdt.dsl.zip

[FKA]

Righty Hoe!

 

I've got as far as changing the P and C state parts as per MC's v2.8.

 

Please note I edited and checked that it compiles on XP (Quite day at work!) - I have NOT tested this yet !

 

Chief can you please have a wee look for me - see what you think?

 

{
   Scope (_PR)
   {
       Name (NCPU, 0x04)
       Name (CFGD, 0x040383F2)
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE7F00, 0x022A)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP0)
               Or (And (TYPE, 0x7FFFFFFF), CAP0, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, One, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Name (_PSS, Package (0x03)
           {
               Package (0x06)
               {
                   0x0C20, 
                   0x000124F8, 
                   0xA0, 
                   0x0A, 
                   0x0820, 
                   0x0820
               }, 

               Package (0x06)
               {
                   0x0A9C, 
                   0xFDE8, 
                   0xA0, 
                   0x0A, 
                   0x071C, 
                   0x071C
               }, 

               Package (0x06)
               {
                   0x0918, 
                   0xEA60, 
                   0xA0, 
                   0x0A, 
                   0x061A, 
                   0x061A
               }
           })
           Method (_CST, 0, NotSerialized)
           {
               If (And (TYPE, 0x18))
               {
                   Return (^^CPU1._CST ())
               }
               Else
               {
                   Return (Package (0x02)
                   {
                       One, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x00,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000000, // Address
                                   ,)
                           }, 

                           One, 
                           0x9D, 
                           0x03E8
                       }
                   })
               }
           }
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE83C0, 0x0152)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP1)
               Or (And (TYPE, 0x7FFFFFFF), CAP1, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, 0x03, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x04)
               {
                   0x03, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               0x01,               // Access Size
                               )
                       }, 

                       One, 
                       One, 
                       0x03E8
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000814, // Address
                               ,)
                       }, 

                       0x02, 
                       One, 
                       0x01F4
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000815, // Address
                               ,)
                       }, 

                       0x03, 
                       0x11, 
                       0xFA
                   }
               })
           }
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE8520, 0x0152)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP2)
               Or (And (TYPE, 0x7FFFFFFF), CAP2, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, 0x03, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           OperationRegion (STBL, SystemMemory, 0xDFEE8680, 0x0152)
           Name (TYPE, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_PDC, 1, NotSerialized)
           {
               Store (SizeOf (Arg0), Local0)
               Store (Subtract (Local0, 0x08), Local1)
               CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
               Concatenate (Buffer (0x04)
                   {
                       0x00, 0x00, 0x00, 0x00
                   }, TEMP, Local2)
               _OSC (Buffer (Zero) {}, One, Zero, Local2)
           }

           Method (_OSC, 4, NotSerialized)
           {
               CreateDWordField (Arg3, 0x04, CAP3)
               Or (And (TYPE, 0x7FFFFFFF), CAP3, TYPE)
               If (LAnd (LEqual (And (TYPE, 0x09), 0x09), LNot (And (
                   TBLD, One))))
               {
                   Or (TBLD, 0x03, TBLD)
                   Load (STBL, HNDL)
               }

               Return (Arg3)
           }

           Method (_CST, 0, NotSerialized)
           {
               Return (^^CPU1._CST ())
           }
       }
   }

 

DSDT17_10_09.dsl.zip

 

**EDIT** this is in vein and last ditch attempt to get C-states working !

 

I stopped at the SMBUS changes .... I'm saving this for another day

 

I don't seem to have gained anything from this.

CPU temps are the same - I still don't enter a C states lower(higher- whatever) than 0.

P-states remain the same.

 

I tried changing CFDG to 0x40383E2 to no avail.

 

I'm going to try MP3,1 cst values but I don't hold much hope.

[Matthew L.]

I don't seem to have gained anything from this.

CPU temps are the same - I still don't enter a C states lower(higher- whatever) than 0.

P-states remain the same.

 

I tried changing CFDG to 0x40383E2 to no avail.

 

I'm going to try MP3,1 cst values but I don't hold much hope.

Maybe check my DSDT.dsl, take a peek at the differences, make some changes, specifically in P-states and location and length of the CpuPm SSDT table. It's been made by Master Chief, and His suggestions. (Important things are at top.)

[FKA]

Maybe check my DSDT.dsl, take a peek at the differences, make some changes, specifically in P-states and location and length of the CpuPm SSDT table. It's been made by Master Chief, and His suggestions. (Important things are at top.)

 

My P-states work just fine - always have

 

I have no native cst (c-state) SSDT tables with my MB and c-states is what I've never managed to get working - I'm just trying all possiblilites ATM.

 

Your DSDT doesn't contain a CPUpm table - it contains your PSS table and data and cst tables from a MacPro3,1 with modified bit width, bit offset and address values.

If you look this is the same as mine - as that's what I've just copied from MC.

 

 

D.

[FKA]

I've never got a _CST table from my motherboard too (only Cpu0Ist, Cpu1Ist and CpuPm), and it loads the CpuPm table from it's address by a code, which Master Chief suggested and writed, so if they are the same, why does mine work and yours doesn't? (No offense, just real curiousity.) And my P-states were working too, 'till the _CST errors were eliminated at boot: at this time, the multiplier stuck, so I had to append my p-states, even if it was working before without patching. AFAIK, my X48 board is more identical to the series 3 MoBos than the series 4 ones, and it's a Gigabyte, too.

 

I get working sleep, CST, and PST (voltage and multiplier autoswitching by AICPUPM kext), and normal temperatures (30/34C in idle) with this DSDT.

 

Did you extract your SSDT tables in linux?

 

do you have a C-state option in BIOS - other than C1E ??

 

EDIT### this line here:

 

OperationRegion (STBL, SystemMemory, [color="#ff0000"]0xDFEE7F00, 0x022A[/color])

 

I presume you refaring to the part in red. This is taken from your specific SSDT table mine is taken from my table.

 

        Name (SSDT, Package (0x18)
       {
           "CPU0IST ", 
           [color="#ff0000"]0xDFEE7F00, 
           0x022A, [/color]
           "CPU1IST ", 
           0xDFEE83C0, 
           0x0152, 
           "CPU0CST ", 
           Zero, 
           0xF000E816, 
           "CPU1CST ", 
           Zero, 
           0xF000E816, 
           "CPU2IST ", 
           0xDFEE8520, 
           0x0152, 
           "CPU3IST ", 
           0xDFEE8680, 
           0x0152, 
           "CPU2CST ", 
           Zero, 
           0xF000E816, 
           "CPU3CST ", 
           Zero, 
           0xF000E816

 

##EDIT## you can see in the above table my cst memory address is zero !! what adress value does your similar table show?

 

D.

[Matthew L.]

My P-states work just fine - always have

 

I have no native cst (c-state) SSDT tables with my MB and c-states is what I've never managed to get working - I'm just trying all possiblilites ATM.

 

Your DSDT doesn't contain a CPUpm table - it contains your PSS table and data and cst tables from a MacPro3,1 with modified bit width, bit offset and address values.

If you look this is the same as mine - as that's what I've just copied from MC.

 

D.

 

I've never got a _CST table from my motherboard too (only Cpu0Ist, Cpu1Ist and CpuPm), and it loads the CpuPm table from it's address by a code, which Master Chief suggested and writed, so if they are the same, why does mine work and yours doesn't? (No offense, just real curiousity.) And my P-states were working too, 'till the _CST errors were eliminated at boot: at this time, the multiplier stuck, so I had to append my p-states, even if it was working before without patching. AFAIK, my X48 board is more identical to the series 3 MoBos than the series 4 ones, and it's a Gigabyte, too.

 

I get working sleep, CST, and PST (voltage and multiplier autoswitching by AICPUPM kext), and normal temperatures (30/34C in idle) with this DSDT.

[Matthew L.]

Did you extract your SSDT tables in linux?

 

do you have a C-state option in BIOS - other than C1E ??

 

EDIT### this line here:

 

OperationRegion (STBL, SystemMemory, [color="#ff0000"]0xDFEE7F00, 0x022A[/color])

 

I presume you refaring to the part in red. This is taken from your specific SSDT table mine is taken from my table.

 

        Name (SSDT, Package (0x18)
       {
           "CPU0IST ", 
           [color="#ff0000"]0xDFEE7F00, 
           0x022A, [/color]
           "CPU1IST ", 
           0xDFEE83C0, 
           0x0152, 
           "CPU0CST ", 
           Zero, 
           0xF000E816, 
           "CPU1CST ", 
           Zero, 
           0xF000E816, 
           "CPU2IST ", 
           0xDFEE8520, 
           0x0152, 
           "CPU3IST ", 
           0xDFEE8680, 
           0x0152, 
           "CPU2CST ", 
           Zero, 
           0xF000E816, 
           "CPU3CST ", 
           Zero, 
           0xF000E816

D.

 

I've extracted my tables in Windows with Everest, and I don't have any other options than enabling or disabling C1E, and the address is not the IST table's address, but the whole CpuPm SSDT table's address (and length).

[FKA]

I've extracted my tables in Windows with Everest, and I don't have any other options than enabling or disabling C1E, and the address is not the IST table's address, but the whole CpuPm SSDT table's address (and length).

 

 

Very interesting - Ill give it a go (later toninght - @work ATM.). If it works I believe I'd owe you and MC a pint !

[kdawg]

Did you extract your SSDT tables in linux?

 

do you have a C-state option in BIOS - other than C1E ??

 

EDIT### this line here:

 

OperationRegion (STBL, SystemMemory, [color="#ff0000"]0xDFEE7F00, 0x022A[/color])

 

I presume you refaring to the part in red. This is taken from your specific SSDT table mine is taken from my table.

 

        Name (SSDT, Package (0x18)
       {
           "CPU0IST ", 
           [color="#ff0000"]0xDFEE7F00, 
           0x022A, [/color]
           "CPU1IST ", 
           0xDFEE83C0, 
           0x0152, 
           "CPU0CST ", 
           Zero, 
           0xF000E816, 
           "CPU1CST ", 
           Zero, 
           0xF000E816, 
           "CPU2IST ", 
           0xDFEE8520, 
           0x0152, 
           "CPU3IST ", 
           0xDFEE8680, 
           0x0152, 
           "CPU2CST ", 
           Zero, 
           0xF000E816, 
           "CPU3CST ", 
           Zero, 
           0xF000E816

 

##EDIT## you can see in the above table my cst memory address is zero !! what adress value does your similar table show?

 

D.

 

 

FKA, take a quick peek at this post. It offers an interesting cause of c-state problems with X58 Gigabyte boards but perhaps this is a board wide problem with all GB MOBOs.

[Matthew L.]

Very interesting - Ill give it a go (later toninght - @work ATM.). If it works I believe I'd owe you and MC a pint !

 

You don't owe me anything (if it works of course), everything goes to Master Chief, the source of all great ideas!

 

FKA, take a quick peek at this post. It offers an interesting cause of c-state problems with X58 Gigabyte boards but perhaps this is a board wide problem with all GB MOBOs.

 

FYI, C-states didn't work with my Asus P5N-D (nForce 750i) motherboard (nor with the current X48 GB board) with the same CPU if I didn't use the default voltage (in windows of course), and IMO this is the case with all the motherboards from the Core 2 era (or even more).

[FKA]

FKA, take a quick peek at this post. It offers an interesting cause of c-state problems with X58 Gigabyte boards but perhaps this is a board wide problem with all GB MOBOs.

 

Also very interesting kdawg -

 

Thanks both for the food for thought !