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OK, i thought its other way : Pstates number would limit the highest possible PStates first, not the lowest possible PStates first.

So, in my case, i must disable P0 (fastest,10*), the solution would be to use busratio=9 (which affects also PStates gen) to avoid P0 (=10*FSB) and i dont need Pstates key ?

this would be added in 5.0.4 which should appear very soon (awaiting feedbacks about archive3 to see if something should be changed for i-series)

Gents,

 

Got this... seems that ACPI is not working due CPU detection failure:

 

FADT: Restart Fix applied !
Invalid character found in ProcessorOP 0x5c!
Invalid character found in ProcessorOP 0x5c!
ACPI CPUs not found: C-States not generated !!!
Invalid character found in ProcessorOP 0x5c!
Invalid character found in ProcessorOP 0x5c!
ACPI CPUs not found: P-States not generated !!!
FADT: Restart Fix applied !
Invalid character found in ProcessorOP 0x5c!
Invalid character found in ProcessorOP 0x5c!
ACPI CPUs not found: C-States not generated !!!
Invalid character found in ProcessorOP 0x5c!
Invalid character found in ProcessorOP 0x5c!
ACPI CPUs not found: P-States not generated !!!

 

See attachment for full details.

bdmesg.zip

Im having this warning:

 

WARNING - ACPI_SMC_CtrlLoop::initCPUCtrlLoop - no sub-config match for MacBookPro4,1 with 10 p-states, using default stepper instead

 

And my CPU is running at 2.16 Ghz but in BIOS I set to 22x180Mhz = 3.80 Ghz

 

My config: ASUS P6T - Core i7 930

 

And this new version detect my GTX 460 correct, but without any aceleration and without possibility to change resolution, just show 1600x1200.

 

Thanks for the hard work, I will wait and test new versions.

 

ps.: sorry about the bad english

See attachment for full details.
I don't need the bdmesg command (I already have one). what if u provide me with the output of bdmesg?

seems to reflect errors related to dsdt

 

@vultu, I need more infos, like which version you used, which options, which values...

also a bdmesg dump would be very helpful

I don't need the bdmesg command (I already have one). what if u provide me with the output of bdmesg?

seems to reflect errors related to dsdt

 

@vultu, I need more infos, like which version you used, which options, which values...

also a bdmesg dump would be very helpful

MacOS 10.6.5

 

I dont set any option, I dont know how do that, I just use default.

 

Here my bdmesg dump:

LoadConfig: [hd(0,1)/Extra/com.apple.Boot.plist] 579 bytes.
CPU: Mobile Intel(R) Core(TM) i7 CPU		 930  @ 2.80GHz
CPU: Tjmax= ~ 99°C		   Temperature= ~ 51°C
CPU: Vendor/Family/ExtFamily: 0x756e6547/0x6/0x0
CPU: Model/ExtModel/Stepping: 0x1a/0x1/0x5
CPU: MaxCoef/CurrCoef:		0x0/0x15
CPU: MaxDiv/CurrDiv:		  0x0/0x0
CPU: Multiplier x10:		  120
CPU: TSCFreq:				 3780MHz
CPU: CPUFreq:				 2160MHz
CPU: FSBFreq:				 180MHz
CPU: Enhanced SpeedStep:	  1
CPU: NoCores/NoThreads:	   8/16
CPU: Features:				0x369802a3
Chipset is UNKNOWN (pci id 0x34058086)
We have an NVIDIA Card
Creating 2 Mode Tables
New table with id : 0
New table with id : 1
First Standard VESA Table at offset 0x4183
Second Standard VESA Table at offset 0x9514
Table #0 has 16 modes
Table #1 has 26 modes
Aspect Ratio is 16/10
Patching Table #0 : 
Mode 1024x768 -> 1024x768 (1047 1183 1343 770 776 805)
Patching Table #1 : 
Mode 640x200 -> 640x400 (664 672 720 408 H- V+)
Mode 640x350 -> 640x400 (664 678 720 408 H- V+)
Mode 640x480 -> 640x400 (669 685 720 408 H- V+)
Mode 640x480 -> 640x400 (669 685 720 408 H- V+)
Mode 800x600 -> 800x500 (836 852 900 512 H- V+)
Mode 800x600 -> 800x500 (836 852 900 512 H- V+)
Mode 1024x768 -> 1024x640 (1071 1087 1152 656 H- V+)
Mode 1024x768 -> 1024x640 (1071 1087 1152 656 H- V+)
Mode 1280x1024 -> 1280x800 (1343 1359 1440 823 H- V+)
Mode 1280x1024 -> 1280x800 (1343 1359 1440 823 H- V+)
Mode 1600x1200 -> 1600x1000 (1674 1690 1800 1025 H- V+)

Darwin/x86 boot v5.0.132 - Chameleon v5.0.1 r164
Build date: 2010-11-14 22:41:19
12278MB memory
VESA v3.0 14MB (NVIDIA)
Scanning device 80...Press any key to enter startup options.(3) (2) (1) (0) LoadConfig: [hd(0,2)/Library/Preferences/SystemConfiguration/com.apple.Boot.plist] 232 bytes.
Setting boot-uuid to: 6B5FA4B0-E716-35CC-AD56-A3600005BE75
Closing VBios
Table #0 : Freeing backup	[OK]
Table #0 : Freeing		[OK]
Table #1 : Freeing backup	[OK]
Table #1 : Freeing		[OK]
Freeing map			[OK]
LoadConfig: [hd(0,2)/System/Library/CoreServices/SystemVersion.plist] 479 bytes.
Loading Darwin 10.6
Loading kernel mach_kernel
LoadConfig: [hd(0,1)/Extra/Extensions/fakesmc.kext/Contents/Info.plist] 2334 bytes.
LoadDrivers: /System/Library/Caches/com.apple.kext.caches/Startup/Extensions.mkext
No DSDT found, using 0 as uid value.
Using PCI-Root-UID value: 0
nVidia GeForce GTX 460 768MB NVc4 [10de:0e22] :: PciRoot(0x0)/Pci(0x7,0x0)/Pci(0x0,0x0)
NVCAP: 04000000-00000300-1c000000-0000000a-00000000
@0,display-cfg: ffffffff
@1,display-cfg: ffffffff
No SMBIOS replacement found.
Intel NHM IMC DRAM Controller [8086:3405] at 00:00.0
Frequency detected: 720 MHz (1440) Triple Channel 
CAS:9 tRC:9 tRP:9 RAS:24 (9-9-9-24)
Slot: 0 Type 24 2048MB (DDR3 SDRAM) 1440MHz Vendor=Corsair
  PartNo=CM3X2G1600C9 SerialNo=00000000
Slot: 1 Type 24 2048MB (DDR3 SDRAM) 1440MHz Vendor=Corsair
  PartNo=CM3X2G1600C9 SerialNo=00000000
Slot: 2 Type 24 2048MB (DDR3 SDRAM) 1440MHz Vendor=Corsair
  PartNo=CM3X2G1600C9 SerialNo=00000000
Slot: 3 Type 24 2048MB (DDR3 SDRAM) 1440MHz Vendor=Corsair
  PartNo=CM3X2G1600C9 SerialNo=00000000
Slot: 4 Type 24 2048MB (DDR3 SDRAM) 1440MHz Vendor=Corsair
  PartNo=CM3X2G1600C9 SerialNo=00000000
Slot: 5 Type 24 2048MB (DDR3 SDRAM) 1440MHz Vendor=Corsair
  PartNo=CM3X2G1600C9 SerialNo=00000000
Patched DMI Table
Found SMBIOS System Information Table 1
Customizing SystemID with : e02a001e-8c00-01fa-c3d5-00261883e747
FADT: Restart Fix applied !
FADT: Restart Fix applied !
Patched ACPI version 2 DSDT
Starting Darwin x86_64

MacOS 10.6.5

 

I dont set any option, I dont know how do that, I just use default.

 

How do I generate a bdmesg dump?

 

Open terminal and type:

cd ~/Extra/Util or cd to /Extra/Util wherever you have it!

bdmesg

 

HALIntosh2010:~ Dave$ diskutil mount disk0s3
Volume Mac RAID Boot 1 on disk0s3 mounted
HALIntosh2010:~ Dave$ /Volumes/Mac\ RAID\ Boot\ 1/Extra/Util/bdmesg 
LoadConfig: [hd(0,3)/Extra/com.apple.Boot.plist] 1156 bytes.
CPU: Intel® Core™2 Quad  CPU   Q9450  @ 2.66GHz
max: 8 current: 6
CPU: Tjmax= ~ 100°C           Temperature= ~ 44°C
CPU: Vendor/Family/ExtFamily: 0x756e6547/0x6/0x0
CPU: Model/ExtModel/Stepping: 0x17/0x1/0x7
CPU: MaxCoef/CurrCoef:        0x8/0x6
CPU: MaxDiv/CurrDiv:          0x0/0x0
CPU: Multiplier x10:          80
CPU: TSCFreq:                 3199MHz
CPU: CPUFreq:                 3199MHz
CPU: FSBFreq:                 399MHz
CPU: Enhanced SpeedStep:      1
CPU: NoCores/NoThreads:       4/4
CPU: Features:                0x268802a1
Chipset is P45 (pci id 0x2e208086)
We have an AtomBios Card
Creating 1 Mode Tables
New table with id : 0
Standard VESA Table at offset * 0x94
Using DTD Format modelines
EDID claims 1 more blocks left
Aspect Ratio is 16/9
Patching Table #0 : 
Mode 320x200 -> 1920x1080
LoadConfig: [hd(0,3)/Extra/Themes/Daves/theme.plist] 2714 bytes.
EDID claims 1 more blocks left
Resolution : 1920x1080 (EDID)
LoadConfig: [hd(0,3)/Extra/Themes/Daves/theme.plist] 2714 bytes.
Found mode 1920x1080 in VESA Table
LoadConfig: [hd(0,3)/Extra/com.apple.Boot.plist] 1156 bytes.
EDID claims 1 more blocks left
Closing VBios
Table #0 : Freeing backup	[OK]
Table #0 : Freeing		[OK]
Freeing map			[OK]
LoadConfig: [hd(0,3)/System/Library/CoreServices/SystemVersion.plist] 479 bytes.
Loading Darwin 10.6
Loading kernel com.apple.boot.P/mach_kernel
LoadDrivers: /Extra/Extensions.mkext
LoadDrivers: /com.apple.boot.P/System/Library/Caches/com.apple.kext.caches/Startup/Extensions.mkext
LoadACPI: [hd(0,3)/Extra/DSDT.aml] 45310 bytes.
Using PCI-Root-UID value: 0
ATI VGA Controller [1002:68b8] :: PciRoot(0x0)/Pci(0x1,0x0)/Pci(0x0,0x0) 
old pci command - 7
boot display - 0
dumping pci config space, 256 bytes
Found bios image
Adding binimage to card 68b8 from mmio space with size f400
LoadConfig: [hd(0,3)/Extra/SMBIOS.plist] 684 bytes.
Intel P45/G45 DRAM Controller [8086:2e20] at 00:00.0
Frequency detected: 533 MHz (1066) Dual Channel 
CAS:7 tRC:7 tRP:7 RAS:24 (7-7-7-24)
Slot: 0 Type 19 2048MB (DDR2 SDRAM) 1066MHz Vendor=Crucial Technology
     PartNo=CT25664AA1067.M16FH SerialNo=00000000
Slot: 2 Type 19 2048MB (DDR2 SDRAM) 1066MHz Vendor=Crucial Technology
     PartNo=CT25664AA1067.M16FH SerialNo=00000000
Patched DMI Table
Found SMBIOS System Information Table 1
Customizing SystemID with : xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
LoadACPI: [hd(0,3)/Extra/DSDT.aml] 45310 bytes.
Converted ACPI V2 FADT to ACPI V4 FADT
FADT: Restart Fix applied !
Found ACPI CPU: P001
Found ACPI CPU: P002
Found ACPI CPU: P003
Found ACPI CPU: P004
C-State: Adding 3 states: C1 C2 C3 
Voltage: min= 987mV, max= 1112mV
P-State: Added [Frequency 3192 MHz, FID 0x8, VID 0x20]
P-State: Added [Frequency 2793 MHz, FID 0x7, VID 0x1d]
P-State: Added [Frequency 2394 MHz, FID 0x6, VID 0x18]
FADT: Restart Fix applied !
Patched ACPI version 2 DSDT
Starting Darwin x86_64

 

D

@FKA & Vultu, please try using the archive3 from the first post by just replacing the boot file

 

@eberts, use string instead; I know what u meant, but till now I could not get it to work with the same types as apple's;. Gonna give it one more accurate try later; and remember it's cosmetic

Hi all, do you have this phenomenon, before the Chameleon boot theme appears, there is a log show like :

ntfs_fixup:magic doesn't match xxxx

, I have search in the google without answer. I do know how this cause, even the unofficial version exist this problem, but when I use RC4 boot version ,it does not appears.

 

After test archive 3 : CStates and PState works great, the PState is five, now it is nine: CPU=Pentium dual core .

 

Here is the log: dmesg.rtf

 

Regards.

hello, i test archive 3 with my E7600 3,06 Ghz Auto Voltage and OC 3,84 Ghz with 1,296 V.

smcK-Stat Voltage min=1088 mV,max= 1264 mV at 3,06 Ghz with 008 mV steps.

bdmesg tells me Voltage: min= 987mV, max= 1175mV and the same when OC.

 

P-State: [Frequency 3830 MHz, FID 0x4b, VID 0x25] is over the limit. Removed!

 

could i change it in com.apple.Boot.plist ?

 

i used the latest FakeSMC from mozodojo.

3_06_Ghz_Auto.rtf

3_84_Ghz_OC.rtf

com.apple.Boot.plist.zip

dsdt.aml.zip

@valv,

 

I tested Archive3 on Asus A42JV with Intel Core i5-450M.

 

bdmesg without GenerateCStates & GeneratePStates:-

AnVAL.5.0.3.Archive3.txt

- PerformaceStateArray = 11

 

bdmesg with GenerateCStates & GeneratePStates:-

AnVAL.5.0.3.Archive3_G.txt

- PerformaceStateArray = 10

 

The processor frequency reported in System Profiler is correct which is 2.4GHz (normal operating frequency).

 

About the GenerateCStates & GeneratePStates, I don't think I need it on my Asus A42JV since I didn't have error message regarding CST in log files & already detected 11 P-States (multiplier 9x - 20x). Somehow the P-States reduced to 10 when I use GeneratePStates, so I don't need it too. Am I right?

 

UPDATE: With GeneratePStates, Turbo Boost doesn't work. The processor frequency won't go beyond normal operating frequency.

@valv,

 

I tested Archive3 on Dell Studio 1557 with Intel Core i7-720QM.

 

bdmesg without GenerateCStates & GeneratePStates:-

AnVAL.5.0.3_Archive3.txt

- PerformaceStateArray = 7

 

bdmesg with GenerateCStates & GeneratePStates:-

AnVAL.5.0.3_Archive3_G.txt

- PerformaceStateArray = 6

 

The processor frequency reported in System Profiler is correct which is 1.6GHz (normal operating frequency).

 

With GeneratePStates, Turbo Boost doesn't work. The processor frequency won't go beyond normal operating frequency.

I dont now, but perhaps its good for valv to know if Pstates are shown (i5/i7) also without pstate gen aktive in the IOREGISTRY EXPLORER.

You can find them , if generated by the OS X itself (and not DSDT / not autogen RC5) in the part the pic shows.

(I have C2D , so i5/i7 will have others - if they are "buildin" generated by OS X itself, without any hack)

If in this ipreg key are no Pstates listed, they were not generated by OS X itself in your case (i5/i7).

Bildschirmfoto_2010_11_19_um_09.34.25.jpg

I went to: http://forge.voodooprojects.org/p/chameleo.../autoResolution

and there's this "Change Log" link, but that points to: http://forge.voodooprojects.org/p/chameleo...e/changes/HEAD/

instead of the proper location. What should this be? Can this please be fixed?

 

Also. Do you plan to take care of Intel Core iX users on notebooks with the Intel HD Graphics, like the GMA5700, which doesn't work of course.

 

I also fail to understand why two people (mozodojo and you) are working on the same stuff (http://www.insanelymac.com/forum/index.php?showtopic=225766) and not simply work together. Must be me.

I don't need the bdmesg command (I already have one). what if u provide me with the output of bdmesg?

seems to reflect errors related to dsdt

 

@vultu, I need more infos, like which version you used, which options, which values...

also a bdmesg dump would be very helpful

 

What an NOOOOB i'm here you go the full output of bdmesg.

 

TIA !

 

Is there also any possibility to force GPU clocks / select performance profiles for a Nvidia Discrete videocard in a laptop? I have a real slow 2d performance. GPU clock is @183Mhz but it can @625. It never goes further then 325Mhz gpu clock.

 

Tried to make a custom bios with new clocks but it seems it loads at the bootloader (UseNvidiaRom etc) but the clocks aren't changed.

bdmesgoutput.rtf.zip

com.apple.Boot.plist.zip

@Carstiman, I found the mistake and fixed it; this behavior should disappear on 5.0.4. Also, regarding voltage, I think you need to inject the new values.

 

@Kizwan, Turbo boost would not work for u (more than 6 cores) sorry; Did u try to go with 6 cores or less. Voltage seems to be undetectable: u'd need to inject 'em.

I understand the fact that u don't need p-state auto-generation; but, maybe some eastern-eggs can convince u to do:

when relying on the auto-generator u get pss + psd + ppc + pct. What do u think?

also u can use EnableCxState (where x is the highest state wanted) to generate c-states, without even using the usual key for c-states auto-generation.

 

@mitch_de, I think this is the effect of a legacy kext. What is important though, is the fact that auto-gen takes precedence. I my self have one (just in case auto-gen fails for a reason or the other).

 

@dutchhokeypro, regarding the source code, my branch has my name valv. autoresolution is diebuche's. the latest changes are not yet on my branch (till I get satisfied with some parts of the code).

Yes, I hope core-iX users and everyone else would be satisfied at the end.

we are working together! but in the main time, every decision had to spell some individual efforts, till it becomes a plausible idea (to most of devs) and thus get its entrance into the trunk.

 

@hannibal1969, as I explained before: u have an error on your dsdt (maybe the guyz on the DSDT editor and patcher topic could help u fixing it)

 

edit: @kizwan, turbo ratio limit is a priority. would u mind testing this one: boot above is now useless

@Kizwan, Turbo boost would not work for u (more than 6 cores) sorry; Did u try to go with 6 cores or less.

When Turbo Boost is activated, based on this calculation, the number of cores in use will be reduced. Anyway, no problem. I usually didn't use GeneratePStates & GenerateCStates since I think P-States & C-States are properly detected on both notebooks (checked in IOReg). Turbo Boost also works on both notebooks without the two keys/flags. On Asus notebook, geekbench score is higher in OSX than in Windows. I just thought maybe you want to see the bdmesg when using the two keys/flags on i-series CPU. :)

Voltage seems to be undetectable: u'd need to inject 'em.

I thought I only need to inject 'em if I want to over/under-voltage the CPU. MSR Tools seems to be able to read the voltage on both notebooks.

I understand the fact that u don't need p-state auto-generation; but, maybe some eastern-eggs can convince u to do:

when relying on the auto-generator u get pss + psd + ppc + pct. What do u think?

Can I check pss + psd + ppc + pct in IOReg? However, if I use GeneratePStates on either notebooks, I will loose TurboBoost.

 

edit: @kizwan, turbo ratio limit is a priority. would u mind testing this one:

OK. I'll try this & post here the bdmesg.

I thought I only need to inject 'em if I want to over/under-voltage the CPU. MSR Tools seems to be able to read the voltage on both notebooks.
not the case of core-iX users (yet).
Can I check pss + psd + ppc + pct in IOReg?
dump your ssdts (with DSDTSE for example)
dump your ssdts (with DSDTSE for example)

Yes, I found pss + psd + ppc + pct in the SSDTs on both notebooks.

Asus A42JV:-

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20100528
*
* Disassembly of acpi_ssdt-3.bin, Fri Oct 22 19:35:15 2010
*
*
* Original Table Header:
*     Signature        "SSDT"
*     Length           0x00000303 (771)
*     Revision         0x01
*     Checksum         0x76
*     OEM ID           "PmRef"
*     OEM Table ID     "ApIst"
*     OEM Revision     0x00003000 (12288)
*     Compiler ID      "INTL"
*     Compiler Version 0x20051117 (537202967)
*/
DefinitionBlock ("acpi_ssdt-3.aml", "SSDT", 1, "PmRef", "ApIst", 0x00003000)
{
   External (\_PR_.CPU7, DeviceObj)
   External (\_PR_.CPU6, DeviceObj)
   External (\_PR_.CPU5, DeviceObj)
   External (\_PR_.CPU4, DeviceObj)
   External (\_PR_.CPU3, DeviceObj)
   External (\_PR_.CPU2, DeviceObj)
   External (\_PR_.CPU1, DeviceObj)
   External (\_PR_.CPU0._PSD, IntObj)
   External (\_PR_.CPU0._PSS, IntObj)
   External (\_PR_.CPU0._PCT, IntObj)
   External (\_PR_.CPU0._PPC, IntObj)

   Scope (\_PR.CPU1)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU2)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU3)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU4)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU5)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU6)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU7)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }
}

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20100528
*
* Disassembly of acpi_ssdt-4.bin, Fri Oct 22 19:35:15 2010
*
*
* Original Table Header:
*     Signature        "SSDT"
*     Length           0x000003F7 (1015)
*     Revision         0x01
*     Checksum         0x94
*     OEM ID           "PmRef"
*     OEM Table ID     "Cpu0Ist"
*     OEM Revision     0x00003000 (12288)
*     Compiler ID      "INTL"
*     Compiler Version 0x20051117 (537202967)
*/
DefinitionBlock ("acpi_ssdt-4.aml", "SSDT", 1, "PmRef", "Cpu0Ist", 0x00003000)
{
   External (NPSS, IntObj)
   External (PDC0)
   External (CFGD)
   External (\LIMT, IntObj)
   External (\_PR_.CPU0, DeviceObj)

   Scope (\_PR.CPU0)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\LIMT)
       }

       Method (_PCT, 0, NotSerialized)
       {
           If (LAnd (And (CFGD, One), And (PDC0, One)))
           {
               Return (Package (0x02)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x00,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x00,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }
               })
           }

           Return (Package (0x02)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x10,               // Bit Width
                       0x00,               // Bit Offset
                       0x000000000000FF00, // Address
                       ,)
               }, 

               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x00000000000000B3, // Address
                       ,)
               }
           })
       }

       Method (XPSS, 0, NotSerialized)
       {
           If (And (PDC0, One))
           {
               Return (NPSS)
           }

           Return (SPSS)
       }

       Name (SPSS, Package (0x0B)
       {
           Package (0x06)
           {
               0x00000960, 
               0x000061A8, 
               0x0000006E, 
               0x0000000A, 
               0x00000083, 
               0x00000000
           }, 

           Package (0x06)
           {
               0x0000095F, 
               0x000061A8, 
               0x0000006E, 
               0x0000000A, 
               0x00000183, 
               0x00000001
           }, 

           Package (0x06)
           {
               0x000008DA, 
               0x00005B14, 
               0x0000006E, 
               0x0000000A, 
               0x00000283, 
               0x00000002
           }, 

           Package (0x06)
           {
               0x00000855, 
               0x000054B9, 
               0x0000006E, 
               0x0000000A, 
               0x00000383, 
               0x00000003
           }, 

           Package (0x06)
           {
               0x000007CF, 
               0x00004E94, 
               0x0000006E, 
               0x0000000A, 
               0x00000483, 
               0x00000004
           }, 

           Package (0x06)
           {
               0x0000074A, 
               0x00004863, 
               0x0000006E, 
               0x0000000A, 
               0x00000583, 
               0x00000005
           }, 

           Package (0x06)
           {
               0x000006C5, 
               0x0000427D, 
               0x0000006E, 
               0x0000000A, 
               0x00000683, 
               0x00000006
           }, 

           Package (0x06)
           {
               0x0000063F, 
               0x00003C9D, 
               0x0000006E, 
               0x0000000A, 
               0x00000783, 
               0x00000007
           }, 

           Package (0x06)
           {
               0x000005BA, 
               0x000036F4, 
               0x0000006E, 
               0x0000000A, 
               0x00000883, 
               0x00000008
           }, 

           Package (0x06)
           {
               0x00000535, 
               0x00003160, 
               0x0000006E, 
               0x0000000A, 
               0x00000983, 
               0x00000009
           }, 

           Package (0x06)
           {
               0x000004AF, 
               0x00002BF2, 
               0x0000006E, 
               0x0000000A, 
               0x00000A83, 
               0x0000000A
           }
       })
       Name (_PSS, Package (0x0B)
       {
           Package (0x06)
           {
               0x00000960, 
               0x000061A8, 
               0x0000000A, 
               0x0000000A, 
               0x00000013, 
               0x00000013
           }, 

           Package (0x06)
           {
               0x0000095F, 
               0x000061A8, 
               0x0000000A, 
               0x0000000A, 
               0x00000012, 
               0x00000012
           }, 

           Package (0x06)
           {
               0x000008DA, 
               0x00005B14, 
               0x0000000A, 
               0x0000000A, 
               0x00000011, 
               0x00000011
           }, 

           Package (0x06)
           {
               0x00000855, 
               0x000054B9, 
               0x0000000A, 
               0x0000000A, 
               0x00000010, 
               0x00000010
           }, 

           Package (0x06)
           {
               0x000007CF, 
               0x00004E94, 
               0x0000000A, 
               0x0000000A, 
               0x0000000F, 
               0x0000000F
           }, 

           Package (0x06)
           {
               0x0000074A, 
               0x00004863, 
               0x0000000A, 
               0x0000000A, 
               0x0000000E, 
               0x0000000E
           }, 

           Package (0x06)
           {
               0x000006C5, 
               0x0000427D, 
               0x0000000A, 
               0x0000000A, 
               0x0000000D, 
               0x0000000D
           }, 

           Package (0x06)
           {
               0x0000063F, 
               0x00003C9D, 
               0x0000000A, 
               0x0000000A, 
               0x0000000C, 
               0x0000000C
           }, 

           Package (0x06)
           {
               0x000005BA, 
               0x000036F4, 
               0x0000000A, 
               0x0000000A, 
               0x0000000B, 
               0x0000000B
           }, 

           Package (0x06)
           {
               0x00000535, 
               0x00003160, 
               0x0000000A, 
               0x0000000A, 
               0x0000000A, 
               0x0000000A
           }, 

           Package (0x06)
           {
               0x000004AF, 
               0x00002BF2, 
               0x0000000A, 
               0x0000000A, 
               0x00000009, 
               0x00000009
           }
       })
       Method (_PSD, 0, NotSerialized)
       {
           If (And (PDC0, 0x0800))
           {
               Return (HPSD)
           }

           Return (SPSD)
       }

       Name (HPSD, Package (0x01)
       {
           Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFE, 
               0x04
           }
       })
       Name (SPSD, Package (0x01)
       {
           Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           }
       })
   }
}

 

Dell Studio 1557:-

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20100528
*
* Disassembly of acpi_ssdt-2.bin, Fri Oct 22 18:02:02 2010
*
*
* Original Table Header:
*     Signature        "SSDT"
*     Length           0x00000303 (771)
*     Revision         0x01
*     Checksum         0x82
*     OEM ID           "PmRef"
*     OEM Table ID     "ApIst"
*     OEM Revision     0x00003000 (12288)
*     Compiler ID      "INTL"
*     Compiler Version 0x20060912 (537266450)
*/
DefinitionBlock ("acpi_ssdt-2.aml", "SSDT", 1, "PmRef", "ApIst", 0x00003000)
{
   External (\_PR_.CPU7, DeviceObj)
   External (\_PR_.CPU6, DeviceObj)
   External (\_PR_.CPU5, DeviceObj)
   External (\_PR_.CPU4, DeviceObj)
   External (\_PR_.CPU3, DeviceObj)
   External (\_PR_.CPU2, DeviceObj)
   External (\_PR_.CPU1, DeviceObj)
   External (\_PR_.CPU0._PSD, IntObj)
   External (\_PR_.CPU0._PSS, IntObj)
   External (\_PR_.CPU0._PCT, IntObj)
   External (\_PR_.CPU0._PPC, IntObj)

   Scope (\_PR.CPU1)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU2)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU3)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU4)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU5)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU6)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }

   Scope (\_PR.CPU7)
   {
       Method (_PPC, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PPC)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PCT)
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSS)
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (\_PR.CPU0._PSD)
       }
   }
}

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20100528
*
* Disassembly of acpi_ssdt-3.bin, Fri Oct 22 18:02:02 2010
*
*
* Original Table Header:
*     Signature        "SSDT"
*     Length           0x000002E8 (744)
*     Revision         0x01
*     Checksum         0xAA
*     OEM ID           "PmRef"
*     OEM Table ID     "Cpu0Ist"
*     OEM Revision     0x00003000 (12288)
*     Compiler ID      "INTL"
*     Compiler Version 0x20060912 (537266450)
*/
DefinitionBlock ("acpi_ssdt-3.aml", "SSDT", 1, "PmRef", "Cpu0Ist", 0x00003000)
{
   External (NPSS, IntObj)
   External (PDC0)
   External (CFGD)
   External (\_PR_.CPU0, DeviceObj)

   Scope (\_PR.CPU0)
   {
       Name (_PPC, Zero)
       Method (_PCT, 0, NotSerialized)
       {
           If (LAnd (And (CFGD, One), And (PDC0, One)))
           {
               Return (Package (0x02)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x00,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x00,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }
               })
           }

           Return (Package (0x02)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x10,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000500, // Address
                       ,)
               }, 

               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x00000000000000B3, // Address
                       ,)
               }
           })
       }

       Method (XPSS, 0, NotSerialized)
       {
           If (And (PDC0, One))
           {
               Return (NPSS)
           }

           Return (SPSS)
       }

       Name (SPSS, Package (0x07)
       {
           Package (0x06)
           {
               0x00000640, 
               0x0000AFC8, 
               0x0000006E, 
               0x0000000A, 
               0x00000083, 
               0x00000000
           }, 

           Package (0x06)
           {
               0x0000063F, 
               0x0000AFC8, 
               0x0000006E, 
               0x0000000A, 
               0x00000183, 
               0x00000001
           }, 

           Package (0x06)
           {
               0x000005BA, 
               0x0000A20D, 
               0x0000006E, 
               0x0000000A, 
               0x00000283, 
               0x00000002
           }, 

           Package (0x06)
           {
               0x00000535, 
               0x000094E0, 
               0x0000006E, 
               0x0000000A, 
               0x00000383, 
               0x00000003
           }, 

           Package (0x06)
           {
               0x000004AF, 
               0x000087F6, 
               0x0000006E, 
               0x0000000A, 
               0x00000483, 
               0x00000004
           }, 

           Package (0x06)
           {
               0x0000042A, 
               0x00007B14, 
               0x0000006E, 
               0x0000000A, 
               0x00000583, 
               0x00000005
           }, 

           Package (0x06)
           {
               0x000003A5, 
               0x00006EB5, 
               0x0000006E, 
               0x0000000A, 
               0x00000683, 
               0x00000006
           }
       })
       Name (_PSS, Package (0x07)
       {
           Package (0x06)
           {
               0x00000640, 
               0x0000AFC8, 
               0x0000000A, 
               0x0000000A, 
               0x0000000D, 
               0x0000000D
           }, 

           Package (0x06)
           {
               0x0000063F, 
               0x0000AFC8, 
               0x0000000A, 
               0x0000000A, 
               0x0000000C, 
               0x0000000C
           }, 

           Package (0x06)
           {
               0x000005BA, 
               0x0000A20D, 
               0x0000000A, 
               0x0000000A, 
               0x0000000B, 
               0x0000000B
           }, 

           Package (0x06)
           {
               0x00000535, 
               0x000094E0, 
               0x0000000A, 
               0x0000000A, 
               0x0000000A, 
               0x0000000A
           }, 

           Package (0x06)
           {
               0x000004AF, 
               0x000087F6, 
               0x0000000A, 
               0x0000000A, 
               0x00000009, 
               0x00000009
           }, 

           Package (0x06)
           {
               0x0000042A, 
               0x00007B14, 
               0x0000000A, 
               0x0000000A, 
               0x00000008, 
               0x00000008
           }, 

           Package (0x06)
           {
               0x000003A5, 
               0x00006EB5, 
               0x0000000A, 
               0x0000000A, 
               0x00000007, 
               0x00000007
           }
       })
       Method (_PSD, 0, NotSerialized)
       {
           If (And (PDC0, 0x0800))
           {
               Return (HPSD)
           }

           Return (SPSD)
       }

       Name (HPSD, Package (0x01)
       {
           Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFE, 
               0x08
           }
       })
       Name (SPSD, Package (0x01)
       {
           Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x08
           }
       })
   }
}

I will test the latest boot file in a couple of hours.

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