1445 replies to this topic

[swtos]

Wake from sleep is instant without any KP. Geekbench is free version. I always follow Gigabyte procedures when flashing bios. Overclocking made step by step (5-10 mins from one step to another).

[voll@]

Thanks dood for fast councils on DSDT all work

[dungeon]

i have to unplug and replug in my usb bluetooth dongle to get it work again after wake from sleep. I get KP lately when i do it. Does anybody have the same experience or know a workaround?

[d00d]

Update 3: Using DVID and the modified MacPro4_1.plist prevents waking from S3 if using a device-properties video string in com.apple.Boot.plist.
Using DVID and the modified MacPro4_1.plist with GraphicsEnabler=yes (and PciRoot=1 for C2RC4, which has a default of 0) in com.apple.Boot.plist doesn't prevent waking from S3.

[FUT1L1TY]

5. For CPU0 through CPU7, make the following change to pass the CStates to OS X.
This is only needed when clocked over a certain point (148x20 or 2.96 GHz for a i7 920 or Xeon W3520 CPU), as it seems that the Gigabyte BIOS doesn't make the CStates available to the OS above that, even with all energy saving options enabled in the BIOS's Advanced CPU Features section.
If you convert the hexadecimal you will find that the PStates represent the default clock of your CPU, but it won't down clock your CPU if over clocked, and is what the BIOS makes available to the OS at default or over clock.

d00d,

Amazing guide! Thank you. I'm however stuck on step 5. I have a Core i7 920 C0 stepping so in order not to fry it I tried the following:

1) In BIOS, set my clock to 2.66 (133 x 20)
2) In BIOS, Enabled C1E and C3/C6/C7
3) Removed DSDT.aml from /Extra
4) Rebooted
5) Ran DSDTSE 1.43 and extracted SSDT (attached below)

My CStates appear to be the same as yours but I don't have 10 PStates. In fact I don't have any. Instead I have 8 TStates. Would you be kind enough to tell me what I'm doing wrong? This is all new territory for me. Any and all help appreciated. Thank you.

Attached Files

•  Core_i7_920_C0_Stepping_SSDT.txt   87.74KB   22 downloads

[d00d]

d00d,

Amazing guide! Thank you. I'm however stuck on step 5. I have a Core i7 920 C0 stepping so in order not to fry it I tried the following:

1) In BIOS, set my clock to 2.66 (133 x 20)
2) In BIOS, Enabled C1E and C3/C6/C7
3) Removed DSDT.aml from /Extra
4) Rebooted
5) Ran DSDTSE 1.43 and extracted SSDT (attached below)

My CStates appear to be the same as yours but I don't have 10 PStates. In fact I don't have any. Instead I have 8 TStates. Would you be kind enough to tell me what I'm doing wrong? This is all new territory for me. Any and all help appreciated. Thank you.

Thanks.
EIST also needs to be enabled to see the ten PStates.

[FUT1L1TY]

Thanks.
EIST also needs to be enabled to see the ten PStates.

Thank you for the quick reply. That was exactly the problem. FYI, my PStates were identical to yours except they were formatted like this:

Package (0x06)                    {                        0x00000A65,                         0x0001FBD0,                         0x0000000A,                         0x0000000A,                         0x00000015,                         0x00000015                    },                     Package (0x06)                    {                        0x00000A64,                         0x0001FBD0,                         0x0000000A,                         0x0000000A,                         0x00000014,                         0x00000014                    },                     Package (0x06)                    {                        0x000009DF,                         0x0001A9C8,                         0x0000000A,                         0x0000000A,                         0x00000013,                         0x00000013                    },                     Package (0x06)                    {                        0x0000095A,                         0x000186A0,                         0x0000000A,                         0x0000000A,                         0x00000012,                         0x00000012                    },                     Package (0x06)                    {                        0x000008D5,                         0x00014438,                         0x0000000A,                         0x0000000A,                         0x00000011,                         0x00000011                    },                     Package (0x06)                    {                        0x00000850,                         0x000128E0,                         0x0000000A,                         0x0000000A,                         0x00000010,                         0x00000010                    },                     Package (0x06)                    {                        0x000007CB,                         0x0000F618,                         0x0000000A,                         0x0000000A,                         0x0000000F,                         0x0000000F                    },                     Package (0x06)                    {                        0x00000746,                         0x0000DEA8,                         0x0000000A,                         0x0000000A,                         0x0000000E,                         0x0000000E                    },                     Package (0x06)                    {                        0x000006C1,                         0x0000B798,                         0x0000000A,                         0x0000000A,                         0x0000000D,                         0x0000000D                    },                     Package (0x06)                    {                        0x0000063C,                         0x0000A7F8,                         0x0000000A,                         0x0000000A,                         0x0000000C,                         0x0000000C                    }

It's probably not important but I used mine instead just to be safe. My idle temp is about 10C lower now. I've updated my sig to reflect my current settings. Please keep up the great work.

[dungeon]

Thank you for the quick reply. That was exactly the problem. FYI, my PStates were identical to yours except they were formatted like this:

Package (0x06)                    {                        0x00000A65,                         0x0001FBD0,                         0x0000000A,                         0x0000000A,                         0x00000015,                         0x00000015                    },                     Package (0x06)                    {                        0x00000A64,                         0x0001FBD0,                         0x0000000A,                         0x0000000A,                         0x00000014,                         0x00000014                    },                     Package (0x06)                    {                        0x000009DF,                         0x0001A9C8,                         0x0000000A,                         0x0000000A,                         0x00000013,                         0x00000013                    },                     Package (0x06)                    {                        0x0000095A,                         0x000186A0,                         0x0000000A,                         0x0000000A,                         0x00000012,                         0x00000012                    },                     Package (0x06)                    {                        0x000008D5,                         0x00014438,                         0x0000000A,                         0x0000000A,                         0x00000011,                         0x00000011                    },                     Package (0x06)                    {                        0x00000850,                         0x000128E0,                         0x0000000A,                         0x0000000A,                         0x00000010,                         0x00000010                    },                     Package (0x06)                    {                        0x000007CB,                         0x0000F618,                         0x0000000A,                         0x0000000A,                         0x0000000F,                         0x0000000F                    },                     Package (0x06)                    {                        0x00000746,                         0x0000DEA8,                         0x0000000A,                         0x0000000A,                         0x0000000E,                         0x0000000E                    },                     Package (0x06)                    {                        0x000006C1,                         0x0000B798,                         0x0000000A,                         0x0000000A,                         0x0000000D,                         0x0000000D                    },                     Package (0x06)                    {                        0x0000063C,                         0x0000A7F8,                         0x0000000A,                         0x0000000A,                         0x0000000C,                         0x0000000C                    }

It's probably not important but I used mine instead just to be safe. My idle temp is about 10C lower now. I've updated my sig to reflect my current settings. Please keep up the great work.

what's your idle temp now?

[d00d]

Thank you for the quick reply. That was exactly the problem. FYI, my PStates were identical to yours except they were formatted like this:

Package (0x06)                    {                        0x00000A65,                         0x0001FBD0,                         0x0000000A,                         0x0000000A,                         0x00000015,                         0x00000015                    },                     Package (0x06)                    {                        0x00000A64,                         0x0001FBD0,                         0x0000000A,                         0x0000000A,                         0x00000014,                         0x00000014                    },                     Package (0x06)                    {                        0x000009DF,                         0x0001A9C8,                         0x0000000A,                         0x0000000A,                         0x00000013,                         0x00000013                    },                     Package (0x06)                    {                        0x0000095A,                         0x000186A0,                         0x0000000A,                         0x0000000A,                         0x00000012,                         0x00000012                    },                     Package (0x06)                    {                        0x000008D5,                         0x00014438,                         0x0000000A,                         0x0000000A,                         0x00000011,                         0x00000011                    },                     Package (0x06)                    {                        0x00000850,                         0x000128E0,                         0x0000000A,                         0x0000000A,                         0x00000010,                         0x00000010                    },                     Package (0x06)                    {                        0x000007CB,                         0x0000F618,                         0x0000000A,                         0x0000000A,                         0x0000000F,                         0x0000000F                    },                     Package (0x06)                    {                        0x00000746,                         0x0000DEA8,                         0x0000000A,                         0x0000000A,                         0x0000000E,                         0x0000000E                    },                     Package (0x06)                    {                        0x000006C1,                         0x0000B798,                         0x0000000A,                         0x0000000A,                         0x0000000D,                         0x0000000D                    },                     Package (0x06)                    {                        0x0000063C,                         0x0000A7F8,                         0x0000000A,                         0x0000000A,                         0x0000000C,                         0x0000000C                    }

It's probably not important but I used mine instead just to be safe. My idle temp is about 10C lower now. I've updated my sig to reflect my current settings. Please keep up the great work.

Thanks.
The PState values in my instructions for editing DSDT.dsl are what the compiler changes them to in DSDT.aml.
So if you use a line like `0x00000A65,' in DSDT.dsl for example, it changes to `0x0A65,' when compiled into DSDT.aml.
Hexadecimal 0x00000A65 is the same as hexadecimal 0x0A65 (decimal 2661);
0x0A65, // 2661 MHz core frequency
0x0001FBD0, // 130000 mW power
0x0A, // 10 us transition latency
0x0A, // 10 us transition latency
0x15, // 21 multiplier
0x15 // 21 multiplier

[LocusOfControl]

LocusOfControl,

I am just happy now my idle sleep is working properly even though the timing is not accurate to the setting in Energy Saver. I did a test last night by using Handbrake to rip a movie from DVD. I set up my computer to go to sleep after 15 minutes. I was happy to find that my computer was asleep this morning and the movie did finish. It means now that I can have activities running and not worrying about the Autosleep script from kicking in. Thanks for your help.

@ttgolf

How is your sleep working? I got idle sleep to work originally after about 1.5 - 2.0 hrs, a bit of fiddling later I had it
sleeping at about 40 min but it sometimes breaks this rule

With wake from BT off, idle sleep still working perfectly

[FUT1L1TY]

what's your idle temp now?

I idle at 37C. I'm only overclocked to 3.33ghz (specs below). My machine is quieter now too. My 3 case fans (Arctic Cooling) are linked to my CPU fan via PWM sharing. I ran MPrime and topped out at 70C.

[sr2]

There's a solution to make resume after sleep to work properly without requiring user to tick the "Start up automatically after a power failure" checkbox.

Guys at the DSDT fixes for Gigabyte boards thread narrowed down the problem to the GEN_PMCON_3 register (spec page 454, see description for bit 0).

First you need to define operation region in the Device (PX40):

OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
				Field (LPC0, ByteAcc, NoLock, Preserve)
				{
					AG3E,   1
				}

For example:

Device (PX40)
			{
				Name (_ADR, 0x001F0000)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", 
							Buffer (0x04)
							{
								0x18, 0x3A, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}

				OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
				Field (LPC0, ByteAcc, NoLock, Preserve)
				{
					AG3E,   1
				}

				/* snip */

And change the Method (_PTS) to look like this:

Method (_PTS, 1, NotSerialized)
	{
		Or (Arg0, 0xF0, Local0)
		Store (Local0, DBG1)
		OSTP()

		If (LEqual (Arg0, 0x05))
		{
			Store (0x99, SMIP)
			Store (One, \_SB.PCI0.PX40.AG3E)
			Store (Zero, SLPE)
			Sleep (0x10)
		}
		Else
		{
			Store (Zero, \_SB.PCI0.PX40.AG3E)
		}
	}

After the above changes sleep should work even if the "Start up automatically after a power failure" checkbox is unchecked.

EDIT:
I'll attach my dsdt just in case if I {censored}ed up something when porting the _PTS method to the dsdt in the first post.
 dsdt.zip   8.26KB   74 downloads

[d00d]

There's a solution to make resume after sleep to work properly without requiring user to tick the "Start up automatically after a power failure" checkbox.

Guys at the DSDT fixes for Gigabyte boards thread narrowed down the problem to the GEN_PMCON_3 register (spec page 454, see description for bit 0).

Thanks, I have that topic open in one of my Firefox tabs, but missed this particular modification.
I'll try it out and include it in the instructions in post 1.

[LocusOfControl]

There's a solution to make resume after sleep to work properly without requiring user to tick the "Start up automatically after a power failure" checkbox.

Guys at the DSDT fixes for Gigabyte boards thread narrowed down the problem to the GEN_PMCON_3 register (spec page 454, see description for bit 0).

First you need to define operation region in the Device (PX40):

OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
				Field (LPC0, ByteAcc, NoLock, Preserve)
				{
					AG3E,   1
				}

For example:

Device (PX40)
			{
				Name (_ADR, 0x001F0000)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"device-id", 
							Buffer (0x04)
							{
								0x18, 0x3A, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}

				OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
				Field (LPC0, ByteAcc, NoLock, Preserve)
				{
					AG3E,   1
				}

				/* snip */

And change the Method (_PTS) to look like this:

Method (_PTS, 1, NotSerialized)
	{
		Or (Arg0, 0xF0, Local0)
		Store (Local0, DBG1)
		OSTP()

		If (LEqual (Arg0, 0x05))
		{
			Store (0x99, SMIP)
			Store (One, \_SB.PCI0.PX40.AG3E)
			Store (Zero, SLPE)
			Sleep (0x10)
		}
		Else
		{
			Store (Zero, \_SB.PCI0.PX40.AG3E)
		}
	}

After the above changes sleep should work even if the "Start up automatically after a power failure" checkbox is unchecked.

EDIT:
I'll attach my dsdt just in case if I {censored}ed up something when porting the _PTS method to the dsdt in the first post.
 dsdt.zip   8.26KB   74 downloads

Is this a generic feature? just looking at one of your earlier posts it looked like you had a non gigabyte board

[sr2]

Is this a generic feature? just looking at one of your earlier posts it looked like you had a non gigabyte board

Well, according to the specification it should work on all ICH9 and ICH10 boards (earlier versions may support it too). I don't know if all manufacturers of ICH[9,10] motherboards comply to spec, but those who do should have this feature consistently working across all their boards.

And yes I've had the MSI P35 Platinum board, but just recently I got myself the Gigabyte GA-EX58-UD5.

A few details about the DSDT I posted earlier:

• It has all OS detection stuff stripped out
• It includes almost all modifications from the first post. I haven't changed the _PR scope because my board is not overclocked. You need to enable CStates in the Advanced Processor Features (not sure if I named it right) for AppleIntelCPUPowerManagement to work.
• No IDE.
• No PIC, only APIC.
• No PS/2.

[LocusOfControl]

Well, according to the specification it should work on all ICH9 and ICH10 boards (earlier versions may support it too). I don't know if all manufacturers of ICH[9,10] motherboards comply to spec, but those who do should have this feature consistently working across all their boards.

And yes I've had the MSI P35 Platinum board, but just recently I got myself the Gigabyte GA-EX58-UD5.

A few details about the DSDT I posted earlier:

• It has all OS detection stuff stripped out
• It includes almost all modifications from the first post. I haven't changed the _PR scope because my board is not overclocked. You need to enable CStates in the Advanced Processor Features (not sure if I named it right) for AppleIntelCPUPowerManagement to work.
• No IDE.
• No PIC, only APIC.
• No PS/2.

A very timely response, I was just pm'ing mm67 on the DSDT fixes for Gigabyte boards about PICM/PICF and APIC

I've also removed IDE etc but wrt to APIC how do you specify this, I thought unless you specify anything you got
PIC by default?

Did you manage to remove all the LNKx and BUFA stuff which depends on PIC?

Also, d00d, your bios settings, I'm confused as to why C3/C6/C7 state support etc needs to be disabled?
It sounds counter-intuitive

Advanced CPU Features:
CPU Clock Ratio ................................ [20x]
Intel® Turbo Boost Tech .................. [Enabled] disabled
CPU Cores Enabled ............................ [All] all
CPU Multi Threading .......................... [Enabled] enabled
CPU Enhanced Halt (C1E) ................... [Disabled] disabled
C3/C6/C7 State Support .................... [Disabled] disabled
CPU Thermal Monitor ......................... [Enabled] enabled
CPU EIST Function ............................ [Disabled] disabled
Bi-Directional PROCHOT ..................... [Enabled] disabled
Virtualization Technology ................... [Enabled] enabled

[d00d]

Also, d00d, your bios settings, I'm confused as to why C3/C6/C7 state support etc needs to be disabled?
It sounds counter-intuitive

I'll update my 4.3 GHz BIOS template, I'm running with everything in Advanced CPU Features enabled except for turbo.

[LocusOfControl]

I'll update my 4.3 GHz BIOS template, I'm running with everything in Advanced CPU Features enabled except for turbo.

!

Edit: d00d, Just a quick question

My assumption is that the difference between your DSDT method and the generic method on the other GB thread is
that yours is a bespoke method for the i7 to get better temperatures whereas the other thread is the 'off the peg,
one size fits all' version with wider coverage for more cpu's but not as good temp control. Is this correct?

[sr2]

A very timely response, I was just pm'ing mm67 on the DSDT fixes for Gigabyte boards about PICM/PICF and APIC

I've also removed IDE etc but wrt to APIC how do you specify this, I thought unless you specify anything you got
PIC by default?

It's the OS that dictates which interrupt controller to use. I don't think that Apple even supports PIC because it's impossible (?) to use on the SMP systems.

[d00d]

!

Edit: d00d, Just a quick question

My assumption is that the difference between your DSDT method and the generic method on the other GB thread is
that yours is a bespoke method for the i7 to get better temperatures whereas the other thread is the 'off the peg,
one size fits all' version with wider coverage for more cpu's but not as good temp control. Is this correct?

I haven't experimented much with making it generic because it seems that Nehalem depends on specific PStates, although I'm open to the concept if it can be made to work without error.
The following is seen if using turbo, and the 21 multiplier in DSDT is different from what is seen in the SSDT dump;
kernel[0]: WARNING: ACPI_SMC_CtrlLoop::initCPUCtrlLoop - turbo enabled but no turbo P-state found