SA22C, on Sep 8 2009, 02:23 AM, said:
I nabbed the OP's tables and changed the p-states to match my CPU. I don't get the C-state error anymore on boot and my Hack now sleeps and shuts down normally. However, I see no evidence that the CPU is actually stepping. The frequency seems pegged at the max. I am unable to boot into 32-bit (I have no idea why, but I the GUI refuses to load in x32) so I can't use CPUi to test, but a sysctl -a | grep freq returns a current, min and max freq as the same value, leading me to believe that no stepping is taking place.
I was also curious about the difference between the NPSS and SPSS states. What do I need to do differently between those two?
Thanks.
System is as follows:
Asus P5K-E
Intel Core 2 Duo E6400
Bios version 1305
My system supplies no SSDT tables of any kind, so I hacked in the provided SSDT dump in the OP.
Hi SA22C
I presume you've tried extracting SSDT in Linux? Some SSDT seem to be blocked when extracted in OS X.
Also p-states can also be added under the scope (_PR) part of DSDT rather than appending SSDT (if you can't find any SSDT then this is probably more suitable than using borrowed SSDT.)
See this example curt' mitch_de
Scope (_PR)
{
Processor (CPU0, 0x00, 0x00000410, 0x06)
{
Name (_PPC, 0x00)
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x04) // 4 Pstates 6-9 fsb muilt * 333 FSB, E7300-2660 GHZ-266*10
{
/* multi 10 OFF Package (0x06) { 3330, 93816, 10, 10, 0xA25, 0xA25 } */
Package (0x06) { 2997, 80535, 10, 10, 0x921, 0x921 }, // 2997 MHZ = 9* 333
Package (0x06) { 2664, 68120, 10, 10, 0x81D, 0x81D },
Package (0x06) { 2331, 56571, 10, 10, 0x71A, 0x71A },
Package (0x06) { 1998, 45889, 10, 10, 0x616, 0x616 }
})
} // end CPU0
Processor (CPU1, 0x01, 0x00000410, 0x06)
{
Name (_PPC, 0x00)
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x04) // 4 Pstates 6-9 fsb muilt
{
/* multi 10 OFF Package (0x06) { 3330, 93816, 10, 10, 0xA25, 0xA25 } */
Package (0x06) { 2997, 80535, 10, 10, 0x921, 0x921 }, // 2997 MHZ = 9* 333
Package (0x06) { 2664, 68120, 10, 10, 0x81D, 0x81D },
Package (0x06) { 2331, 56571, 10, 10, 0x71A, 0x71A },
Package (0x06) { 1998, 45889, 10, 10, 0x616, 0x616 }
})
} // end CPU1
Processor (CPU2, 0x02, 0x00000410, 0x06)
{
} // end CPU2
Processor (CPU3, 0x03, 0x00000410, 0x06)
{
} // end CPU3
}
When I get some time I'm going to try to add c-state (_cst) table in this fashion. See post #53 and page 281 section 8.4.2 of ACPI specs. This could be a more universal method?!
D.
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52
Seeing what differences are made.
