It might be preferred to leave the hotplug feature for only certain ports. I have it enabled and it shows every drive but the boot disk as an external drive...able to eject any of them.
d00d, can you please check your p-state information in your original post. I can not seem to get it compiled, I get an error on line 38 or 39. And maybe give more details on your overclock settings...I was attempting to use this with memory rated for 1600mhz but could not get bios to post. I might need to set static voltage for memory. I managed to get everything else working perfectly Thank you!....although I do get a kernel message on boot that LPC did not load properly and I am using stock cpu bios settings so my geekbench scores are very low at the moment. The only time it does not give an error about LPC is when enabling C-states, but if those are enabled I can not awake from sleep.
Also, sleep works perfectly but obviously only when C1E and C3, C6, C7 modes are disabled. This makes sense now...I read late last night that C states are idle states. I think some people in other threads discussing using them were assuming they were just like p-states...but not defined by the DSDT. I'm assuming there is no need for them because C0 is the only one necessary.
You might be missing the enclosing bracket or coma that's on line 38.
Do `./iasl -d DSDT.aml' on my attached DSDT to get DSDT.dsl, then copy and paste from that.
My over clock settings for 4.1 and 4.2 GHz are listed in a previous post, and for 4.2 I had to set DRAM to 1.58v for 12 GB rated for 1.5v and 1333 MHz (running at 1260 MHz), with all other voltages set to auto.
To get AppleLPC.kext to load you need to fix the PX40 section of the DSDT, and check the `Start up automatically after a power failure' option in Energy Saver, or sleep will shut the computer down instead.
For kernel.log to not show CState errors you need to be clocked at 2.96 GHz or lower, or if clocked higher you need to correct the CPU section of your DSDT to pass CStates to the OS.
Sleep and wake works at any clock with these modifications and C2RC3 and PCEFI10.5, even when either or both of the two CState options are disabled in BIOS.