Iris Xe iGPU on Tiger Lake successfully loaded ICLLP Frambuffer and VRAM also recognizes 1536MB! + However, some issues.

[Visual Ehrmanntraut]

On 12/16/2024 at 7:08 PM, jalavoui said:

struct OSInfo __packed
{
    int64_t id;
    char* model;
    int32_t ports_conf;
    int64_t shmem;
    int32_t mem;
    char connector[0x9][0x18];
    int32_t flags;
    int32_t field_100;
    int64_t field_108;
    int64_t field_110;
    int64_t field_118;
    int64_t field_120;
    int64_t field_128;
    int64_t field_130;
    int64_t field_138;
    int64_t field_140;
    int64_t field_148;
    int64_t field_150;
    int64_t field_158;
    int64_t field_160;
    int64_t field_168;
    int64_t field_170;
    int64_t field_178;
    int64_t field_180;
    int64_t field_188;
    int64_t field_190;
    int64_t field_198;
    int64_t field_1a0;
    int64_t field_1a8;
    int64_t field_1b0;
    int64_t flag2;
    int64_t flag3;
};

 

strucuture is applied to pointer of _gPlatformInformationList. size is 0x1c0

 

I have this:
 

struct IGOSInfo
{
    uint32_t fInfoPlatformID;
    uint32_t field_4;
    char const* fInfoModelName;
    bool fInfoHasLid;
    uint8_t fInfoPipeCount;
    uint8_t fInfoPortCount;
    uint8_t fInfoFramebufferCount;
    uint32_t fInfoFramebufferMemorySize;
    uint32_t fInfoFBCompressionMemorySize;
    uint32_t fInfoUnifiedMemorySize;
    uint8_t field_20[0xd8];
    enum IGOSInfoFlags fInfoFlags;
    __padding char _fc[4];
    uint32_t field_100;
    void* field_108;
    uint32_t field_110;
    void* field_118;
    uint32_t field_120;
    void* field_128;
    uint32_t field_130;
    void* field_138;
    uint32_t field_140;
    void* field_148;
    uint32_t field_150;
    void* field_158;
    uint32_t field_160;
    void* field_168;
    uint32_t field_170;
    void* field_178;
    uint32_t field_180;
    void* field_188;
    uint32_t fCamelliaVersion;
    uint32_t field_194;
    uint32_t field_198;
    uint32_t field_19c;
    uint32_t field_1a0;
    uint32_t field_1a4;
    uint32_t field_1a8;
    uint32_t fInfoDynamicFBCThreshold;
    uint32_t fInfoVideoTurbo;
    uint32_t fMaxSliceCount;
    uint32_t fMaxEUCount;
    uint32_t fMaxSubsliceCount;
};

enum IGOSInfoFlags : uint32_t
{
    OSInfoFlagDisable3D = 0x10000,
    OSInfoFlagEnableFBC = 0x2
};

 

Edited February 7, 2025 by Visual Ehrmanntraut

[jalavoui]

this is interesting. not gonna ask how u got it

enum IGOSInfoFlags : uint32_t
{
    OSInfoFlagDisable3D = 0x10000,
    OSInfoFlagEnableFBC = 0x2
};

what i can't understand atm is values on this function

ulong __thiscall IntelAccelerator::initHardwareCaps(IntelAccelerator *this)

{
  uint uVar1;
  int iVar2;
  int iVar3;
  int iVar4;
  undefined8 unaff_R14;
  ulong uVar5;
  
  if (*(int *)(this + 0x1120) == 2) {
    *(undefined8 *)(this + 0x112c) = 0x222000000c0;
    *(undefined8 *)(this + 0x1134) = 0x22200000150;
    *(undefined4 *)(this + 0x113c) = 0x150;
    *(undefined8 *)(this + 0x1174) = 0x200000007;
    *(undefined8 *)(this + 0x117c) = 0x1000000080;
    *(undefined4 *)(this + 0x1160) = 0xf00;
    *(undefined4 *)(this + 0x1148) = 6;
    uVar1 = *(uint *)(this + 0x1158) >> 1;
    iVar3 = 2;
    iVar4 = 6;
    iVar2 = 0x80;
  }
  else {
    if (*(int *)(this + 0x1120) != 1) {
      uVar5 = 0;
      _IOLog("[IGPU] HWCAPS: invalid Gfx SKU: %d\n");
      _kprintf("[IGPU] HWCAPS: invalid Gfx SKU: %d\n",(ulong)*(uint *)(this + 0x1120));
      goto LAB_0002a7e1;
    }
    *(undefined8 *)(this + 0x112c) = 0x2d800000180;
    *(undefined8 *)(this + 0x1134) = 0x270000001b0;
    *(undefined4 *)(this + 0x113c) = 0x1b0;
    *(undefined8 *)(this + 0x1174) = 0x100000007;
    *(undefined8 *)(this + 0x117c) = 0x1000000040;
    *(undefined4 *)(this + 0x1160) = 0x800;
    *(undefined4 *)(this + 0x1148) = 0xc;
    uVar1 = *(uint *)(this + 0x1158);
    iVar3 = 1;
    iVar4 = 0xc;
    iVar2 = 0x40;
  }
  *(uint *)(this + 0x114c) = uVar1;
  this[0x1184] = (IntelAccelerator)((byte)this[0x1184] & 0xfb);
  *(uint *)(this + 0x1128) = iVar3 * uVar1;
  *(uint *)(this + 0x1144) = (iVar4 - uVar1) * iVar3;
  *(uint *)(this + 0x1140) = iVar2 * uVar1;
  *(int *)(this + 0x1168) = *(int *)(this + 0x115c) << 4;
  uVar5 = CONCAT71((int7)((ulong)unaff_R14 >> 8),1);
LAB_0002a7e1:
  return uVar5 & 0xffffffff;
}

in theory with a few "correct" values the acelerator might just load and do someting usefull

Edited February 7, 2025 by jalavoui

[benmacfreak]

1 hour ago, jalavoui said:

this is interesting. not gonna ask how u got it

enum IGOSInfoFlags : uint32_t
{
    OSInfoFlagDisable3D = 0x10000,
    OSInfoFlagEnableFBC = 0x2
};

what i can't understand atm is values on this function

ulong __thiscall IntelAccelerator::initHardwareCaps(IntelAccelerator *this)

{
  uint uVar1;
  int iVar2;
  int iVar3;
  int iVar4;
  undefined8 unaff_R14;
  ulong uVar5;
  
  if (*(int *)(this + 0x1120) == 2) {
    *(undefined8 *)(this + 0x112c) = 0x222000000c0;
    *(undefined8 *)(this + 0x1134) = 0x22200000150;
    *(undefined4 *)(this + 0x113c) = 0x150;
    *(undefined8 *)(this + 0x1174) = 0x200000007;
    *(undefined8 *)(this + 0x117c) = 0x1000000080;
    *(undefined4 *)(this + 0x1160) = 0xf00;
    *(undefined4 *)(this + 0x1148) = 6;
    uVar1 = *(uint *)(this + 0x1158) >> 1;
    iVar3 = 2;
    iVar4 = 6;
    iVar2 = 0x80;
  }
  else {
    if (*(int *)(this + 0x1120) != 1) {
      uVar5 = 0;
      _IOLog("[IGPU] HWCAPS: invalid Gfx SKU: %d\n");
      _kprintf("[IGPU] HWCAPS: invalid Gfx SKU: %d\n",(ulong)*(uint *)(this + 0x1120));
      goto LAB_0002a7e1;
    }
    *(undefined8 *)(this + 0x112c) = 0x2d800000180;
    *(undefined8 *)(this + 0x1134) = 0x270000001b0;
    *(undefined4 *)(this + 0x113c) = 0x1b0;
    *(undefined8 *)(this + 0x1174) = 0x100000007;
    *(undefined8 *)(this + 0x117c) = 0x1000000040;
    *(undefined4 *)(this + 0x1160) = 0x800;
    *(undefined4 *)(this + 0x1148) = 0xc;
    uVar1 = *(uint *)(this + 0x1158);
    iVar3 = 1;
    iVar4 = 0xc;
    iVar2 = 0x40;
  }
  *(uint *)(this + 0x114c) = uVar1;
  this[0x1184] = (IntelAccelerator)((byte)this[0x1184] & 0xfb);
  *(uint *)(this + 0x1128) = iVar3 * uVar1;
  *(uint *)(this + 0x1144) = (iVar4 - uVar1) * iVar3;
  *(uint *)(this + 0x1140) = iVar2 * uVar1;
  *(int *)(this + 0x1168) = *(int *)(this + 0x115c) << 4;
  uVar5 = CONCAT71((int7)((ulong)unaff_R14 >> 8),1);
LAB_0002a7e1:
  return uVar5 & 0xffffffff;
}

in theory with a few "correct" values the acelerator might just load and do someting usefull

badass jala, glad to hear.. hope we get something to try soon. Keep it up brother.

[Visual Ehrmanntraut]

7 hours ago, jalavoui said:

this is interesting. not gonna ask how u got it

enum IGOSInfoFlags : uint32_t
{
    OSInfoFlagDisable3D = 0x10000,
    OSInfoFlagEnableFBC = 0x2
};

what i can't understand atm is values on this function

ulong __thiscall IntelAccelerator::initHardwareCaps(IntelAccelerator *this)

{
  uint uVar1;
  int iVar2;
  int iVar3;
  int iVar4;
  undefined8 unaff_R14;
  ulong uVar5;
  
  if (*(int *)(this + 0x1120) == 2) {
    *(undefined8 *)(this + 0x112c) = 0x222000000c0;
    *(undefined8 *)(this + 0x1134) = 0x22200000150;
    *(undefined4 *)(this + 0x113c) = 0x150;
    *(undefined8 *)(this + 0x1174) = 0x200000007;
    *(undefined8 *)(this + 0x117c) = 0x1000000080;
    *(undefined4 *)(this + 0x1160) = 0xf00;
    *(undefined4 *)(this + 0x1148) = 6;
    uVar1 = *(uint *)(this + 0x1158) >> 1;
    iVar3 = 2;
    iVar4 = 6;
    iVar2 = 0x80;
  }
  else {
    if (*(int *)(this + 0x1120) != 1) {
      uVar5 = 0;
      _IOLog("[IGPU] HWCAPS: invalid Gfx SKU: %d\n");
      _kprintf("[IGPU] HWCAPS: invalid Gfx SKU: %d\n",(ulong)*(uint *)(this + 0x1120));
      goto LAB_0002a7e1;
    }
    *(undefined8 *)(this + 0x112c) = 0x2d800000180;
    *(undefined8 *)(this + 0x1134) = 0x270000001b0;
    *(undefined4 *)(this + 0x113c) = 0x1b0;
    *(undefined8 *)(this + 0x1174) = 0x100000007;
    *(undefined8 *)(this + 0x117c) = 0x1000000040;
    *(undefined4 *)(this + 0x1160) = 0x800;
    *(undefined4 *)(this + 0x1148) = 0xc;
    uVar1 = *(uint *)(this + 0x1158);
    iVar3 = 1;
    iVar4 = 0xc;
    iVar2 = 0x40;
  }
  *(uint *)(this + 0x114c) = uVar1;
  this[0x1184] = (IntelAccelerator)((byte)this[0x1184] & 0xfb);
  *(uint *)(this + 0x1128) = iVar3 * uVar1;
  *(uint *)(this + 0x1144) = (iVar4 - uVar1) * iVar3;
  *(uint *)(this + 0x1140) = iVar2 * uVar1;
  *(int *)(this + 0x1168) = *(int *)(this + 0x115c) << 4;
  uVar5 = CONCAT71((int7)((ulong)unaff_R14 >> 8),1);
LAB_0002a7e1:
  return uVar5 & 0xffffffff;
}

in theory with a few "correct" values the acelerator might just load and do someting usefull

@jalavoui here's what I got:
 

0002a666    bool IntelAccelerator::initHardwareCaps(class IntelAccelerator* this)

0002a66f        int64_t rax
0002a66f        int64_t var_28 = rax
0002a673        uint32_t fSKU = this->fHWCaps.fSKU
0002a67c        int64_t r14
0002a67c        uint32_t fNumSubSlices
0002a67c        int32_t rcx_1
0002a67c        int32_t rdx_1
0002a67c        int32_t rsi
0002a67c        
0002a67c        if (fSKU == 2) {
0002a70e            this->fHWCaps.field_1c = 0xc0  {"g"}
0002a70e            this->fHWCaps.field_20 = 0x222
0002a71f            this->fHWCaps.field_24 = 0x150
0002a71f            this->fHWCaps.field_28 = 0x222
0002a726            this->fHWCaps.field_2c = 0x150
0002a73a            this->fHWCaps.field_64 = 7
0002a73a            this->fHWCaps.field_68 = 2
0002a74b            this->fHWCaps.field_6c = 0x80
0002a74b            this->fHWCaps.field_70 = 0x10
0002a752            this->fHWCaps.field_50 = 0xf00
0002a75c            this->fHWCaps.field_38 = 6
0002a76c            fNumSubSlices = this->fHWCaps.fNumSubSlices u>> 1
0002a76e            rdx_1 = 2
0002a773            rsi = 6
0002a778            rcx_1 = 0x80
0002a77d            label_2a77d:
0002a77d            this->fHWCaps.field_3c = fNumSubSlices
0002a783            this->fHWCaps.field_74 &= 0xfb
0002a78f            this->fHWCaps.field_18 = rdx_1 * fNumSubSlices
0002a79a            this->fHWCaps.field_34 = (rsi - fNumSubSlices) * rdx_1
0002a7a3            this->fHWCaps.field_30 = rcx_1 * fNumSubSlices
0002a7b2            this->fHWCaps.field_58 = this->fHWCaps.fNumSlices << 4
0002a7b8            r14.b = 1
0002a67c        } else {
0002a685            if (fSKU == 1) {
0002a695                this->fHWCaps.field_1c = 0x180
0002a695                this->fHWCaps.field_20 = 0x2d8
0002a6a6                this->fHWCaps.field_24 = 0x1b0  {"__DATA"}
0002a6a6                this->fHWCaps.field_28 = 0x270
0002a6ad                this->fHWCaps.field_2c = 0x1b0  {"__DATA"}
0002a6c1                this->fHWCaps.field_64 = 7
0002a6c1                this->fHWCaps.field_68 = 1
0002a6d2                this->fHWCaps.field_6c = 0x40
0002a6d2                this->fHWCaps.field_70 = 0x10
0002a6d9                this->fHWCaps.field_50 = 0x800
0002a6e3                this->fHWCaps.field_38 = 0xc
0002a6ed                fNumSubSlices = this->fHWCaps.fNumSubSlices
0002a6f3                rdx_1 = 1
0002a6f8                rsi = 0xc
0002a6fd                rcx_1 = 0x40
0002a702                goto label_2a77d
0002a685            }
0002a685            
0002a7c4            r14 = 0
0002a7cc            _IOLog("[IGPU] HWCAPS: invalid Gfx SKU: …", fSKU)
0002a7dc            _kprintf("[IGPU] HWCAPS: invalid Gfx SKU: …", zx.q(this->fHWCaps.fSKU))
0002a67c        }
0002a7ee        return r14.b

struct _IntelHwCapsInfo
{
    uint32_t fRevisionID;
    uint32_t fPCHRev;
    uint32_t fDeviceID;
    uint32_t fPCHID;
    uint32_t fSKU;
    uint32_t fExecUnitCount;
    uint32_t field_18;
    uint32_t field_1c;
    uint32_t field_20;
    uint32_t field_24;
    uint32_t field_28;
    uint32_t field_2c;
    uint32_t field_30;
    uint32_t field_34;
    uint32_t field_38;
    uint32_t field_3c;
    uint32_t fMaxFrequencyInMhz;
    uint32_t fMinFrequencyInMhz;
    uint32_t fNumSubSlices;
    uint32_t fNumSlices;
    uint32_t field_50;
    uint32_t fL3BankCount;
    uint32_t field_58;
    uint32_t fMaxEUPerSubSlice;
    uint32_t field_60;
    uint32_t field_64;
    uint32_t field_68;
    uint32_t field_6c;
    uint32_t field_70;
    uint8_t field_74;
    uint32_t field_78;
};

 

[jalavoui]

my BN is close to yours except for the memcpy. idk why it is displaying like this

 

 

class IntelAccelerator
{
    __padding char _0[0x40];
    __padding char _40[0x40];
    __padding char _80[0x40];
    __padding char _c0[0x40];
    __padding char _100[0x40];
    __padding char _140[0x40];
    __padding char _180[0x40];
    __padding char _1c0[0x40];
    __padding char _200[0x40];
    __padding char _240[0x40];
    __padding char _280[0x40];
    __padding char _2c0[0x40];
    __padding char _300[0x40];
    __padding char _340[0x40];
    __padding char _380[0x40];
    __padding char _3c0[0x40];
    __padding char _400[0x40];
    __padding char _440[0x40];
    __padding char _480[0x40];
    __padding char _4c0[0x40];
    __padding char _500[0x40];
    __padding char _540[0x40];
    __padding char _580[0x40];
    __padding char _5c0[0x40];
    __padding char _600[0x40];
    __padding char _640[0x40];
    __padding char _680[0x40];
    __padding char _6c0[0x40];
    __padding char _700[0x40];
    __padding char _740[0x40];
    __padding char _780[0x40];
    __padding char _7c0[0x40];
    __padding char _800[0x40];
    __padding char _840[0x40];
    __padding char _880[0x40];
    __padding char _8c0[0x40];
    __padding char _900[0x40];
    __padding char _940[0x40];
    __padding char _980[0x40];
    __padding char _9c0[0x40];
    __padding char _a00[0x40];
    __padding char _a40[0x40];
    __padding char _a80[0x40];
    __padding char _ac0[0x40];
    __padding char _b00[0x40];
    __padding char _b40[0x40];
    __padding char _b80[0x40];
    __padding char _bc0[0x40];
    __padding char _c00[0x40];
    __padding char _c40[0x40];
    __padding char _c80[0x40];
    __padding char _cc0[0x40];
    __padding char _d00[0x40];
    __padding char _d40[0x40];
    __padding char _d80[0x40];
    __padding char _dc0[0x18];
    __padding char _dd8[4];
    __padding char _ddc[0x24];
    __padding char _e00[0x40];
    __padding char _e40[0x40];
    __padding char _e80[0x40];
    __padding char _ec0[0x40];
    __padding char _f00[0x40];
    __padding char _f40[0x40];
    __padding char _f80[0x40];
    __padding char _fc0[0x40];
    __padding char _1000[0x40];
    __padding char _1040[0x40];
    __padding char _1080[0x40];
    __padding char _10c0[0x40];
    __padding char _1100[0x10];
    struct _IntelHwCapsInfo fHWCaps;
};

 

anyway the code starts to make some sense

0002847e  int64_t IntelAccelerator::getGPUInfo(class IntelAccelerator* arg1)

0002849c      IntelAccelerator::SafeForceWake()
000284a1      void* rax = arg1->__offset(0x1240).q
000284cc      int32_t r12 = *(rax + 0x9138)
000284d3      uint32_t rcx = *(rax + 0x913c)
000284dc      char rcx_1 = (*(rax + 0x9134)).b
000284fe      int32_t r14_1 = not.d(*(rax + 0x9140))
00028504      int32_t r13_1 = r14_1 & 0xf00ff
0002850b      int32_t rax_1 = *(rax + 0xd00)
00028515      uint32_t rbx = 0
00028521      IntelAccelerator::SafeForceWake(arg1, 0, 5, zx.q(*(rax + 0x9118)))
00028536      _IOLog("[IGPU] HWCAPS - GPU Sku: %u\n", zx.q(arg1->fHWCaps.fSKU))
0002854b      _kprintf("[IGPU] HWCAPS - GPU Sku: %u\n", zx.q(arg1->fHWCaps.fSKU))
00028556      uint32_t temp0 = _popcnt_u32(r13_1 u>> 8)
00028561      uint32_t temp0_1 = _popcnt_u32(zx.d(r14_1.b))
00028575      _IOLog("[IGPU] HWCAPS - VEDBOXEnableFuse…", zx.q(r13_1))
0002858c      _kprintf("[IGPU] HWCAPS - VEDBOXEnableFuse…", zx.q(r13_1), zx.q(temp0), zx.q(temp0_1))
00028591      uint64_t rax_9 = arg1->__offset(0x1300).q
00028591      
0002859b      if (rax_9 != 0)
0002859d          uint64_t rflags_1
0002859d          uint64_t rax_10
0002859d          rax_10, rflags_1 = _bit_scan_forward(rax_9)
00028603          uint64_t i
00028603          
00028603          do
000285b0              if (rax_10 - 3 u<= 2)
000285b2                  int64_t rcx_5 = rax_10 * 0x79
000285b2                  
000285bb                  if ((*(rcx_5 + &kIGHwCsDesc.rings[0].GEN8_RING_CS_GPR+1) & r13_1) == 0)
000285bd                      uint64_t rcx_6 = zx.q(*(rcx_5 + &kIGHwCsDesc))
000285ce                      uint64_t rsi_5 = rcx_6 u>> 6
000285d2                      *(arg1 + (rsi_5 << 3) + 0x1300) &= rol.q(-2, rcx_6.b)
000285d2              
000285de              if (rax_10 u> 4)
000285de                  break
000285de              
000285f4              i = -2 << rax_10.b & *(arg1 + ((rax_10 + 1) u>> 6 << 3) + 0x1300)
000285fc              uint64_t rflags_2
000285fc              rax_10, rflags_2 = _bit_scan_forward(i)
00028603          while (i != 0)
00028603      
00028605      arg1->fHWCaps.fNumSlices = 0
00028621      int32_t i_1
00028621      
00028621      for (i_1 = 0; i_1 != 8; i_1 += 1)
0002861a          rbx += r12 u>> i_1.b & 1
0002861a      
00028623      arg1->fHWCaps.fNumSlices = rbx
0002863b      _IOLog("[IGPU] HWCAPS - NumSlices:%d    …", zx.q(rbx), zx.q(r12), i_1)
0002864f      _kprintf("[IGPU] HWCAPS - NumSlices:%d    …", zx.q(arg1->fHWCaps.fNumSlices), zx.q(r12))
0002865d      arg1->fHWCaps.fNumSubSlices = _popcnt_u32(rcx) * 2
00028672      _IOLog("[IGPU] HWCAPS - NumSubSlices:%u …")
00028685      _kprintf("[IGPU] HWCAPS - NumSubSlices:%u …", zx.q(arg1->fHWCaps.fNumSubSlices), zx.q(rcx))
0002868e      uint32_t temp0_3 = _popcnt_u32(zx.d(rcx_1))
00028699      arg1->fHWCaps.fMaxEUPerSubSlice = 8 - temp0_3
000286aa      arg1->fHWCaps.fExecUnitCount = arg1->fHWCaps.fNumSubSlices * (8 - temp0_3)
000286bf      _IOLog("[IGPU] HWCAPS - MaxEUPerSubSlice…")
000286d9      _kprintf("[IGPU] HWCAPS - MaxEUPerSubSlice…", zx.q(arg1->fHWCaps.fMaxEUPerSubSlice), zx.q(temp0_3), zx.q(arg1->fHWCaps.fExecUnitCount))
000286e8      arg1->fHWCaps.fMaxFrequencyInMhz = 0x3e8
000286e8      arg1->fHWCaps.fMinFrequencyInMhz = 0x1c2
0002870a      _IOLog("[IGPU] HWCAPS - fMaxFrequencyInM…", 0x3e8, 0x1c2, 0x90014)
00028727      _kprintf("[IGPU] HWCAPS - fMaxFrequencyInM…", zx.q(arg1->fHWCaps.fMaxFrequencyInMhz), zx.q(arg1->fHWCaps.fMinFrequencyInMhz), 0x90014)
0002872c      uint32_t fNumSlices = arg1->fHWCaps.fNumSlices
0002873c      int64_t rcx_11
0002873c      rcx_11.b = fNumSlices u> 1
0002873f      int64_t rax_23 = arg1->__offset(0x1190).q
00028751      arg1->__offset(0x1190).q = (rax_23 & 0xfffffffffffffff7) + (rcx_11 << 3)
00028758      arg1->__offset(0xdd8).d = fNumSlices
0002875f      uint32_t fSKU = arg1->fHWCaps.fSKU
00028766      uint32_t fNumSubSlices = arg1->fHWCaps.fNumSubSlices
0002876d      arg1->__offset(0xddc).d = fNumSubSlices
0002876d      
00028776      if (fSKU == 1)
0002879b          arg1->fHWCaps.fL3BankCount = 8
0002879b          
000287ae          if (fNumSlices != 1 || fNumSubSlices != 0xc)
000287c0              _IOLog("[IGPU] HWCAPS - ERROR: Invalide …")
000287d8              _kprintf("[IGPU] HWCAPS - ERROR: Invalide …", zx.q(arg1->fHWCaps.fNumSlices), zx.q(arg1->fHWCaps.fNumSubSlices))
00028776      else
0002877b          if (fSKU != 2)
0002890a              IntelAccelerator::getGPUInfo()
0002890f              return IntelAccelerator::teardownDevice() __tailcall
0002890f          
00028789          if (fNumSlices == 1 && fNumSubSlices == 0xc)
0002878b              arg1->fHWCaps.fL3BankCount = 8
00028789          else if (fNumSlices != 1 || zx.q(rax_23.d & 0x20) == 0 || fNumSubSlices != 4)
0002880a              _IOLog("[IGPU] HWCAPS - ERROR: Invalid N…")
00028822              _kprintf("[IGPU] HWCAPS - ERROR: Invalid N…", zx.q(arg1->fHWCaps.fNumSlices), zx.q(arg1->fHWCaps.fNumSubSlices))
000287ef          else
000287f1              arg1->fHWCaps.fL3BankCount = 4
000287f1          
00028833          _IOLog("[IGPU] HWCAPS - GPU Sku: TGL GT2…")
0002883d          _kprintf("[IGPU] HWCAPS - GPU Sku: TGL GT2…")
0002883d      
00028856      uint64_t rsi_20 = zx.q(rax_1 u>> 3 & 7)
00028859      int32_t rax_31 = 0x16e3600
00028859      
00028860      if (rsi_20.d u<= 3)
00028869          rax_31 = *(&data_b0bb0 + (rsi_20 << 2))
00028869      
0002886c      uint32_t rax_32 = rax_31 u>> ((not.d(rax_1 u>> 1)).b & 3)
00028885      _g_timestampFreqPerDenominator = zx.q(rax_32 u/ 0x186a0)
00028888      arg1->fHWCaps.field_78 = rax_32
000288a2      _IOLog("[IGPU] HWCAPS - L3BankCount: %u\n", zx.q(arg1->fHWCaps.fL3BankCount), &_g_timestampFreqPerDenominator)
000288b3      _kprintf("[IGPU] HWCAPS - L3BankCount: %u\n", zx.q(arg1->fHWCaps.fL3BankCount))
000288bb      char result = IntelAccelerator::initHardwareCaps(arg1_1: arg1)
000288bb      
000288c2      if (result != 0)
000288d2          return result
000288d2      
000288e6      _IOLog("[IGPU] HWCAPS initHardwareCapsFa…", zx.q(arg1->fHWCaps.fNumSubSlices))
000288eb      arg1->fHWCaps
00028905      jump(_kprintf)  {"_TEXT"}

struct ring
{
    char* id;
    char* classs;
    uint32_t RING_ELSP;
    uint32_t RING_EXECLIST_SQ_CONTENTS;
    uint32_t RING_EXECLIST_CONTROL;
    uint32_t EL_OFFSET_STATUS;
    uint32_t EL_OFFSET_STATUS_PTR;
    uint32_t EL_OFFSET_STATUS_BUF;
    uint32_t field8_0x28;
    uint32_t field9_0x2c;
    uint32_t RING_HWS_PGA;
    uint32_t RING_MODE_GEN7;
    uint32_t RING_RESET_CTL;
    uint32_t RING_EIR;
    uint32_t RING_EMR;
    uint32_t RING_TIMESTAMP;
    uint32_t GEN8_RING_CS_GPR;
    uint32_t executionUnitCountnt;
    uint32_t Contextsize;
    uint32_t field19_0x54;
    uint32_t field20_0x58;
    uint32_t field21_0x5c;
    char field22_0x60[0x4];
    char field23_0x64[0x4];
    char field24_0x68[0x4];
    uint32_t FORCEWAKE;
    uint32_t FORCEWAKE_ACK;
    uint32_t flags;
    bool field28_0x78;
};

struct IGHwCsDesc
{
    char kIGHwCsDesc;
    char field1_0x1;
    char field2_0x2;
    char field3_0x3;
    char field4_0x4;
    struct ring rings[0x6];
};

 

Edited February 7, 2025 by jalavoui

[jalavoui]

from linux this card should have fNumSubSlices=5

but the code only makes sense if  fNumSubSlices= 6

change it in nblue but not the fHWCaps.fNumSubSlices field

 

let's say for  dgpu this->fHWCaps.fNumSubSlices is 6

fNumSubSlices = this->fHWCaps.fNumSubSlices >> 1 (= 3)
            rdx_1 = 2
            rsi = 6
            rcx_1 = 0x80
            label_2a77d:
            this->fHWCaps.field_3c = fNumSubSlices (= 3)
            this->fHWCaps.field_74 &= 0xfb
            this->fHWCaps.field_18 = rdx_1 * fNumSubSlices (= 6)
            this->fHWCaps.field_34 = (rsi - fNumSubSlices) * rdx_1 (= 6)
            this->fHWCaps.field_30 = rcx_1 * fNumSubSlices (= 0x180)
            this->fHWCaps.field_58 = this->fHWCaps.fNumSlices << 4 (= 0x60)

 

so we got a "setup" for 6 SubSlices and idk howto convert all variables so it can work for 5

there also other variables to consider like fHWCaps.fL3BankCount = 4 (i think this wont work for igpu)

 

 

most probably os x code is made for dgpu and might need some changes for igpu (mem offsets, sizes, etc)

 

so guessing

for  igpu this->fHWCaps.fNumSubSlices is 5

fNumSubSlices = this->fHWCaps.fNumSubSlices >> 1 (= 2)
            rdx_1 = 2
            rsi = 5 (changed to 5)
            rcx_1 = 0x80
            label_2a77d:
            this->fHWCaps.field_3c = fNumSubSlices (= 2)
            this->fHWCaps.field_74 &= 0xfb
            this->fHWCaps.field_18 = rdx_1 * fNumSubSlices (= 4)
            this->fHWCaps.field_34 = (rsi - fNumSubSlices) * rdx_1 (= 6)
            this->fHWCaps.field_30 = rcx_1 * fNumSubSlices (= 0x100)
            this->fHWCaps.field_58 = this->fHWCaps.fNumSlices << 4 (= 0x50)

 

maybe this is correct but what about other values used on original SKU=2 ?

 

this->fHWCaps.field_1c = 0xc0

this->fHWCaps.field_20 = 0x222

this->fHWCaps.field_24 = 0x150

this->fHWCaps.field_28 = 0x222

this->fHWCaps.field_2c = 0x150

this->fHWCaps.field_64 = 7

this->fHWCaps.field_68 = 2

this->fHWCaps.field_6c = 0x80

this->fHWCaps.field_70 = 0x10

this->fHWCaps.field_50 = 0xf00

this->fHWCaps.field_38 = 6

Edited February 8, 2025 by jalavoui

[Visual Ehrmanntraut]

On 2/7/2025 at 4:16 PM, jalavoui said:

my BN is close to yours except for the memcpy. idk why it is displaying like this

 

nested struct handling bug in the optimiser, I talked to the devs, it will be fixed soon hopefully

[jalavoui]

long time ago there was a guy that decided to inspect the windows drivers in order to find usefull infor for mac os x drivers.

 

with that in mind i'll leave a link of intel drivers for further investigation.

 

https://www.intel.com/content/www/us/en/download/785597/intel-arc-iris-xe-graphics-windows.html

 

tons of files in here so idk where to look at

 

found symbols here

https://software.intel.com/sites/downloads/symbols/

 

and so far this file

 

and yes this are "windows" files...

Edited February 9, 2025 by jalavoui

[Mastachief]

I have found a lot of files, but it appears that based on the way windows does the driver, it has a lot extra information for the entire subset of cards used, I dont see a iris XE only driver for windows, so do i need to go back to trying the mesa driver?

[omegax]

Apologies if this is the wrong place. I have a Dell Latitude 5420 with Intel Iris Xe iGPU. I am attempting to use the modified WhateverGreen.kext provided in this thread. 
A few things: 
(1) I didn't use SSDT as when I used SSDTTime it dumped all the tables into 12 individual SSDT files - not sure which to use. 
(2) I generated a USBmap with USBToolBox and put both kexts on the USB installer disk (USBToolBox.kext and UTBMap.kext). 
(3) I also have AppleALC, IntelMausi, Lilu, VirtualSMC kexts on the USB as well. 
(4) I kept the 40+ *.efi files in the OC\Drivers folder, though I did try a few times with a minimal set of *.efi files (OpenHfsPlus/OpenNtfsDxe/OpenRuntime/ToggleSipEntry/XhciDxe) but it didn't make any difference.
(5) I used ProperTree on the sample.plist that came with OpenCore-1.0.4 to generate the config.plist on the installer disk.
(6) I have tried building the installer using the manual dortania guide's method as well as gibMacOS (chose OpenCore). 
(7) I boot and select the USB, I get the menu which for some reason includes all the *.efi files in the Drivers folder. I choose the "MacOS Base System (external)" and it reads the USB stick for a while, the apple logo on the black background comes up, and then nothing.
(8) I tried attaching an external HDMI monitor to it, but I guess it is too early in the boot process so nothing is being sent to it (it is just blank).

I am guessing I haven't customized my config.plist enough/properly so any help or suggestions are welcome. Thank you!

 

[Mastachief]

I'm sorry, these are not necessarily igpu related issues (which this thread is focusing on) but just general opencore issues, get those resolved forst, you can boot in Vesa mode using the -igfxvesa boot flag and then you can start resolving igpu issues thereafter.

I strongly recommend you fix the booting issues and read the opencore guide at least three times, watch a few videos too to help you understand what you are trying to do, good luck.

[jalavoui]

there is a fresh project here https://github.com/pawan295/Appleinteltgldriver.kext

 

i'm glad someone else is also trying to make this work.

 

This kext (for now) only loads in /L/E and you can get some kp while testing and the system will loop on kernel panics.

 

so i found out that if i use nblue and force icl frame to load it will overwrite the new tgl kext and allow system to boot.

 

here's what i'm using to boot if tgl gives a kp.

 

NootedBlue.kext.zip

 

if u wanna test the new tgl just edit oc config and disable nblue.

Edited December 12, 2025 by jalavoui

[jalavoui]

wonder why they do this "fixes"

this is why a few displays fail to work

 

void __thiscall AppleIntelBaseController::initPlatformWorkarounds(AppleIntelBaseController *this)

{
  flagosinfo *pfVar1;
  flagosinfo fVar2;
  
  _DAT_00153e70 = _DAT_00153e70 + 1;
  pfVar1 = &this->flagsosinfo;
  _bzero(pfVar1,4);
  if (this->fPCIConfigRevisionID == 0) {
    _DAT_00153e78 = _DAT_00153e78 + 1;
    _DAT_00153e80 = _DAT_00153e80 + 1;
    *pfVar1 = *pfVar1 | (FB_FLAG_ENABLE_SLICE_FEATURES|FB_FLAG_ENABLE_BACKLIGHT_REG_CONTROL);
  }
  _DAT_00159d30 = _DAT_00159d30 + 1;
  if (*(int *)((long)&this->osinfo->_gPlatformInformationList + 4) == 0) {
    _DAT_00153e88 = _DAT_00153e88 + 1;
    fVar2 = *pfVar1 | FB_FLAG_LIMIT_4K_SOURCE_SIZE;
    *pfVar1 = fVar2;
  }
  else {
    fVar2 = *pfVar1;
  }
  *pfVar1 = fVar2 | (FB_FLAG_ALTERNATE_PWM_INCREMENT1|FB_FLAG_DISABLE_HIGH_BITRATE_MODE2|
                     FB_FLAG_FORCE_POWER_ALWAYS_CONNECTED|FB_FLAG_AVOID_FAST_LINK_TRAINING);
  return;
}

 

Edited March 22 by jalavoui

[Stezza88]

I'm still alive... soon news by me.

[Stezza88]

For acceleration working! Let's nootedgreen!
 

[jalavoui]

i've just created this in linux

 

22:20:19 [INFO ] ============================================================
22:20:19 [INFO ]  Intel GPU Extractor v8.6
22:20:19 [INFO ]  Target: I915, XE
22:20:19 [INFO ] ============================================================
22:20:19 [INFO ] [1/7] Checking dependencies...
22:20:19 [INFO ] [2/7] Preparing source...
22:20:19 [INFO ] [3/7] Configuring kernel...
22:20:19 [INFO ] Executing: make LLVM=1 defconfig
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_KMS_HELPER
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_TTM
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_SCHED
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_BUDDY
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_EXEC
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_GPUVM
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_GPUSVM
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_MIPI_DSI
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_GEM_SHMEM_HELPER
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_TTM_HELPER
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_PANEL_BRIDGE
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_ACPI
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DEBUG_FS
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_HWMON
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_PCI_IOV
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_PERF_EVENTS
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_COMPAT
22:20:35 [INFO ] Executing: ./scripts/config --set-val CONFIG_DRM_I915 m
22:20:35 [INFO ] Executing: ./scripts/config --set-val CONFIG_DRM_XE m
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_I915_DP_TUNNEL
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_I915_GVT
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_I915_PXP
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_I915_CAPTURE_ERROR
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_I915_SELFTEST
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_XE_DISPLAY
22:20:35 [INFO ] Executing: ./scripts/config --enable CONFIG_DRM_XE_DP_TUNNEL
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_TTM
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_SCHED
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_BUDDY
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_EXEC
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_GPUVM
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_GPUSVM
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_MIPI_DSI
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_GEM_SHMEM_HELPER
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_TTM_HELPER
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_PANEL_BRIDGE
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_ACPI
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DEBUG_FS
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_HWMON
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_PCI_IOV
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_PERF_EVENTS
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_COMPAT
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_I915_DP_TUNNEL
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_I915_GVT
22:20:35 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_I915_PXP
22:20:36 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_I915_CAPTURE_ERROR
22:20:36 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_I915_SELFTEST
22:20:36 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_XE_DEBUG_SRIOV
22:20:36 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_XE_DEBUG
22:20:36 [INFO ] Executing: ./scripts/config --disable CONFIG_DEBUG_FS
22:20:36 [INFO ] Executing: ./scripts/config --disable CONFIG_DRM_I915_DEBUG_RUNTIME_PM
22:20:36 [INFO ] Executing: make LLVM=1 olddefconfig
22:20:39 [INFO ] Generating autoconf.h...
22:20:39 [INFO ] Executing: make LLVM=1 prepare
22:21:40 [INFO ] [4/7] Compiling i915, xe module(s)...
22:21:40 [INFO ] Executing: make LLVM=1 scripts
22:21:41 [INFO ]   -> Building i915...
22:23:34 [INFO ]   -> Building xe...
22:25:22 [WARNING] i915.ko failed to link, falling back to i915.o for build artifacts.
22:25:22 [WARNING] xe.ko failed to link, falling back to xe.o for build artifacts.
22:25:22 [INFO ] Compiled successfully in 221s.
22:25:22 [INFO ] [5/7] Scanning build artifacts for dependencies...
22:25:55 [INFO ] Resolved 590 sources, 1902 headers.
22:25:55 [INFO ] [6/7] Extracting CONFIG flags...
22:25:55 [INFO ] Extracted 1668 CONFIG flags
22:25:55 [INFO ] [7/7] Extracting compiler flags...
22:25:55 [INFO ] Flags: 23 Xcode-safe, 15 Defines
22:25:55 [INFO ] Extracting files (STRICTLY from .cmd deps)...
22:25:55 [INFO ] Copied 2492 base + 179 module-specific files.
22:25:55 [INFO ] Normalizing includes (Pass 1: Hierarchical Resolution)...
22:25:55 [INFO ] Indexing kernel source tree for on-demand fallback...
22:25:56 [INFO ] Indexed 64545 fallback files.
22:25:57 [INFO ] Pass 1 Complete: 7271 angle, 46 pulled, 25 disabled.
22:25:57 [INFO ] Normalizing includes (Pass 2: Verification & Force-Fix)...
22:25:58 [WARNING] Pass 2 fixed 89 missed includes that failed in Pass 1!
22:25:58 [INFO ] Final Tally: 7360 angle, 1369 quoted. Pulled: 46. Disabled: 25, .c: 71
22:25:58 [INFO ] Detailed log written to /home/linux/i915_xe_extracted/extraction_changes.log
22:25:58 [INFO ] Adding extern C guards...
22:25:58 [INFO ] Added extern C to 1922 headers
22:25:58 [INFO ] Generating Xcode compatibility layer...
22:25:58 [INFO ] Prepending __extract_compat.h...
22:25:59 [INFO ] Prepended to 2718 files
22:25:59 [INFO ] 
============================================================
22:25:59 [INFO ]  EXTRACTION SUCCESSFUL
22:25:59 [INFO ]  Output: /home/linux/i915_xe_extracted
22:25:59 [INFO ]  Files: 2721
22:25:59 [INFO ] ============================================================

it is useful for browsing  code and follow structures in xcode 

add to xcode let it index and you can browse intel code

 

 

idk if someone can add mackernelSDK to this and ask AI to make os x bridge

 

better move this to tgl source code thread. i change the script to use master tree and they just updated i915 sources with lots of fixs

 

Edited April 22 by jalavoui

[Mastachief]

5 hours ago, jalavoui said:

 

 

idk if someone can add mackernelSDK to this and ask AI to make os x bridge

 

 

🙂

[jalavoui]

the linux source with resolved structs is quite nice.

 

- why my display xxx always break ?

 

and as now linked cross works in xcode

 

 

[jalavoui]

dam bug !

 

[Visual Ehrmanntraut]

On 4/21/2026 at 12:29 AM, jalavoui said:

idk if someone can add mackernelSDK to this and ask AI to make os x bridge

 

GPU SDK is closed-source. LLMs can barely make simple apps and fixes and it'll forever stay at that. Use your brain and ignore the hype instead of letting the hallucinator pro slow down your tasks. 

[jalavoui]

looks like bios connectors

 

 

if linux says "Samsung SyncMaster 205BW. Note: irony" then fine

static const struct edid_quirk {
	const struct drm_edid_ident ident;
	u32 quirks;
} edid_quirk_list[] = {
	/* Acer AL1706 */
	EDID_QUIRK('A', 'C', 'R', 44358, BIT(EDID_QUIRK_PREFER_LARGE_60)),
	/* Acer F51 */
	EDID_QUIRK('A', 'P', 'I', 0x7602, BIT(EDID_QUIRK_PREFER_LARGE_60)),

	/* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
	EDID_QUIRK('A', 'E', 'O', 0, BIT(EDID_QUIRK_FORCE_6BPC)),

	/* BenQ GW2765 */
	EDID_QUIRK('B', 'N', 'Q', 0x78d6, BIT(EDID_QUIRK_FORCE_8BPC)),

	/* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
	EDID_QUIRK('B', 'O', 'E', 0x78b, BIT(EDID_QUIRK_FORCE_6BPC)),

	/* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
	EDID_QUIRK('C', 'P', 'T', 0x17df, BIT(EDID_QUIRK_FORCE_6BPC)),

	/* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
	EDID_QUIRK('S', 'D', 'C', 0x3652, BIT(EDID_QUIRK_FORCE_6BPC)),

	/* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
	EDID_QUIRK('B', 'O', 'E', 0x0771, BIT(EDID_QUIRK_FORCE_6BPC)),

	/* Belinea 10 15 55 */
	EDID_QUIRK('M', 'A', 'X', 1516, BIT(EDID_QUIRK_PREFER_LARGE_60)),
	EDID_QUIRK('M', 'A', 'X', 0x77e, BIT(EDID_QUIRK_PREFER_LARGE_60)),

	/* Envision Peripherals, Inc. EN-7100e */
	EDID_QUIRK('E', 'P', 'I', 59264, BIT(EDID_QUIRK_135_CLOCK_TOO_HIGH)),
	/* Envision EN2028 */
	EDID_QUIRK('E', 'P', 'I', 8232, BIT(EDID_QUIRK_PREFER_LARGE_60)),

	/* Funai Electronics PM36B */
	EDID_QUIRK('F', 'C', 'M', 13600, BIT(EDID_QUIRK_PREFER_LARGE_75) |
					 BIT(EDID_QUIRK_DETAILED_IN_CM)),

	/* LG 27GP950 */
	EDID_QUIRK('G', 'S', 'M', 0x5bbf, BIT(EDID_QUIRK_CAP_DSC_15BPP)),

	/* LG 27GN950 */
	EDID_QUIRK('G', 'S', 'M', 0x5b9a, BIT(EDID_QUIRK_CAP_DSC_15BPP)),

	/* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
	EDID_QUIRK('L', 'G', 'D', 764, BIT(EDID_QUIRK_FORCE_10BPC)),

	/* LG Philips LCD LP154W01-A5 */
	EDID_QUIRK('L', 'P', 'L', 0, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)),
	EDID_QUIRK('L', 'P', 'L', 0x2a00, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)),

	/* Samsung SyncMaster 205BW.  Note: irony */
	EDID_QUIRK('S', 'A', 'M', 541, BIT(EDID_QUIRK_DETAILED_SYNC_PP)),
	/* Samsung SyncMaster 22[5-6]BW */
	EDID_QUIRK('S', 'A', 'M', 596, BIT(EDID_QUIRK_PREFER_LARGE_60)),
	EDID_QUIRK('S', 'A', 'M', 638, BIT(EDID_QUIRK_PREFER_LARGE_60)),

	/* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
	EDID_QUIRK('S', 'N', 'Y', 0x2541, BIT(EDID_QUIRK_FORCE_12BPC)),

	/* ViewSonic VA2026w */
	EDID_QUIRK('V', 'S', 'C', 5020, BIT(EDID_QUIRK_FORCE_REDUCED_BLANKING)),

	/* Medion MD 30217 PG */
	EDID_QUIRK('M', 'E', 'D', 0x7b8, BIT(EDID_QUIRK_PREFER_LARGE_75)),

	/* Lenovo G50 */
	EDID_QUIRK('S', 'D', 'C', 18514, BIT(EDID_QUIRK_FORCE_6BPC)),

	/* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
	EDID_QUIRK('S', 'E', 'C', 0xd033, BIT(EDID_QUIRK_FORCE_8BPC)),

	/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
	EDID_QUIRK('E', 'T', 'R', 13896, BIT(EDID_QUIRK_FORCE_8BPC)),

	/* Valve Index Headset */
	EDID_QUIRK('V', 'L', 'V', 0x91a8, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b0, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b1, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b2, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b3, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b4, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b5, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b6, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b7, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b8, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91b9, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91ba, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91bb, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91bc, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91bd, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91be, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('V', 'L', 'V', 0x91bf, BIT(EDID_QUIRK_NON_DESKTOP)),

	/* HTC Vive and Vive Pro VR Headsets */
	EDID_QUIRK('H', 'V', 'R', 0xaa01, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('H', 'V', 'R', 0xaa02, BIT(EDID_QUIRK_NON_DESKTOP)),

	/* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
	EDID_QUIRK('O', 'V', 'R', 0x0001, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('O', 'V', 'R', 0x0003, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('O', 'V', 'R', 0x0004, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('O', 'V', 'R', 0x0012, BIT(EDID_QUIRK_NON_DESKTOP)),

	/* Windows Mixed Reality Headsets */
	EDID_QUIRK('A', 'C', 'R', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('L', 'E', 'N', 0x0408, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('F', 'U', 'J', 0x1970, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('D', 'E', 'L', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('S', 'E', 'C', 0x144a, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('A', 'U', 'S', 0xc102, BIT(EDID_QUIRK_NON_DESKTOP)),

	/* Sony PlayStation VR Headset */
	EDID_QUIRK('S', 'N', 'Y', 0x0704, BIT(EDID_QUIRK_NON_DESKTOP)),

	/* Sensics VR Headsets */
	EDID_QUIRK('S', 'E', 'N', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)),

	/* OSVR HDK and HDK2 VR Headsets */
	EDID_QUIRK('S', 'V', 'R', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)),
	EDID_QUIRK('A', 'U', 'O', 0x1111, BIT(EDID_QUIRK_NON_DESKTOP)),

	/* LQ116M1JW10 displays noise when 8 bpc, but display fine as 6 bpc */
	EDID_QUIRK('S', 'H', 'P', 0x154c, BIT(EDID_QUIRK_FORCE_6BPC)),

	/*
	 * @drm_edid_internal_quirk entries end here, following with the
	 * @drm_edid_quirk entries.
	 */

	/* HP ZR24w DP AUX DPCD access requires probing to prevent corruption. */
	EDID_QUIRK('H', 'W', 'P', 0x2869, BIT(DRM_EDID_QUIRK_DP_DPCD_PROBE)),
};

 

Edited May 20 by jalavoui

[jalavoui]

defining a variable as expected by the function is the magic need to make a patch.

nblue::klibMTLIGCCompilerPluginOriginal

 

[jalavoui]

idk if anyone testing adlp but as current research shows frame as small display issues this is worth checking

 

 

this is in nblue linux sources. adlp needs small fixes to have a working framebuffer

 

there's others like this just need someone with the hardware to fix it