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[Guide] macOS Sierra 10.12.1 + Windows 10 - Dual boot - Cintiq Companion 2

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NOTE: This guide mixes static patch with hotpatch. It will be edited to make it works only with static patch soon. There's zero issues with this guide but it seems better not to mix patching methods (thanks, RehabMan)

 

Hello, everybody! 

 

After two years of using my Cintiq Companion 2 with Yosemite thanks to mactabletman’s guide and reading, testing a lot and trying to understand what I was doing, I’m in a good path to share my experiences and help you to install macOS Sierra in your Companion 2 keeping your Windows installation.

There are a few things that need to be solved, like sleep/wake (Cintiq goes to sleep, led blinks but display doesn’t wake up, maybe framebuffer, IOKit or PWR related) or audio using AppleHDA for codec ALC286 instead of VoodooHDA (I will add notes in each section about all this).

 

WE HAVE GOOD NEWS, CINTIQ MODE WORKS!!

(see notes at the bottom)

 

No need to say that I’m taking zero responsibilities of what happened if you follow this guide. We are all grown people and before taking any step you better read all the info you can find about what you are trying to accomplish. 

 

This guide is done for the Cintiq Companion 2 i5-4258U 128GB model (DTHW1310L) with the last BIOS version (MB01) but can be useful as a start for other CPU/graphic models. I’m assuming you updated or reinstalled and have Windows 10 running but same procedure is required for Windows 8/8.1.

 

WORKING: All except wake from sleep using Power Button (wake well if previously connected in Cintiq mode), PCI Realtek SD Card Reader, volume buttons and HDMI audio.

 

So first, things you are going to need:

 

- 2 usb drives (16GB and 32GB minimum), one for create an installer and another to install Sierra into.

- 1 usb keyboard and 1 usb mouse since Clover has no support for touch devices and touch doesn't work natively in Sierra as it does in Yosemite.

- 1 usb drive for Clonezilla (*optional but recommended)

- 1 external hard drive to backup your whole internal SSD using Clonezilla (*optional but recommended)

- An original Apple computer to create installer.

- A BCM94352Z WiFi and Bluetooth 4.0 card to replace default Intel wireless card. You can check how to open your device here.

 

* In order to create a Clonezilla Live USB, I recommend to use Yumi. You can create a multiboot installer for your Windows version, Ubuntu, Wifislax… very useful stuff. 

 

 

CREATING THE INSTALLER…

 

Ok, you did a backup of your data, so let’s create a usb installer for macOS Sierra:

 

- Download macOS Sierra from App Store, this will download the last update 10.12.1 

- Open Disk Utility and format your 16GB usb to HFS+J, GUID partition and rename it to install_osx.

- Copy and paste these commands in Terminal, one by one:

sudo "/Applications/Install macOS Sierra.app/Contents/Resources/createinstallmedia" --volume  /Volumes/install_osx --applicationpath "/Applications/Install macOS Sierra.app" --nointeraction

sudo diskutil rename "Install macOS Sierra" install_osx

INSTALLING CLOVER IN USB INSTALLER…

 

Now open the Clover installer and select your Install macOS Sierra USB, click on “Customize” and use this configuration:

 

- Check Install for UEFI booting only, Install Clover in the ESP is also automatically selected

- Check embebbed theme.

- Check OsxAptioFixDrv-64 from Drivers64UEFI

- Check PartitionDxe-64 from Drivers64UEFI

- Check EmuVariableUefi-64 from Drivers64UEFI*

- Check Install RC scripts on target volume from Drivers64UEFI*

- Click Install.

 

Clover_driversuefi.png

 

After install Clover, a EFI partiton is mounted. Go to EFI/CLOVER, delete that config.plist and put my config_install.plist there. Rename it to config.plist. 

 

- Go to EFI/CLOVER/Drivers64UEFI and delete VboxHfs-64.efi. Put there HFSPlus.efi.

- Go to EFI/CLOVER/kexts/ and leave only "10.12" and “Other” folders. Put FakeSMC.kext inside both of them.

Now your installer USB is ready.

 

*NOTES ABOUT NVRAM

 

EmuVariableUefi-64 and Install RC scripts on target volume might be needed to make NVRAM works in a dual boot configuration since both systems read and write there (I guess). Or maybe our device has not NVRAM hardware, I don’t know. Anyway, I’ve tested it. To test NVRAM, type this in Terminal:

sudo nvram MyVar=TestValue

Check/show NVRAM:

nvram -p

You should see the following entry among others: 

MyVar=TestValue

Reboot, check NVRAM again and if above entry persists, your NVRAM is working. Mine didn’t installing only OsxAptioFixDrv-64, so I reinstalled Clover with EmuVariableUefi-64 and Install RC scripts on target volume.

 

 

BIOS CONFIGURATION…

 

Check your BIOS. Press power button while holding volume up button to enter BIOS.

- CPU Configuration: Boot performance mode: Turbo performance; EIST: enabled; Turbo Mode: enabled; Performance/Watt: Performance; Configurable TDP: TDP Nominal.

- Intel Smart Connect Technology: disabled.

- CSM configuration: CSM Support: enabled; Network: Do not launch; Video: Legacy.

- Chipset/System Agent (SA) Configuration/Graphics Configuration: Aperture Size: 256MB; DVMT Pre-Allocated: 128MB; DVMT Total Gfx Mem: MAX.

- BOOT: Fast Boot: disabled; Boot mode select: dual; all fixed boot order priorities disabled except for UEFI USB KEY.

- Save & Exit.

 

 

BOOTING INSTALLER…

 

Now, to boot into Clover you just need to reboot with your installer usb plugged, so your motherboard recognize the UEFI entry in that drive. Click on power icon in Windows, and while pressing SHIFT, click on reset to go to Windows Boot Manager. Click on "Use a device" and next on "UEFI: SanDisk, Partiton 1" (if you are using SanDisk drive, if not it will be diferent but easily to discover).

 

Click enter in your keyboard to boot "Install macOS Sierra". You will se the verbose log in order to fix any boot issue (you shouldn't need to if you follow this guide). 

 

Open Disk Utility and format your 32GB drive to HFS+J, GUID partition and give it a name, for example, SierraHD. Close Disk Utility and Select Install macOS Sierra and install it to your SierraHD drive. Wait until it reboots after creating the Recovery partition. You will need to boot again into Clover and boot this time from your new boot entry in your SierraHD drive to finish installation.

 

 

INSTALLING CLOVER TO SIERRAHD USB…

 

After install macOS Sierra you might want to install Clover to your SierraHD drive so you don’t need both usb drives to be plugged in order to boot. Follow same steps than before in INSTALLING CLOVER IN USB INSTALLER…

 

Ok, now you’re able to boot into your macOS Sierra but you don’t have CPU PM, IGPU PM, backlight control, battery level… Some of them will be fixed installing kexts, other with DSDT patches or renames, some with Clover… 

 

 

ACPI FILES - DSDT & SSDT

 

ACPI Tables Extraction using Clover

 

Press F4 in Clover boot menu and OEM ACPI tables will be placed in EFI/CLOVER/ACPI/origin. Copy only those files named DSDT.aml and SSDT-X.aml (where X is any number) to your desktop in a new folder called ACPI that we will use to disassemble with iASL.

 

Disassembling ACPI files

 

Download iASL to your Downloads directory, type this in Terminal:

cd ~/Downloads
git clone https://github.com/RehabMan/Intel-iasl.git iasl.git
cd iasl.git
make
sudo make install

Install MaciASL.app to your Applications directory and run this command in Terminal to update iASL:

sudo cp /usr/bin/iasl /Applications/MaciASL.app/Contents/MacOS/iasl61

Now we are going to disassemble the files. Type in Terminal:

cd Desktop
cd ACPI
iasl -da -dl *.aml

You can also try to disassemble them using External declarations in a text file called refs.txt. This may help to fix some unresolved externals (symbols not defined in any file). Copy the following text and create a refs.txt into ACPI folder in your Desktop:

External(MDBG, MethodObj, 1)
External(_GPE.MMTB, MethodObj, 0)
External(_SB_.PCI0.LPCB.H_EC.ECWT, MethodObj, 2)
External(_SB_.PCI0.LPCB.H_EC.ECRD, MethodObj, 1)
External(_SB_.PCI0.PEG0.PEGP.SGPO, MethodObj, 2)
External(_SB.PCI0.GFX0.DD02._BCM, MethodObj, 1)
External(_SB.PCI0.SAT0.SDSM, MethodObj, 4)
External(_SB.PCI0.SAT1.SDSM, MethodObj, 4)
External(_GPE.VHOV, MethodObj, 3)

Type in Terminal:

iasl -da -dl -fe refs.txt *.aml

Using refs.txt or not, this will create .dsl files that we will use to patch. Open them using MaciASL and click “Compile” to check for errors. Main mission here is to have them compile without errors (warnings and optimizations are ok).

 

We only need DSDT and all non dynamic SSDT files. Clover shows dynamic SSDT files adding "x" (SSDT-4x.aml for example). Use dynamic files only to disassemble.

 

NOTE: never open .aml files with MaciASL and compile, if you ever get lost among DSDT and SSDT files, extract and disassemble them again.

 

 

POST-INSTALLATION…

 

Ok, we can boot our Sierra installation, we have our ACPI files disassembled and with no errors, not patched yet, so it’s time to start fixing things.

 

First thing to fix must be CPU Power Management. For that we use ssdtPRGen.sh. In my CC2_PACK.zip there is a SSDT for my CPU (i5-4258U).

 

If you have other CPU, you need to generate a proper one (you will need internet access so install now FakePCIID and FakePCIID_Broadcom_WiFi and copy all WiFi related Clover patches from config_OK.plist to your config.plist). Open Terminal and type this command to download ssdtPRGen:

curl -o ~/ssdtPRGen.sh https://raw.githubusercontent.com/Piker-Alpha/ssdtPRGen.sh/master/ssdtPRGen.sh

Now change the file mode (+x) with:

chmod +x ~/ssdtPRGen.sh

Default SSDT generation:

sudo ~/ssdtPRGen.sh

Type n and n one more time. Open Finder and go to /Library/ssdtPRGen/. You will see a SSDT.aml, this is our CPU Power Management SSDT. Copy it to your EFI/CLOVER/ACPI/patched. You will see if PM is well implemented if X86PlatformPligin is loaded under CPU0@0 in IOReg (use IORegistryExplorer to check it. You can also use AppleIntelInfo.kext)

 

Open SSDT-HACK.dsl with MaciASL, save it as SSDT_HACK.aml and put it into EFI/CLOVER/ACPI/patched. You can check SSDT-HACK.dsl to see what I did there (Basically, emulate Windows (_OSI to XOSI), injecting IGPU properties and ig-platform, disabling EHCI, injecting XHC properties, fixing GPRW to avoid instant wake and making EXEL and ESEL do nothing).

 

Second thing should be IGPU Power Management. For that GFX0 needs to be renamed to IGPU in our DSDT and all SSDT files that contain any GFX0 reference. We will rename it in DSDT using Clover patch and manually find/replace in SSDT files (in our case, SSDT-7 has some GFX0 code).

 

Third, we are going to install some kexts to enable Bluetooth, WiFi (if you replaced default wireless card with BCM94352Z), all USB ports and backlight control. Just open Kext Wizard (we will always use it to install kext files), click “Install” and look for:

 

- FakeSMC.kext

- FakePCIID.kext

- FakePCIID_Broadcom_WiFi.kext

- IntelBacklight.kext

- XHCInjectorCC2.kext

- BrcmPatchRAM2.kext

- BrcFirmwareRepo.kext

 

Any time you install any kext file, you must rebuild your cache and fix permissions. You can do it with KextWizard but it is recommended to use Terminal (see TIPS AND EXTRAS)

 

Now that you have WiFi enabled, OS X probably put it at en1 while Bluetooth PAN is at en0. To reorder them just do the following:

 

- Go to System Preferences > Network and delete all interfaces (WiFi and Bluetooth PAN). If you are asked about bluetooth reappearing again, click no.

- In Finder go to ~/Library/Preferences/SystemConfiguration and delete NetworkInterfaces.plist.

- Reboot, go to System Preferences > Network and add your WiFi interface again.

 

This will reorder your interfaces, leaving WiFi as en0 and letting you to access Apple services as Mac App Store. You still needing to create a good SMBIOS profile, with a serial, etc. in order to activate everything: FaceTime, iMessage, Mac App Store… You can follow these guides:

 

How to enable iMessage

Clover: iMessage/Facetime Fix for Yosemite

 

With all this you will have everything working except for battery status and audio/sound. Now it's a good time to install Wacom drivers.

 

Battery status needs ACPIBatteryManager.kext to be installed and a patched DSDT. I’ve created a patch that you can use with MaciASL and your DSDT (you extracted and disassembled before, remember?), just click “Patch” and look for Battery CC2 Patch.txt, apply and save.

NOTE: Recent tests with RehabMan probes my patch matches Dell XPS 18, so that will work too. Use any of them.

 

IMPORTANT: Until now we were booting with ACPI/SSDT/DropOEM=false because we weren't using patched OEM files. Now we are going to use a DSDT file, so we must also provide all patched SSDT files, set DropOEM=true and set SorterOrder (same order than OEM files, making SSDT.aml the first and SSDT-HACK.aml the last, so it will be: SSDT.aml, SSDT-0.aml, SSDT-1.aml, SSDT-2.aml, SSDT-3.aml, SSDT-7.aml, SSDT-HACK.aml). You can do this with PlistEdit Pro or Xcode by yourself (check Clover Wiki for how-to). Anyway, I've prepared config_OK.plist with all these changes and more patches. Paste it in EFI/CLOVER/ and rename it to config.plist to continue with post-installation.

 

I would like to avoid adding patched ACPI files transforming my DSDT patch to the new hotpach method (thanks Rehabman!), adding code to SSDT-HACK and adding DSDT/patches to Clover if necessary but is waaaay out of my league. Any help achieving this will be appreciated.

 

NOTE: DSDT only needs Battery CC2 Patch for now. SSDT files only need names to be balanced, so any rename we are doing with Clover in ACPI/DSDT/Patches need to be do it as well in all SSDT (GFX0 to IGPU; B0D3 to HDAU…)

 

If you did it all well, you should have battery status working.

 

Audio/Sound can be achieved installing VoodooHDA. You will be able to use the internal microphone and speakers, so Siri will work. Airplay audio works too. HDMI needs work.

 

A better choice would be to patch our codec and use AppleHDA, HDMI audio seem to work better this way and might help to fix sleep/wake. I’ve attached a dump from my Realtek ALC286 and my Intel Haswell HDMI if somebody want to help with this matter.

 

 

CLONING TO INTERNAL DRIVE

 

Now that you have an almost fully working hackintosh, you probably want to clone it to your internal SSD. For that, just follow these steps:

 

- Boot into Windows, and shrink your C: partition using Disk Management.

- Format new volume to FAT32 and give it a name (you can use MacDrive to format to HFS+J)

- Boot using your USB installer, open Disk Utility and format your new internal partition to HFS+J (if you didn’t do it before using MacDrive). If you are prompted with an error, try it again. If error persists, try next step.

- Clone your current installation selecting as source your SierraHD drive and destination your new internal partition.

 

After clone, you still needing to install Clover in your internal EFI partition, so boot again your Sierra installation using your USB and repeat steps in INSTALLING CLOVER IN USB INSTALLER…  You also need to place proper config.plist and your ACPI patched files, SSDT.aml and SSDT-HACK.aml in EFI/CLOVER/ACPI/patched. Note that your internal EFI partition could have no name, mine in fact shows as NO NAME in Finder

 

In order to boot your internal Clover installation, you might like to create an entry in your Windows Boot Manager. I use EasyUEFI for that. Just click on the Create a new entry icon, select Linux or other OS, and select the path to EFI/CLOVER/CLOVERX64.EFI. Give entry a name, for example macOS Sierra ;)

 

 

NOTES:

 

I still having some doubts about this guide. For example:

 

- Our graphics device 8086,0A2E is natively recognized but doesn’t show a name in DPCIManager, I don’t know if can be an issue.

- PCI Realtek Card Reader 10EC,5229 has no support.

- USB may need work to make wake from Power Button work properly. I’ve created an injector and disable EHC with SSDT-HACK.aml and it’s under 15 port limit. I did the same with a EHC injector and FakePCIID_XHCIMux.kext or USBInjectAll.kext and a SSDT-UIAC.aml. Same result, ports work, wake with Power Button doesn’t, some of them are lost when reboot after try to wake up from sleep (using Power Button)

- There are some errors with methods in EC0 that probably need work (GBTT, SMB0._STA)

- Good news!! Cintiq Mode works ;) Just plug your cable to your PC or Mac, put your Companion to sleep and it should wake as a plain Cintiq and recognized by your PC or Mac. When you unplug your video cable, you Companion come back with everything working. Enjoy :)

 

- I did another test and wake quite good but with black screen: go to sleep (no cable video plugged), plug video cable, this will make screen wake but remain black, unplug video cable, use screen sharing to access and change resolution or detect displays in SysPref to push the signal to your internal display.

 

 

TIPS AND EXTRAS

 

- If you want to install any software, you must enable the lost option inside Security and Privacy. Type this in Terminal:

sudo spctl —master-disable

- If you want to enable HiDPi resolutions, just copy DisplayVendorID-5c23 folder into ~/System/Library/Displays/Contents/Resources/Overrides and install RDM.

 

- If you need to rebuild caches, run this in Terminal:

sudo rm -r /System/Library/Caches/com.apple.kext.caches
sudo touch /System/Library/Extensions && sudo kextcache -u /

- Sometimes boot into safe mode is needed. Just add -x  to boot flags in Clover or push spacebar in Clover boot menu (this second option is not working for me right now, I don’t know why).

 

- To enable playing a power chime sound effect when battery charged is plugged, type this in Terminal:

defaults write com.apple.PowerChime ChimeOnAllHardware -bool true; open /System/Library/CoreServices/PowerChime.app &

- If you want to try the new TouchBar present in new MacBook Pro, you can give it a try! Go here and follow instructions :)

 

 

CONCLUSIONS AND THOUGHTS

 

The Cintiq Companion maybe is not a famous tablet because its mainly client target are professional artists than doesn’t have too much time to play with this hackintosh stuff, but it works very well in my opinion, better than Surface devices. Geekbench results is same than MacBook Pro with same CPU and LuxMark gives a result of more than 1600 for what I checked.

 

The only thing that it would need to be perfect, in my opinion, is to sleep and wake properly. We can do that just plugin the video cable and entering Cintiq Mode, unplug and wake but it would be nice to wake it with the Power Button. For those who could help, here you have some clues you may find helpful to solve it.

 

Sleep works, display goes off, fans go off and led starts blinking. But when wake (only with power button) display goes back but remains black for seconds and suddenly go off, fans keep running, led keep on without blinking, but can’t access using VNC or screen sharing. If you enable the power chime sound effect, you will hear it if you unplug and plug your battery charger.

The only way to come back is to force a restart by holding power button and next time you boot some devices are missing (WiFi and some USB). Restarting one more time makes all devices work again.

 

Since I have no idea of binary patching, programming or ACPI concepts, it was very hard for me to get all this together. I’m probably doing something wrong or there’s a better way to make things work, so if you have any idea or suggestion, don’t hesitate to comment or ask. I'm doing this for two reasons, to share what I learned and to keep all the information together in one post.

 

And this is everything, folks! I hope this help you to install macOS Sierra in your Companion 2. Now that new model is out (but far away from my budget) you can find some affordable second hand units.

 

DOWNLOAD MY CC2_PACK

It contains:

  • ACPI folder, before and after patches (for those who want to check).
  • Battery CC2 Patch.
  • Kexts folder.
  • Official BIOS folder, in case you didn’t update your Companion 2 or disabled CSM support and can’t see BIOS menu.
  • SSDT Files folder, containing SSDT-HACK.dsl and SSDT.aml for i5-4258U PM.
  • APPS folder: Clover Configurator 2, DPCIManager, PlistEdit Pro, Kext Wizard, MaciASL, IORegistryExplorer.
  • EXTRAS folder: Brightness app (slider control in menu bar), Intel Power Gadget, iStat Pro widget, AppleIntelInfo.kext (for checking CPU PM).
  • HiDPi: DisplayVendorID-5c23 folder and RDM-2.2.pkg
  • codec_dump_ALC286.txt and codec_dump_HDMI.text for someone to may help patching AppleHDA.

 

I want to give a HUGE thanks to all the people that are involved in making this possible, from developers to testers (Piker, Rehabman, the-darkvoid, Slice, Allan... I don't know, I'm still learning who you are, people, you are a lot so don't be offended if I didn't mention you, please ^_^). And sorry if there's some grammar mistakes or something, it's my first guide in english.

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Amazing what you did mate, thanks a lot, I read your topic with a lot of attention, as well as the other one on the Cintiq, where your name occured many times !

I'm considering buying next week a second hand cintiq companion 2 with i7, 512Go SSD, 16Go RAM and intel Iris 6100. 

 

The thing is that there is a broadwell processor inside, from what i understood, it gets a bit tricky to deal with it. Anyway i will give a try. To make illustration and work for 2D animation, I prefer working with OSX. 

 

By the way, do you know if there is a chance that I can run El capitan or High Sierra with it instead of Yosemite ?

 

Thanks again for the great work you manage to do !

 

Cheers.

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The AppleALC audio approach (section E.3.1) bases on AppleALC.kext v1.2.6 and Lilu.kext v1.2.3 and could be implemented thanks to the extensive efforts and brilliant work of @vit9696 and @apfelnico.  2.) The VoodooHDA audio approach (section E.3.2) bases on the VoodooHDA.kext v2.9.0d10 and VoodooHDA.prefPane v1.2. 3.) Finally, @toleda's cloverALC audio approach (section E.3.3) bases on the realtekALC.kext v2.8 and on an additional pathing of the native vanilla AppleHDA.kext in the /S/L/E/ directory of the System Disk and has been successfully implemented thanks to the instructions and help of @Ramalama. The correct HDMI/DP digital Audio PCI implementation will be detailed in Section E.9) of this guide in line with the HDEF and GPU PCI device implementation.   The ASUS Prime X299 Deluxe on-board Bluetooth is natively supported and also Bluetooth Audio works OoB, however due to the non-functionality of the ASUS Prime X299 Deluxe on-board Wifi Module, I also use the Bluetooth 4.0 module of the OSX WIFI PCIe Adapter, which in line with its natively supported Wifi-module also provides native Airdrop, native Handoff and native Continuity as well as keyboard support in BIOS/UEFI and Clover Boot Loader. A full-featured alternative and more budget friendly BT/WIFI solution is the ABWB 802,11 AC WI-FI + Bluetooth 4.0 PCI-Express (PCI-E) BCM94360CD Combo PCIe Adapter of Flughafen Computer especially for our friends in Europe (thanks to @DSM2 for providing this information).   Thanks to the SmallTree-Intel-211-AT-PCIe-GBE.kext, also the Intel I211_AT Gigabit on-board LAN controller of the ASUS Prime X299 Deluxe is now correctly implemented and fully functional, in addition to the anyway natively implemented and of course also fully operational Intel I219-V Gigabyte on-board LAN controller of the Asus Prime X299 Deluxe (see Section E.8 of my guide).   In May 2018, @mm2margeret pointed me even to a fully working 10GBit Lan Solution (thanks to@mikeboss, @d5aquep and @Mieze) based on the ASUS XG-C100C 10-Gigabit Ethernet PCIe x4 Adapter. The latter adapter employs the same Aquantia AQC107 chip like the iMac Pro. How to successfully implement and run the ASUS XG-C100C is detailed in Sections E.8.2.1) and E.9.9). In addition, I also successfully implemented and tested the Intel X540-T1 single port 10GBit LAN PCIe Adapter after some Ubuntu modding of it's EEPROM to be compatible with the Small-Tree 10GB macOS 10.13 driver (see Sections E.8.2.2 and E.9.9 ). I now however use this latter adapter in my X99 rig. The Small-Tree P2EI0G-2T 2-Port 10GB LAN PCIe Adapter constitutes my actual 10GBit LAN implementation, working OoB with the Small-Tree 10GB macOS 10.13 driver. The 10Gbit NIC connects with a NetGear ProSave XS508M 8-port 10GBit switch, which further connects with a QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port that harbours 4x 12 TB Seagate IronWolf in RAID 0 configuration (optimised for read/write speed). Let me express my gratitude to @gxsolace at this place for providing me with 1x Intel X540-T1, 1x Small-tree P2EI0G-2T and 4x 12 TB Seagate IronWolf hardware. You are just awesome!   Excellent news concerning CPU Power Management: ASUS, MSI and ASROCK mainboards allow now for manually unlocking the MSR 0xE2 BIOS Register along their X299 mainboard series. The MSR 0xE2 BIOS Register of all Gigabyte mainboards is anyway unlocked by factory default. The manual unlocking of BIOS 1301 for the ASUS Prime Deluxe however still causes issues with respect to sleep/wake functionality and Skylake-X TSC. Therefore we have to enable the MSR lock in the BIOS settings but patch in advance the 1301 BIOS firmware by means of 3 patches provided by @interferenc. By this we achieve fully native HWP (Intel SpeedShift Technology) CPU Power Management for all Skylake-X processors on all mainboards with unlocked MSR 0xE2 BIOS Register, resulting in absolutely brilliant and top-end CPU performance (see Section E.1). With all unpatched mainboards we witness however some TSC desynchronisation of the Skylake-X threads at boot and wake from S3. Until further microcode updates are performed by the mainboard manufacturers, we therefore have to use the TSCAdjustRest.kext provided by @interferenc in this case.   Outstanding historical Skylake-X/X299 iMac pro Benchmark Scores finally also depict the excellent overall build and and system performance:     Geekbench i9-7980XE (4.8GHz) CPU Benchmark:  Multi-Core Sore: 65.348 Single-Core Sore: 5.910  
      Cinebench i9-7980XE (4.8GHz) CPU Benchmark: 4.618 CB  
      Geekbench Gigabyte Nvidia GeForce GTX 1080 Ti WaterForce WB 11GB Xtreme Edition OpenGL and Metal2 Benchmark:  OpenGL Sore: 229.965 Metal 2 Sore:  242.393   See Sections F.1) and F.2) for further details.   All Skylake-X Systems harbouring a mainboard with unlocked MSR 0xE2 BIOS Register now also posses fully native forced and automated Sleep/Wake Functionality not only thanks too a fully developed SSDT implementation and respective ACPI replacements.    Good new also for all users of C422 and XEON-W System. This guide seems also fully compatible with your systems     Before starting with all detailed instructions, please find a Table of Content that provides an overview of the individual topics addressed within this guide:   --------------------------------------------------------------------------------   Table of Contents   A.) Hardware Overview Details about the build configuration that states the baseline of this guide.   B.) Mainboard BIOS B1.) ASUS BIOS Firmware Patching B2.) ASUS BIOS Configuration B3.) Gigabyte BIOS Configuration   C.) Important General Note/Advice and Error Prevention Hardware and System Configuration recommendations. Make sure you've read all of this before complaining that something does not work.   D.) iMac Pro macOS 10.13 High Sierra System Setup This chapter includes a general guideline how to perform the initial setup of your iMac Pro with macOS High Sierra 10.13.5 (17F77). Note that the macOS High Sierra 10.13.5 (17F77) full package installer apparently can be only successfully downloaded on non-iMacPro systems. For iMacPro systems, there we provide a sophisticated workaround that bases on pristine sources from Apple. D.1) iMac Pro EFI-Folder Preparation D.2) iMac Pro macOS High Sierra 10.13.5 (17F77) Installer Package Creation D.3) iMac Pro macOS High Sierra 10.13.5 (17F77) USB Flash Drive Installer Creation D.4) iMac Pro macOS High Sierra 10.13.5 (17F77) Clean Install on Skylake-X/X299 D.5) Direct iMac Pro conversions of a functional Skylake-X/X299 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation D.6) iMac Pro macOS High Sierra Build Update Procedure   E.) Post Installation Process E.1) HWP (Intel SpeedShift Technology) CPU Power Management Configuration E.2) Graphics Configuration General ATI and Nvidia GPU advices including a detailed guideline for Nvidia Web Driver Installation and Black Screen Prevention E.3) Audio Configuration Use only one of the following, where E.3.1 is recommended by the author. E.3.1.) AppleALC Audio Implementation E.3.2) VoodooHDA Audio Implementation E.3.3) cloverALC Audio Implementation E.4) USB Configuration including some initial benchmarks E.5) ASUS Prime X299 Deluxe Thunderbolt EX3 PCIe Add-On Implementation E.6) NVMe compatibility E.7.) SSD/NVMe TRIM Support Extend the life of your SSD and maintained its normal speed E.8) Gbit and 10-Gbit Ethernet Implementations E.8.1) ASUS Prime X299 Deluxe on-board Gbit Ethernet Functionality E.8.2) 10-Gbit LAN Implementations E.8.2.1) ASUS XG-C100C Aquantia AQC107 10-Gbit NIC E.8.2.2) Intel X540-T1 10-Gbit NIC E.8.2.3) Small-Tree P2EI0G-2T 10-Gbit NIC E.8.2.4) NetGear ProSave XS508M 8-port 10-Gbit Switch E.8.2.5) QNAP TS-431X2 Quad-core 4-Bay NAS tower E.8.2.6) 10-GBit Ethernet Optimisation E.9) ASUS Prime X299 Deluxe PCI Device Implementation E.9.1) ACPI DSDT Replacement Implementation E.9.2) SSDT-X299-iMacPro.aml PCI Implementation E.9.2.1) - HDEF - onboard PCI Audio Controller PCI Implementation E.9.2.2) - GFX0, HDAU - Nvidia Graphics Card and HDMI/DP Audio PCI implementation E.9.2.3) - PMCR - onboard Power Management Controller (PMC) PCI Implementation E.9.2.4) - USBX - fixing XHCI USB Power errors during Boot E.9.2.5) - XHCI - onboard Extended Host Controller Interface (XHCI) PCI Implementation E.9.2.6) - XHC2,3,4 - ASMedia ASM3142 USB 3.1 Controller PCI Implementation E.9.2.7) - ANS1, ANS2 - Apple NVMe Controller PCI Implementation E.9.2.8) - SAT1 - Intel AHCI SATA Controller PCI Implementation E.9.2.9) XGBE - 10GBit NIC Implementation E.9.2.10) - ETH0/ETH1 - onboard LAN Controller PCI Implementation E.9.2.11) - ARPT - OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI Implementation E.9.2.12) - DTGP Method E.9.2.13) - Debugging Sleep Issues E.9.3)  SSDT-X299-TB3-iMacPro-KGP.aml PCI Implementation E.10) System Overview CPU Cosmetics E.11) iMac Pro Boot Splash Screen Cosmetics E.12) iMac Pro Desktop Background cosmetics E.13) Native Display Brightness Control / Native NightShift Functionality for Monitors with DCC/IC Support E.14) Logic-X and Audio Studio Software Functionality E.15) iStatMenus Hardware Monitoring   F.) Benchmarking F.1) Sylake-X Intel I9-7980XE CPU Benchmarking F.2) Gigabyte AORUS GTX 1080 Ti Waterforce EB 11GB Extreme Edition Benchmarking   G.) Summary and Conclusion   --------------------------------------------------------------------------------  
      Now enjoy and have have fun with the detailed guidelines below. Many thanks to [USER=956262]@paulotex[/USER] for committing the efforts in providing the Table of Contents detailed above.
       
      A.)  Hardware Overview
       
       
       
      Mainboard: Asus Prime X299 Deluxe [380€]
      CPU: i9-7980XE (18 core, 4.4Ghz) [1.900€] RAM Memory: Tridentz DDR-4 3200 Mhz 128GB (8x16GB) Kit (F4-3200C14Q2-128GTZSW) [1.400€] GPU: Gigabyte Aorus GTX 1080 Ti Waterforce WB Extreme Edition 11GB [900€] System Disks: EVO 960 NVMe M.2 1TB (system disk macOS High Sierra 10.13.3) [450€] ; EVO 960 NVMe M.2 1TB (system disk macOS Sierra 10.12.6 Sierra) [450€] Power Supply: Corsair AX1500i [450€] Monitor: LG 38UC99-W 38" curved 21:9 Ultra Wide QHD+ IPS Display (3840 pix x 1600 pix) [1.350€] WebCam: Logitech C930e [80€] Mouse: Apple Magic Mouse 2 [75€] Keyboard: Apple Magic Keyboard Wireless [99€] Bluetooth + Wifi: PC/HACKINTOSH - APPLE BROADCOM BCM94360CD - 802.11 A/B/G/N/AC + BLUETOOTH 4.0 [129€] Internal USB2.0 HUB: NZXT AC-IUSBH-M1T [20€] Case: Thermaltake Core X71 Tempered Glass Edition Full Tower Chassis [140€]   10Gbit Ethernet components: - 1x ASUS XG-C100C AQC107 PCIe x4 10GBit LAN Adapter (for testing purposes) - 1x Intel X540-T1 single port 10GBit LAN PCIe Adapter (for testing purposes, now installed in my X99 rig) - 1x Small-Tree P2EI0G-2T 2-Port 10GBit LAN PCIe Adapter (now default configuration) - 1x NetGear ProSave XS508M 8-port 10GBit switch - 1x QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port and 4x 12 TB Seagate IronWolf in RAID 0 configuration.   Let me express once more my gratitude to @gxsolace at this place for providing me with 1x Intel X540-T1, 1x Small-tree P2EI0G-2T and 4x 12 TB Seagate IronWolf hardware.   CPU/GPU Cooling: Water Cooling main components: - 1x EK-FB ASUS Prime X299 RGB Monoblock - Nickel [117€] - 1x EK-CoolStream PE 360 (Triple, 39 mm, Roof) [80€] - 1x EK-CoolStream Ce 280 (Dual, 45mm, Front) [90€] - 2x EK-CoolStream XE 360 (Triple, 60 mm, Cellar) [220€] - 1x XSPC Twin D5 Dual Bay Reservoir/Pump Combo [209€] - 15x Thermaltake Riing 12 High Static Pressure LED Radiator Fan (120mm) [210€] - 5x Thermaltake Riing 14 High Static Pressure LED Radiator Fan (140mm) [100€] - 3x Phantek PMW Fan Hub (up to 12 fans or 30W power consumption) [17€] - 1x Alphacool Eisflügel Flow Indicator Black G1/4 IG [16€] - 1x Phobya Temperatur Sensor G1/4 + C/F Display [22€]    
      -----------
      Total: 8904€
      -----------
      Compared with:
       
      B.) Mainboard BIOS
      Please find below instructions for the Asus X299 Prime Deluxe BIOS firmware patching (Section B.1), a summary of my actual Asus X299 Prime Deluxe BIOS settings (Section B.2), and some actual BIOS settings for the Gigabyte Designare EX settings (Section B.3).
       
      B1.) ASUS BIOS Firmware Patching
        On a real Mac with native OSX XCPM power management, the MSR 0xE2 register is unlocked and therefore writeable. However, on ASUS mobos this register was usually read only for ages.  When the kernel tried to write to this locked register, it caused a kernel panic. This panic could happen very early in the boot process, with the result that the system freezes or reboots during the boot process. We could circumvent the MSR 0xE2 register write with a dedicated KernelToPatch entry in the config.plist, namely "xcpm_core_scope_msrs © Pike R. Alpha" and by enabling the "KernelPM" in the config.plist in Section "Kernel and Kext Patches" of the Clover Configurator.   Within the ASUS Prime X299 Deluxe BIOS firmware 1301, ASUS now allows upon my user request for the first time to manually unlock the MSR 0xE2 register within the most recent BIOS settings. The manual unlock along the the BIOS settings of BIOS 1301 for the ASUS Prime Deluxe however still causes issues with respect to sleep/wake functionality and Skylake-X TSC. Therefore we have to enable the MSR lock in the BIOS and patch the latter firmware in advance.   Thanks to recent modifications in CodeRush's Longsoft UEFIPatch distributions and thanks to three sophisticated MSR 0xE2 Register patches provided by [USER=1295997]@interferenc[/USER] (partly former work of CodeRush, Pike Alpha and Adrian_dsl), we are able to successfully patch any ASUS X299 mainboard BIOS distribution and unlock the MSR 0xE2 register. The patched ASUS mainboard BIOS firmware finally can be uploaded to the specific ASUS X299 mainboard by means of the ASUS EZ BIOS Flashback Procedure. This makes the "xcpm_core_scope_msrs © Pike R. Alpha" KernelToPatch entry obsolete and allows full native read/write MSR 0xE2 register access by the OSX kernel.   MSI and ASRock mainboards successfully allow the manual unlock of the MSR 0xE2 BIOS Register. The MSR 0xE2 BIOS Register of all Gigabyte mainboards is anyway unlocked by factory default. On all unpatched mainboards, yet we however witness some TSC desynchronisation of the Skylake-X threads at boot and wake from S3. Until further microcode updates are performed by the mainboard manufacturers, we therefore have to use in this case the TSCAdjustRest.kext provided by @inteferenc (see error prevention 7.) in Section C.) of this guide).   By this we achieve fully native HWP (Intel SpeedShift Technology) CPU Power Management for all Skylake-X processors on all mainboards with unlocked MSR 0xE2 BIOS Register, resulting in absolutely brilliant and top-end CPU performance (see Section E.1).   The individual steps for the ASUS X299 BIOS Patching are detailed below:   1.) Installation of the BREW distribution:   a.) Open a terminal and change to "bash" shell. bash  
      b.) Now enter the following "bash" terminal command and follow the standard BREW installation instructions: /usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)  
      2.) After the successful installation of the BREW distribution, we have to implement the QT5 distribution, again by using a "bash" terminal shell. Just enter the following "bash" terminal commands: brew install qt5  
      brew link qt5 --force  
      3.) After successfully implementing BREW and QT5, we can now download the most actual CodeRush UEFIPatch distribution from Github to our home directory with the following terminal command: git clone https://github.com/LongSoft/UEFITool  
      Now we have to change to ~/UEFITool/UEFIPatch/ cd ~/UEFITool/UEFIPatch/  
      and execute the following "bash" commands: qmake uefipatch.pro make  
      Now we have the executable UEFIPatch distribution.   4.) Create a UEFIPatch-Folder on your Desktop mkdir ~/Desktop/UEFIPatch/  
      5.) Copy the previously compiled UEFI patch distribution to your new Desktop cp ~/UEFITool/UEFIPatch/UEFIPatch ~/Desktop/UEFIPatch/  
      6.) Download the most recent BIOS Firmware file from ASUS. For the ASUS Prime X299 Deluxe follow THIS LINK   7.) Copy the most recent ASUS BIOS Firmware file to your UEFIPatch-Folder on your Desktop, e.g. cp ~/Downloads/PRIME-X299-DELUXE-ASUS-1301.CAP ~/Desktop/UEFIPatch/  
      8.) Download patches.txt provided by @interferenc  and copy the file to your ~/Desktop/UEFIPatch/ Folder. cp ~/Downloads/patches.txt ~/Desktop/UEFIPatch/  
      9.) Change to your UEFIPatch directory on the Desktop cd ~/Desktop/UEFIPatch/  
      You now have all required data in the ~/Desktop/UEFIPatch/ Folder, which basically are UEFIPatch, patches.txt and the most recent ASUS BIOS Firmware distribution for your particular ASUS X299 mainboard.   10.) To finally patch the most recent ASUS BIOS Firmware distribution for your particular ASUS X299 mainboard, enter the following terminal commands (this example is for the ASUS Prime X299 Deluxe mainboard): cd ~/Desktop/UEFIPatch/ ./UEFIpatch PRIME-X299-DELUXE-ASUS-1301.CAP  
      You will see the following terminal output during the patch procedure:
      parseImageFile: Aptio capsule signature may become invalid after image modifications parseFile: non-empty pad-file contents will be destroyed after volume modifications parseFile: non-empty pad-file contents will be destroyed after volume modifications patch: replaced 8 bytes at offset 4380h 81E10080000033C1 -> 9090909090909090 patch: replaced 8 bytes at offset 4380h 81E10080000033C1 -> 9090909090909090 patch: replaced 8 bytes at offset 2CBEEh 81E10080000033C1 -> 9090909090909090 patch: replaced 8 bytes at offset 2CBEEh 81E10080000033C1 -> 9090909090909090 patch: replaced 4 bytes at offset 298Fh 0FBAE80F -> 0FBAE00F Image patched  
      The resulting patched BIOS Firmware distribution file has the ending ".patched", e.g. for the ASUS Prime X299 Deluxe we obtain "PRIME-X299-DELUXE-ASUS-1102.CAP.patched".   11.) Now rename the patched BIOS Firmware distribution file in concordance with the ASUS EZ Flashback filename convention for your particular ASUS X299 mainboard. For the ASUS Prime X299 Deluxe, the modified BIOS Firmware distribution file must be named "X299D.CAP": mv ~/Desktop/UEFIPatch/PRIME-X299-DELUXE-ASUS-1301.CAP.patched ~/Desktop/UEFIPatch/X299D.CAP  
      Now copy the CAP-file with the correct ASUS EZ Flashback filename convention to a USB Drive with a FAT32 File System of your choice:
      cp ~/Desktop/UEFIPatch/X299D.CAP /Volumes/"YOUR_USB_DRIVE"/  
      and reboot.
        12.) On reboot, enter the BIOS Menu with F2, save your actual BIOS settings to your USB Drive (CMO.file) and shut down your system.   The most recent ASUS mainboard BIOS firmware can be uploaded to the specific ASUS X299 mainboard in many different ways. The ASUS EZ BIOS Flashback Procedure is one of several options. The individual steps for the latter procedure are detailed below:   13.) Connect the USB Drive to the USB-port assigned to the ASUS BIOS Flashback procedure (see your mainboard manual for further details)   Subsequently, press the EZ BIOS-Flashback button on your mainboard for three seconds until the EZ BIOS Flashback led starts blinking, indicating that the EZ BIOS Flashback procedure is in progress. Release the button and wait until the light turns off, indicating that the EZ BIOS Flashback procedure has completed.    
        14.) Boot your system, enter the BIOS Menu with F2 and restore your previously saved BIOS settings from your USB Drive (CMO.file). Save your BIOS settings and exit the BIOS with F7 and F10.   Now you completed the BIOS patching procedure and you should have an ASUS X299 mainboard with an unlocked MSR 0xE2 register.   To check that the latter is the case, enter the following terminal command after reboot:   bdmesg   The Clover boot log will show if the MSR 0xE2 register of your ASUS mainboard is unlocked.   If you are able to find something like the following information, you fully succeeded in unlocking your MSR 0xE2 register:   MSR 0xE2 before patch 00000402 MSR 0xCE 00070C2C_F3011A00 MSR 0x1B0 00000000   Alternatively, you can also check the status of your MSR 0xE2 register by means of the VoltageShift distribution.   Download the VoltageShift distribution by following THIS LINK.   Copy the voltageshift folder to your desktop   mv ~/Downloads/voltageshift ~/Desktop/  
      Enter the following terminal commands:
      cd ~/Desktop/voltageshift/ sudo chmod -R 755 VoltageShift.kext sudo chown -R root:wheel ~/Desktop/voltageshift/VoltageShift.kext ./voltageshift read 0xe2  
      With unlocked MSR 0xE2 register, the output should look like as follows:
      RDMSR e2 returns value 0x7e000003   0x7e000003 is the value we need for our Skylake-X processors:   This is from the latest kernel, the E2 value is in bold and backwards:   00a572c0: E200 0000 4C00 0000 0000 0000 0000 0000 ....L...........
      00a572d0: 0F04 0000 0000 0000 0500 001E 0000 0000 ................
      00a572e0: 0000 0000 0000 0000 0000 0000 0000 0000 ................

      00a572f0: E200 0000 9033 0000 0000 0000 0000 0000 .....3..........
      00a57300: 0F04 0000 0000 0000 0800 007E 0000 0000 ...........~....
      00a57310: 0000 0000 0000 0000 0000 0000 0000 0000 ................

      00a57320: E200 0000 0040 0000 0000 0000 0000 0000 .....@..........
      00a57330: 0F04 0000 0000 0000 0300 007E 0000 0000 ...........~....
      00a57340: 0000 0000 0000 0000 0000 0000 0000 0000 ................  
      Alternatively you can also check the MSR 0xE2 register status by means of Pike Alpha's AppleIntelInfo.kext. Note however that the latter kext is incompatible with the i9-7980XE! Users of the latter Skylake-X CPU should opt for either the "bdmesg" or "voltageshift" MSR 0xE2 register verification approach detailed above.   Here I link the already patched ASUS Prime X299 Deluxe 1301 BIOS firmware distribution X299D.CAP, which already includes the iMacPro Splash Screen image implemented by the procedure detailed in Section E.11).   
      B2.) ASUS BIOS Configuration
       
      Before applying the specific settings, please provide your ASUS X299 Prime Deluxe with the most actual BIOS firmware 1301.   After Updating System time and System Date, enable X.M.P for your DDR4 modules. Don't forget to enable the EZ XMP Switch previously to this step on your ASUS Mainboard! Subsequently switch form the easy to the advanced ASUS BIOS Setup mode by pressing F7.   I use all optimized BIOS settings (OoB, no OC yet) despite a few changes listed in detail below:   1.) /AI Tweaker/ a.) ASUS MultiCore Enhancement: Auto [optional "Disabled", see important notification below!] b.) AVX Instruction Core Ratio Negative Offset: "3" [optional "Auto", see important notification below!] c.) AVX-512 Instruction Core Ratio Negative Offset: "2" [optional "Auto", see important notification below!] d.) CPU Core Ratio: Sync All Cores [optional "Auto", see important notification below!] e.) CPU SVID Support: Enabled [fundamental for proper IPG CPU power consumption display] f.) DRAM Frequency: DDR4-3200MHz   2.) /Advanced/CPU Configuration/ a.) Hyper Threading [ALL]: Enabled b.) MSR Lock Control: Enabled    3.) /Advanced/CPU Configuration/CPU Power Management Configuration/ a.) Enhanced Intel Speed Step Technology (EIST): Enabled b.) Autonomous Core C-States: Enabled c.) Enhanced Halt State (C1E): Enabled d.) CPU C6 report: Enabled e.) Package C-State: C6(non retention) state f.) Intel SpeedShift Technology: Enabled   (crucial for native HWP Intel SpeedShift Technology CPU Power Management) g.) MFC Mode Override: OS Native   4.) /Advanced/Platform Misc Configuration/   a.) PCI Express Native Power Management: Disabled b.) PCH DMI ASPM: Disabled d.) ASPM: Disabled e.) DMI Link ASPM Control: Disabled f.)  PEG - ASMP: Disabled   5.) /Advanced/System Agent Configuration/ a.) Intel VT for Directed I/O (VT-d): Disabled (see VT-d notification below)   6.) /Boot/ a.) Fast Boot: Disabled b.) Above 4G Decoding: Off c.) Set your specific Boot Option Priorities   7.) /Boot/Boot Configuration a.) Boot Logo Display: Auto (important for E.11 - ASUS Boot Splash Screen Cosmetics) b.) Boot up NumLock State: Disabled c.) Setup Mode: Advanced   8.) /Boot/Compatibility Support Module/ a.) Launch CSM: Disabled   9.) /Boot/Secure Boot/ a.) OS Type: Other OS   With F7 and F10 you can save the modified BIOS settings.   Important Notes:   "ASUS MultiCore Enhancement": When set to "Auto", MCE  allows you to maximise the overclocking performance optimised by the ASUS core ratio settings. When disabled, MCE allows to set to default core ratio settings.   "CPU Core Ratio - Sync All Cores": Tremendous increase in CPU performance  can be achieved with the CPU Core Ratio set to "Sync All Cores". In case of i9-7980XE stock settings (max. turbo 4.4 Ghz), the Geekbench score difference is approx. 51.000 (disabled) compared to 58.000 (enabled)! Note however, that Sync All Cores should be used only in case of the availability of an excellent and extremely sophisticated water cooling system! Otherwise, CPU Core Ratio should be set to "Auto". Further note that with CPU Core Ratio set to "Sync All Cores", the AVX Instruction Core Ratio Negative Offset must be set to "3" and the AVX-512 Instruction Core Ratio Negative Offset must be set to "2". Without the correct core ratio offsets, your system might become unstable with CPU Core Ratio set to "Sync All Cores"!   VT-d Note: For compatibility with VM or parallels, VT-d can be also ENABLED... Verify however, in this case that in your config.plist the boot flag "dart=0"  is checked under Arguments in the "Boot" Section of Clover Configurator! However, it might well be that the "dart=0" boot flag is already obsolete.   Intel(R) Power Gadget (IPG) CPU Power Consumption note: for the proper display of the CPU Power Consumption in e.g. the Intel(R) Power Gadget it is absolutely mandatory to enable both /AI Tweaker/CPU SVID Support/.   CPU Core Voltage Correction for ASUS X299 mainboard users: The ASUS Skylake-X BIOS microcode implementation has improved considerably. Former issues with "/AI Tweaker/CPU Core Voltage/" set to "Auto", where the assigned CPU Core Voltages have been too high by far, have been totally removed.   Iterative manual approach to derive minimal  CPU Core Voltages:   This iterative approach detailed assumes the BIOS settings described in Section B1) - point 1) to 10), however by considering the following else optional settings:   i.) "ASUS MultiCore Enhancement" set to "Auto" ii.) "CPU Core Ratio" set to "Sync All Cores" iii.) "AVX Instruction Core Ratio Negative Offset" set to "3" iv.) "AVX-512 Instruction Core Ratio Negative Offset" set to "2"   1.) Boot into Windows and launch ASUS CPU-Z as well as Cinebench.   2.) Run Cinebench CPU benchmarks and watch the Core VID values in CPU-Z under CPU max.load conditions. These values will usually exceed 1.2V with "/AI Tweaker/CPU Core Voltage/" set to "Auto".   3.) To optimise the "/AI Tweaker/CPU Core Voltage/"  perform the following steps:   a.) Enter the BIOS, go to "/AI Tweaker/CPU Core Voltage/" and change from "Auto" to "Manual"   b.) Enter a slightly lower CPU Core Voltage Overrride (e.g. typically 0.01 V less) than originally observed with CPU-Z under Cinebench CPU benchmark max.load conditions in Windows, e.g. 1.190 V in the first iteration.   c.) Reboot into windows and check if the Cinebench CPU benchmark scores are still in the expected range by also controlling the respective Core VID values during the Cinebench CPU benchmark max. load conditions   d.) Repeat b.) and c.) until either your Cinebench CPU benchmarks scores start to significantly decrease or you start facing problems in booting your system.    Given my personal experience with the i9-7980XE, a CPU Core Voltage Override of 1.120 V was optimal for a stock 4.4 GHz stock turbo frequency. In case of OC, the minimal CPU Core Voltage easily exceeded 1.2 V.   Warning!    Before performing the CPU Core Voltage Override Value Optimisation Approach, save your actual BIOS settings to a USB Drive. If during the iterative approach you are not able to successfully boot your system, perform a CMOS reset and restore your BIOS settings from the USB Drive, by subsequently entering the last successful CPU Core Voltage Override value!   Too high voltages can severely damage your CPU! In any case, when performing OC, a sophisticated water block circuit is absolutely mandatory! Always watch also your CPU temps when performing the CPU Core Voltage Optimisation, which should not exceed 90 deg C under CPU max. load conditions!   Many thanks to @DSM2 for all his comments, valuable input, and proposed solutions.     B.3) Gigabyte BIOS Configuration   Please find below the BIOS settings for the Gigabyte Designare EX kindly provided by @jyavenard and @DSM2.   1.) /M.I.T/Advanced Frequency Settings/ a.) Extreme Memory Profile: (X.M.P): Profile1   2.) /M.I.T/Advanced Frequency Settings/Advanced CPU Core Settings   a.) Active Cores Control: Auto b.) Hyper-Threading Technology: Enabled c.) Intel Turbo Boost Max Technology 3.0 : Enabled d.)  Intel Speed Shift Technology : Enabled e.) Enhanced Multi-Core Performance: enabled/disabled (optional; consider warning in Section B.2) - ASUS BIOS Settings) f.) CPU Enhanced Halt (C1E): Enabled g.) C6/C7 State Support: Enabled h.) Package C State limit: C6 i.) CPU EIST Function: Enabled j.)  Energy Efficient Turbo : Disabled   3.) /M.I.T/Advanced Memory Settings/ a.) Extreme Memory Profile (X.M.P): Profile1   4.) /BIOS/ a.) Boot Numlock State: Disabled/Enabled (optional) b.) Security option: Setup c.) Full Screen Logo Show: Enbabled d.) Fast Boot: Disabled e.) CSM Support: Disabled   5.) /BIOS/Secure Boot/ a.) Secure Boot Enable: Disabled   6.) /Peripherals/USB Configuration/ a.) XHCI Hand-off: Enabled   7.) /Peripheral/Thunderbolt Configuration/ (Designare EX only) a.) Security Level : SL0 - No Security   8.) /Chipset/ a.) VT-d: Disabled/Enabled (optional, see VT-d notification in Section B.2) - ASUS BIOS settings)   9.) /Save& Exit/ a.) Save & Exit     C.) Important General Note/Advice and Error Prevention   Please note the following important General Note / Advice and Error Prevention, when setting up your Skylake-X/X299 System and implementing the latest macOS High Sierra distribution.   1.) The /EFI/Clover/drivers64UEFI/-directory of EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip contains by default AptioMemoryFix.efi thanks to @vit9696. Note that with Clover_v2.4k_r4392, AptioMemoryFix.efi has become an official Customization Option of Clover and can now be selected and therefore also just easily implemented in the frame of the Clover Boot Loader Installation.
       
      For native NVRAM implementation, Clover's RC Scripts have to be omitted during the clover boot loader installation. If already previously installed, remove Clover's RC Scripts from the /etc directory of your macOS USB Flash Drive Installer or System Disk:
      sudo rm -rf /etc/rc.boot.d sudo rm -rf /etc/rc.shutdown.d  
      Also the "slide" boot flag needs to be disabled.
       
      2.a.) Most ATI GPUs, e.g. RX Vega 64, RX Vega Frontier, RX 580, RX 560 are natively implemented.  Remaining HDMI/DP port errors, hot plug errors and flaws with multi-monitor or 5K display configurations can be fixed by means of VegaGraphicsFixup.kext, kindly provided by @jyavenard. Important comment for all Vega users with 4K monitors though:  when connecting e.g. the Vega Frontier with e.g. the LG 38UC99-W (WUHD, 3840 pix x 1600 pix) via one of the Display Ports (DPs), the screen resolution is fine under both Windows 10 and macOS High Sierra but is totally at odd during boot (VGA like boot screen resolution). @DSM2 reported similar issues with his true 4K display and with both the ASUS Prime X299 Deluxe and the Gigabyte Designare EX. Thus the VEGA DP 4K boot screen resolution issue is neither related with the fact that the LG 38UC99-W is a ultra-wide (3840x1600) and not a true UHD (3840x2160) monitor nor related to any likely apparent issue with the ASUS Prime X299 Deluxe firmware. It is definitely a Vega firmware problem in combination with 4K displays, as the DP 4K boot screen resolution issue is totally absent with my Nvidia GPU and the problem also does not only affect the ASUS Splash Screen but also spreads over the entire boot process until the login screen is reached (Windows and macOS). Splash Screen, Apple logo or verbose boot messages are not stretched but rather have VGA like resolution. Any fix of the AMD vBIOS would be highly appreciated. It is more than disappointing to witness such issues with 1000$ GPUs... Fortunately, the 4K boot screen issue is restricted to the Vega DP ports and likely due to the fact that the LG 38UC99-W only supports DP 1.2. Solution: Connect your Vega and your 4K display via the HDMI port and everything will work as expected.
       
      b.) Also Nvidia Kepler Graphics Cards are natively implemented. 
        c.) All Users with Maxwell and Pascal Nvidia Graphics Cards Users and SMBIOS MacPro1,1 can employ officially distributed Nvidia 10.13 Web Drivers for their Nvidia Pascal and Maxwell graphics cards! Upon my request from 7 January 2018, Nvidia officially released first WebDriver-387.10.10.10.25.105 for 10.13.2 (17C2120) and first WebDriver-387.10.10.10.25.106 for 10.13.2 SA (17C2205) - Supplemental Update on 11 January 2018. On 25 January 2018, Nvidia released a Web Driver 387.10.10.10.25.157 for 10.13.3 (17D2047), which worked flawless with Pascal GPUs (lagging issues have been reported for Maxwell GPUs). On 20 February 2018, Nvidia released a Web Diver 387.10.10.10.30.159 for 10.13.3 SA (17D2102). On 31 March 2018 and 18 April 2018, Nvidia also released Web Driver 387.10.10.10.30.103 and 387.10.10.10.30.106 for 10.13.4 (17E199). On 25 April 2018,  Web Driver 387.10.10.10.30.107 has been released for 10.13.4 SU (17E202). On 02 June 2018, finally we Driver 387.10.10.10.35.106 followed for 10.13.5. Since Web Driver 387.10.10.10.30.106 former lagging issues have been fully removed. 10.13.6 Public Beta 2 (17G39b) users can use WebDriver-78.10.10.10.35.106 after a simple patching procedure detailed in Section E.2)   For further details and error prevention see Section E.2).   3.) Avoid any MacOS assignments in KextToPatch and KernelToPatch entries implemented in the  "Kernel and Kext Patches" Section of the Clover Configurator. If subsequently in my Guide you still find MatchOS assignments in respective figures or text, just ignore all likely yet persistent MatchOS assignments. In the config.plist of the EFI-Folder contained in EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip, all MatchOS assignments have been definitely removed.   4.) If you have the Thunderbolt EX3 or Gigabyte Alpine Ridge PCIe extension card already successfully connected with your mainboard and properly implemented in your system, disconnect any Thunderbolt device during the macOS installation/upgrade procedure. However, if any Thunderbolt PCIe extension card has not been properly configured and implemented yet in your system, remove the card for the macOS Upgrade or Clean Install procedure.   5.) Note that on some systems it might be necessary to check the KernelPM Option in the "Kernel and Kext Patches Section" of the Clover Configurator to successfully boot the respective system. Note that in the config.plist of the EFI-Folder attached below, this option is unchecked, as it is not required in case of the ASUS Prime X299 Deluxe.   6.) The /EFI/Clover/drivers64UEFI/-directory of all former EFI-distributions contains a patched version of the actual apfs.efi. The actual apfs.efi can be obtained by following the respective guideline detailed below:   Right-click with your mouse on the "Install macOS High Sierra.app" and select "Show Package Contents" -> click with the mouse on "Contents" and subsequently on "Shared Support" -> double-click with the mouse on "BaseSystem.dmg" for mounting.   Go to "usr" -> "standalone" -> "i386". Drop the apfs.efi to your Desktop.   To patch the apfs.efi for non-verbose boot, follow THIS LINK. Credits to @PMheart and @ermac.   Note however, that the entire apsf.efi approach detailed above recently has become totally obsolete. Thanks to the ApfsSupportPkg developed by @acidenthera & Co. and thanks to it's recent implementation to Clover (thanks to @Slice, @Philip Petev & Co.) in form of ApsfDriverLoader.efi, there is no further need of the former apsf.efi in the /EFI/Clover/drivers64UEFI/ directory.       The actual Clover distribution package including the ApsfDriverLoader.efi can by build by means of the Build_Clover.command available on Gitub. Since Version 4.8.8, the latter script also can be used with 10.14 and Xcode 10 +Xcode 10 Command Line Tools thanks to @vector sigma. By adding  export PATH="/usr/local/bin:/usr/bin:/bin:/usr/sbin:/sbin" && buildclover to the script,     the latter also can be used in case of Brew, QT5, UEFITool or MacPorts implementations like Latex, X11, gcc, etc. not yet fully compatible with 10.14 Mojave. Again thanks to @vector sigma for also providing/enabling this trick/possibility .    7.) To avoid Skylake-X thread TSC desynchronisation errors during boot and wake from S3, likely induced by yet erroneous Skylake-X BIOS microcode implementations, we need to use TSCAdjustReset.kext provided by @interferenc in the /EFI/CLOVER/kexts/Other/ directory of both USB Flash Drive and System Disk.    All ASUS Prime X299 Deluxe users with patched BIOS firmware 1301 can skip point 7.), as the applied patches of @interferenc also resolve all Skylake-X TSC desynchronisation errors during boot and wake from S3.   To access TSCAdjustRest.kext, download primarily its source distribution from Github with the following terminal command: git clone https://github.com/interferenc/TSCAdjustReset  
      Subsequently copy the TSCAdjustRest source distribution to your Desktop using the following terminal command:
      mv /TSCAdjustReset ~/Desktop  
      Now change in the terminal to the TSCAdjustReset source distribution on your Desktop with the following terminal command:
      cd ~/Desktop/TSCAdjustReset/  
      Now compile the source distribution with Xcode by using the following terminal command:
      xcodebuild   After successful compilation, you will find the TSCAdjustRest.kext in ~/Desktop/TSCAdjustReset/build/Release/   Please note that the TSCAdjustRest.kext by default is configured for a 8-core CPU (16 threads) like the i7-7820X. To adopt the kext for Skylake-X processers with more or less cores than 8 cores, apply the following approach:   a.) Right-click with the mouse on the TSCAdjustRest.kext file and select "Show Packet Contents".   b.) Double-click with the mouse on /contents/ . After a right-click on the "Info.plist" file, select "Open with /Other". Select the TextEdit.app and edit the "Info.plist" file.   c.) Use the "find"-function of TextEdit.app and search for the term "IOCPUNumber"   d.) Note that the adequate IOCPUNumber for your particular Skylake-X processor is the number of its threads -1, by always keeping in mind that the number of it's threads is always 2x the number of it's cores.   Thus in case of the 8 core i7-7820X, the IOCPUNumber is 15 (16 threads - 1).   <key>IOCPUNumber</key> <integer>15</integer>   By following this methodology, the correct IOCPUNumber for the 10-core i9-7900X would be 19 (20 threads -1).   <key>IOCPUNumber</key> <integer>19</integer>   and the IOCPUNumber for the 18-core i9-7980XE would result in 35 (36 threads -1).   <key>IOCPUNumber</key> <integer>35</integer>   e.) After adopting the IOCPUNumber for your particular Skylake-X processor, save the info.plist file and copy the modified TSCAdjustRest.kext to the /EFI/CLOVER/kexts/Other/ - directories of both USB Flash Drive Installer and System Disk and you are save and all done!     8.) Already during the first Beta Versions of macOS 10.13 High Sierra, Apple forced the beta users to use the new Apple file system APFS in case of a Clean Install/update of MacOS High Sierra 10.13. Also within macOS High Sierra 10.13.5 (17F77) this is the case.  Most APSF incompatibilities with available system related software apparently have been already removed. All recent versions  of Carbon Copy Cloner (CCC) support the direct cloning of APFS system disks and provide the previously missing option for APFS system backups. Until Boot-Loader Distribution Clover_v2.4k_r4210, it was also impossible to install the Clover Boot-Loader in the EFI-Partition of an APFS System Disk by means of the Clover Boot-Loader Installer Package (the Clover Boot-Loader files had to be added manually). However, all recent Clover Boot-Loader Distributions work absolutely flawless with APFS System Disks.   In any case, with @Brumbear's UnSolid.kext in the /EFI/Clover/kexts/Other/ directory, OSX is forced to remain with the HFS+ file format when installing or updating to the most recent macOS 10.13 distribution.    Note that there is no way to convert an APFS disk back to HFS+ without the loss of all data, but one can easily reformat an APFS formatted disk to HFS+ under OSX by using either Apple's Disk Utility App or "diskutil" commands. All you need to do is to previously unmount the APFS volume before erasing it with a journaled HFS+ file system and a GRUB Partition Table (GTP). If you want to maintain the disk's content, perform a backup before erasing the disk with a HFS+ format.   The application of Apple's Disk utility is straight forward. The  "diskutil" equivalent is detailed below:   In the Terminal app, type: diskutil list   In the output which you can read by scrolling back, you will find all internal disks named /dev/disk0, /dev/disk1, depending upon how many physical disks are present in your system.   Make a note of the disk identifier for the disk you intend to format (you can eliminate risk by removing all disks but the intended target).   In the Terminal app, type: diskutil unmount /dev/diskX  
      where diskX is a place holder for the disk to be unmounted.   Now delete the APFS container of diskX: diskutil apfs deleteContainer /dev/diskX  
      Subsequently, you can erase the entire disk with HFS+ and a GPT by typing the following terminal command: diskutil partitionDisk /dev/diskX 1 GPT jhfs+ "iMacPro" R   where /dev/diskX is again a place holder for disk to be erased and iMacPro would be the label for the single partition created. The remaining 1 GPT jhfs+ and R arguments tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and using the entire disk, respectively.   Alternatively one can also use the following terminal command: diskutil partitionDisk /dev/diskX GPT JHFS+ iMacPro 0b  
      where /dev/diskX is again a place holder for disk to be erased and iMacPro is again the label for the disk partition created. The GPT HFFS+ and 0b arguments again tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and covering the entire disk, respectively.   In the Terminal app, type now: diskutil mount /dev/diskX   where diskX is again a place holder for the disk to be remounted.   Note, that by means of the "diskutil approach", brand new unformatted or not compatibly formatted system NVMe, SSD and HDD system drives can be also directly formatted within the macOS Clean Install procedure. When presented with the initial install screen where you are presented options to Restore From Backup or Install, select Terminal from the Utilities menu bar item;   The "diskutil" terminal approach is also able to convert a HFS+ macOS High Sierra 10.13 System Disk to APFS. To do so enter the following terminal command: diskutil apfs convert /dev/diskX   where diskX is again a place holder for the HFS+ disk to be converted to APFS. The same procedure again can also be directly performed by means of Apple's Disk Utility.   If you opt for an APFS System Disk implementation, please note that all other disks on your system also should be formatted with APFS. On systems with APFS disks and non-APFS disks, the boot duration will increase, as apsf.efi will perform a fsck check of non-AFPS disks (like HFS+ or Fat32) during boot. However, dual boot APFS Systems with an NTFS Windows System Disk are not effected by the apsf.efi issue, as OSX does not know how to properly deal with NTFS.   9.) All ASUS Prime X299 Deluxe users, who enabled the second LAN controller in the ASUS Prime X299 Deluxe BIOS, are advised to download, unzip and copy the SmallTree-Intel-211-AT-PCIe-GBE.kext to the EFI-Folders of both USB Flash Drive Installer and 10.13 System Disk, or to disable the second LAN port in the BIOS during the MacOS Installation.   10.) Lilu and Lilu Plugin distribution remarks:   To access, download and compile most actual but not yet officially released Lilu and Lilu plugin distributions, follow these links:   a.) Lilu Source distribution b.) AppleALC Source Distribution c.) NvidiaGraphicsFixup d.) Whatevergreen   To successfully compile the AppleALC, NvidiaGraphicsFixup and Whatevergreen source code distributions with Xcode 9.3 under macOS High Sierra 10.13.4 SU (17E202), download, unzip and copy the respective actual Lilu DEBUG distribution to the AppleALC, NvidiaGraphicsFixup and Whatevergreen source code distribution directories. To compile the respective Lilu, AppleALC, and NvidiaGraphicsFixup source code distributions just execute the terminal command "xcodebuild" after changing to the respective source code distribution with the "cd" terminal command. The resulting compiled kexts can be always found in the respective /build/Release/ sub-directories of the respective source code distribution directories.   Further details to the topic can be accessed by following THIS LINK.   11.) To clearly get kernel panic images with a call trace in case of kernel panics, I implemented (checked) boot flags "debug=0x100" and "keepsyms=1" in the config.plist of EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip in the "Boot" Section of Clover Configurator under "Arguments".   12.) Note that in the current EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip distributions, I also removed CsmVideoDxe-64.efi from /EFI/CLOVER/drivers64UEFI, as the latter file is only required for proper Legacy screen resolution purposes with CSM enabled, which is definitely not  our case.   13.) All Gigabite mainboard users need to add the "npci=0x2000" boot flag to their config.plist by checking the latter in Section "Boot" of Clover Configurator under "Arguments".    
      D.) iMac Pro macOS 10.13 High Sierra System Setup   Below, one finds a detailed description for the Clean Install of macOS High Sierra 10.13.5 (17F77) - special iMacPro build (D.4). This also includes the iMacPro EFI-Folder Preparation (D.1) as well as the macOS High Sierra 10.13.5 (17F77) Installer Package (D.2) and macOS macOS High Sierra 10.13.5 (17F77) USB Flash Drive Installer Creation (D.3). One also finds instructions for a direct iMac Pro conversion of a functional Skylake-X/X299 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation (D.5), as well as for the subsequent iMac Pro macOS High Sierra Update Procedure.   D.1) iMac Pro EFI-Folder Preparation   In order to successfully boot a macOS USB Flash Drive Installer or System Disk on a Hackintosh system, both drives must be equipped with an EFI-Folder in their EFI partitions. In this Section we will prepare a fully equipped EFI-Folder with SMBIOS iMacPro1,1 System definition.   1.) Download and unzip EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip and copy the therein contained EFI-Folder to your Desktop.   2.) Open the config.plist in /EFI/Clover/ with the latest version of Clover Configurator (>/= v.4.60.0), proceed to the "SMBIOS" Section and complete the SMBIOS iMacPro1,1 Serial Number, Board Serial Number and SMUUID entries. These details are mandatory to successfully run iMessage and FaceTime on your iMac Pro System. Note that all other iMacPro1,1 SMBIOS Details  are already implemented in the config.plist of EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip.   Press several times the "Generate New" Button next to serial number text field.   Open a terminal, enter repeatedly the command "uuidgen", and copy the output value to the SMUUID field in the "SMBIOS" Section of the Clover Configurator.   Users of mainboards with locked MSR Register (disabled MSR OSX Kernel write access) have to enable the xcpm_pkg_scope_msrs © Pike R. Alpha Kernel patch in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator.   Enable "PluginType" in your config.plist under SSDT/Generate Options/ in Section ACPI of Clover Configurator for a fully working XCPM implementation. Note that by this, Pike Alpha's former ssdt.aml XCPM implementation becomes totally obsolete.   Finally save the modified config.plist.   3.) Users of unpatched mainboards have to copy the appropriate TSCAdjustRest.kext, which has been modified in error prevention C.7), to the /EFI/CLOVER/kexts/Other/ directory of the EFI-Folder.   You know have a fully equipped EFI-Folder for subsequent implementations as detailed below.   D.2) iMac Pro macOS High Sierra 10.13.5 (17F77) Installer Package Creation    If you are not able to successfully download the macOS High Sierra 10.13.5 (17F77) full package installer (5.22 GB) from the Appstore, follow the individual steps detailed below:   1.) Open a terminal and create a "091-86775" directory on your Desktop. Subsequently change to the newly created directory. All this can be done with the following terminal commands: mkdir ~/Desktop/091-86775/ cd ~/Desktop/091-86775/  
      2.) Download the following files from the Apple server (public links) to your ~/Desktop/091-86775/ directory by a copy & paste of the following terminal commands: curl https://swdist.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/091-86775.English.dist -o 091-86775.English.dist curl https://swdist.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/RecoveryHDMetaDmg.pkm -o RecoveryHDMetaDmg.pkm curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/RecoveryHDMetaDmg.pkg -o RecoveryHDMetaDmg.pkg curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/OSInstall.mpkg -o OSInstall.mpkg curl https://swdist.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/InstallAssistantAuto.pkm -o InstallAssistantAuto.pkm curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/InstallAssistantAuto.pkg -o InstallAssistantAuto.pkg curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/BaseSystem.dmg -o BaseSystem.dmg curl https://swdist.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/InstallESDDmg.pkm -o InstallESDDmg.pkm curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/InstallESDDmg.pkg -o InstallESDDmg.pkg curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/BaseSystem.chunklist -o BaseSystem.chunklist curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/InstallESDDmg.chunklist -o InstallESDDmg.chunklist curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/InstallInfo.plist -o InstallInfo.plist curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/AppleDiagnostics.chunklist -o AppleDiagnostics.chunklist curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/AppleDiagnostics.dmg -o AppleDiagnostics.dmg  
      The full list of package files can be found within the following catalog URL, searching for key "1fn3s8c48wk0u34dyujciitmn0nx3ul3dc":   https://swscan.apple.com/content/catalogs/others/index-10.13-10.12-10.11-10.10-10.9-mountainlion-lion-snowleopard-leopard.merged-1.sucatalog.gz     3.) Create the installer.pkg on your Desktop with the following terminal command: cd .. productbuild --distribution ./091-86775/091-86775.English.dist --package-path ./091-86775/ installer.pkg  
      4.) Create the "Install MacOS High Sierra.app" in the /Applications folder of your System Disk with the following terminal command: sudo /usr/sbin/installer -pkg installer.pkg -target /  
      In case that you receive an error message, ignore the latter and proceed with 5.)   5.) Now add the following files to your "Install High Sierra.app" with the following terminal commands: sudo cp ./091-86775/InstallESDDmg.pkg /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/InstallESD.dmg sudo cp ./091-86775/AppleDiagnostics.dmg /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/ sudo cp ./091-86775/AppleDiagnostics.chunklist /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/ sudo cp ./091-86775/BaseSystem.dmg /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/ sudo cp ./091-86775/BaseSystem.chunklist /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/  
      Verify your "Install High Sierra.app" for completeness. You should now have a complete macOS High Sierra 10.13.5 (17F77) Installer package in your /Applications Folder.
        The entire iMac Pro macOS Installer Package Creation Approach detailed above has been verified and approved by Motbod and is fully in line with the actual board rules.   Many thanks to @macandrea for his substantial and extensive contributions. He even now automatised the entire "Install High Sierra.app" creation procedure detailed above within one single script:    createInstaller.sh will automatically create on any MacOS System the "Install High Sierra.app" for macOS High Sierra 10.13.5 (17F77) in the /Applications folder.   Just download und unzip createInstaller.sh.zip and run the following terminal commands: cd ~/Downloads chmod +x createInstaller.sh ./createInstaller.sh  
        Absolutely brilliant, gorgeous and genius job man!     D.3) iMac Pro macOS High Sierra 10.13.5 (17F77) USB Flash Drive Installer Creation    Follow the individual steps detailed below to successfully create a bootable iMac Pro macOS High Sierra macOS High Sierra 10.13.5 (17F77) USB Flash Drive Installer.   1.) Format a USB Flash Drive of your choice (source, named USB) with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on your iMac Pro macOS USB Flash Drive Installer.   2.) With the macOS High Sierra 10.13.5 (17F77) Installer Package in your /Application Folder,  connect your USB Flash Drive (named USB) and run the following terminal command:     sudo /Applications/Install\ macOS\ High\ Sierra.app/Contents/Resources/createinstallmedia --volume /Volumes/USB --applicationpath /Applications/Install\ macOS\ High\ Sierra.app --nointeraction     Alternatively, one can create the iMac Pro macOS USB Flash Drive Installer also by means of the Install Disk Creator.app.   3.) Yet we have to make our iMac Pro macOS USB Flash Drive Installer also bootable. This can be partly done by means of the following terminal commands: cd /Volumes/YOUR_USB_VOLUME mkdir .IABootFiles cd .IABootFiles cp /Volumes/YOUR_USB_VOLUME/System/Library/CoreServices/boot.efi .
      This is a tricky part where many people fail. Note that "YOUR_USB_VOLUME" is a place holder in the above commands for the name of your real USB Flash Drive. Before executing the above commands, replace "YOUR_USB_VOLUME" by the real name of your USB Flash Drive.   To make the entire thing idiot proofed, let me explain the entire procedure by means of some nice example once provided by @paulotex to some user:   If your USB is called "Super USB I Like It Very Much" then you have to use:   cd /Volumes/Super\ USB\ I\ Like\ It\ Very\ Much   Note the "\" before each space.   The entire procedure for the assumed USB Flash Drive with the above name convention would look like that (don't forgot the isolated dot "." at the end of the last copy (cp) command below): cd /Volumes/Super\ USB\ I\ Like\ It\ Very\ Much mkdir .IABootFiles cd  .IABootFiles cp /Volumes/Super\ USB\ I\ Like\ It\ Very\ Much/System/Library/CoreServices/boot.efi .  
      With the terminal command: ls boot.efi  
      you can subsequently verify that boot.efi is there where it should be.   If you mistake at this point, your USB Flash Drive Installer will not be bootable and the USB Flash Drive macOS Installer partition will be simply invisible in the Clover Boot Menu!   4.) For successfully booting your iMac Pro macOS USB Flash Drive Installer, the latter must however also contain a valid EFI- Folder with an SMBIOS iMacPro1,1 system definition. Thus, copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition of your iMac Pro macOS USB Flash Drive Installer.   You now have a fully functional and bootable iMac Pro macOS High Sierra 10.13.5 (17F77) USB Flash Drive Installer.   Many thanks to @macandrea for his substantial and extensive contributions.     D.4) iMac Pro macOS High Sierra 10.13.5 (17F77) Clean Install on Skylake-X/X299   Follow the individual steps detailed below to successfully setup macOS High Sierra 10.13.5 (17F77)  on a virgin system drive of your choice (NVMe, SSD or HDD).   1.) In order to perform a clean install of macOS High Sierra 10.13.5 (17F77), prepare a virgin NVMe, SDD or HDD destination drive for the iMac Pro macOS installation by formatting the drive with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on the drive.   2.) Copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition.   3.) Now connect the Destination Drive to your Hackintosh System and boot the latter with the plugged iMac Pro macOS High Sierra 10.13.5 (17F77) USB Flash Drive Installer, your created in Section D.2)   4.) While booting your system, press the F8 button to enter the BIOS boot menu. Select to boot from your iMac Pro macOS USB Flash Drive Installer.   5.) Subsequently, click on the USB Flash Drive Installer Icon in the clover boot menu to boot the respective macOS Installer partition on your iMac Pro macOS USB Flash Drive Installer   6.) After successful boot, pass the individual steps of the macOS high Sierra 10.13 installation menu and finally select the destination drive of your macOS High Sierra 10.13 Installation, which should be logically the system disk you successfully configured above. In the next step, the Installer will create a macOS High Sierra 10.13 Installer Partition on the system disk and subsequently reboot your system.   7.) During system reboot, just press again the F8 button to enter the BIOS boot menu. Select again to boot from your USB Flash Drive. In contrary to 6.), click this time on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS High Sierra 10.13 Installer Partition on your system disk.   8.) After successful boot, you will enter now the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 34 minutes.   9.) After another reboot, press again the F8 button to enter the BIOS boot menu. Select to boot with your System Disk EFI-folder. Click on the "MacOS High Sierra" icon in the clover boot screen to boot the updated macOS High Sierra 10.13 partition on your system disk.   10.) After successful boot you will enter again the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 18 minutes. After successfully registration at iCloud at the end of the macOS installation, you now have your first iMac Pro macOS High Sierra 10.13.5 (17F77) build.   Proceed with Section D.6) - iMac Pro macOS High Sierra Build Updates (if necessary) or E.) - Post Installation Process.     D.5) Direct iMac Pro conversions of a functional Skylake-X/X299 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation   1.) Replace the EFI-Folder of your System Disk by the EFI-Folder you created in Section D.1)   2.) Copy /System/Library/CoreServices/PlatformSupport.plist to your Desktop, add BoardID "Mac-7BA5B2D9E42DDD94" under SupportedBoardIDs by means of Xcode as suggested by user Griven from the German Hackintosh-Forum and copy back the modified PlatformSupport.plist to System/Library/CoreServices/.   3.) If not already in your /Applications folder after performing Section D.2), copy the iMac Pro macOS Installer Package ("Install High Sierra.app") to your /Applications folder. Alternatively to D.2) and the macOS Full Package Installer, it is also sufficient to just download the original unmodified macOS High Sierra 10.13.5 (17F77) BaseSystem.dmg distribution from the Apple Server to your Desktop with the following terminal commands: cd ~/Desktop/ curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/BaseSystem.dmg -o BaseSystem.dmg  
      4.) Double click on the "Install High Sierra.app" in the /Applications Folder to start the macOS High Sierra 10.13.5 (17F77) installation. Alternatively, double click on the BaseSystem.dmg to mount the macOS installer and double click on the therein contained  "Install macOS High Sierra.app" to start the macOS High Sierra 10.13.5 (17F77) installation.   5.) After reboot, click on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS High Sierra 10.13 Installer Partition on your system disk.   6.) After successful boot, you will enter now the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 43 minutes.   7.) After another reboot, click on the "MacOS High Sierra" icon in the clover boot screen to boot the updated macOS High Sierra 10.13 partition on your system disk.   8.) After successful boot you will enter again the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 18 minutes. After successfully registration at iCloud at the end of the macOS installation, you now have your first iMac Pro macOS High Sierra 10.13.5 (17F77) build.   Proceed with Section D.6) - iMac Pro macOS High Sierra Build Updates (if necessary) or Section E.) - Post Installation Process.     D.6) iMac Pro macOS High Sierra Update Procedure   After the successful clean install or conversion you will be able to update your iMac Pro macOS High Sierra 10.13.5 (17F77) build to macOS High Sierra 10.13.6 Public Beta 2 (17G39b) directly via the Appstore. For macOS beta builds it is recommended to clone your macOS High Sierra System Disk with Carbon Copy Cloner (CCC) to a test drive and to update to the Public Beta on the latter.   Also any other future macOS High Sierra Update can be directly performed via the Appstore.  
      E.) Post Installation Process
       
      E.1) HWP (Intel SpeedShift Technology) CPU Power Management Configuration
       
      On Skylake-X/X299 Systems with unlocked mainboard BIOS MSR 0xE2 BIOS register and SMBIOS iMacPro1,1 we gain fully native HWP (IntelSpeedShift) Power Management after disabling the last remaining XCPM KernelToPatch entry "xcpm_core_scope_msrs" in Section "Kernel and Kext Patches" of Clover Configurator, which by default is still implemented but disabled in the config.plist of the distributed EFI-Folder EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip.
       
      Users with locked mainboard BIOS MSR 0xE2 register, still have to use the "xcpm_core_scope_msrs" XCPM KernelToPatch entry to successfully boot their systems. Otherwise the OSX Kernel will write to that BIOS register and cause KP at boot! 
        HWP is a way for the processor itself to manage the power consumption, with minor input from OSX on what it thinks it needs. In contrary, XCPM is the OSX power management part. It directly controls older hardware like Broadwell-E/EP or Haswell-E/EP and enables HWP on newer hardware like Skylake-X. It also sets some HWP variables, like the desired frequency at the maximum.   XCPM is enabled by default.    XCPM is enabled by default.   For it's complete configuration, XCPM still requires the CPU "plugin-type" injection to properly load the required XCPM frequency vectors from the iMacPro.plist, which can be directly achieved within the config.plist by checking "PluginType" in Section "ACPI" of Clover Configurator.    
      How to verify a working xcpm configuration?   a.) Typically the command "sysctl machdep.xcpm.mode" reveals 1, which means that XCPM is active.   b.) Verify that in the IORegistryExplorer you have now under CP00@0 the following entry:   Property: Type: Value: plugin-type Number 0x1  
      c.) Also verify with the terminal command:
      kextstat|grep -y x86plat  
      that the "X86PlatformPlugin.kext" is now loaded. If the command returns something like
      112 1 0xffffff7f822bc000 0x17000 0x17000 com.apple.driver.X86PlatformPlugin (1.0.0) FD88AF70-3E2C-3935-99E4-C48669EC274B <111 19 18 13 11 7 6 5 4 3 1> 146 1 0xffffff7f822d3000 0x7000 0x7000 com.apple.driver.X86PlatformShim (1.0.0) DCEA94A4-3547-3129-A888-E9D5C77B275E <112 111 13 7 4 3>  
      d.) Verify with the following terminal command:
      kextstat|grep -y appleintelcpu that you got rid of the Apple Intel CPU power management. If the result is empty you are fine.
       
      d.)  Verify the following terminal command:
      sysctl -n machdep.xcpm.vectors_loaded_count  
      If this command returns "1", the XCPM FrequencyVectors are properly loaded and you are all set.
       
      E.2) Graphics Configuration
       
       Most ATI GPUs, e.g. RX Vega 64, RX Vega Frontier, RX 580, RX 560 are natively implemented.  Remaining HDMI/DP port errors, hot plug errors and flaws with multi-monitor or 5K display configurations can be fixed by means of VegaGraphicsFixup.kext, kindly provided by @jyavenard. Important comment for all Vega users with 4K monitors though:  when connecting e.g. the Vega Frontier with e.g. the LG 38UC99-W (WUHD, 3840 pix x 1600 pix) via one of the Display Ports (DPs), the screen resolution is fine under both Windows 10 and macOS High Sierra but is totally at odd during boot (VGA like boot screen resolution). @DSM2 reported similar issues with his true 4K display and with both the ASUS Prime X299 Deluxe and the Gigabyte Designare EX. Thus the VEGA DP 4K boot screen resolution issue is neither related with the fact that the LG 38UC99-W is a ultra-wide (3840x1600) and not a true UHD (3840x2160) monitor nor related to any likely apparent issue with the ASUS Prime X299 Deluxe firmware. It is definitely a Vega firmware problem in combination with 4K displays, as the DP 4K boot screen resolution issue is totally absent with my Nvidia GPU and the problem also does not only affect the ASUS Splash Screen but also spreads over the entire boot process until the login screen is reached (Windows and macOS). Splash Screen, Apple logo or verbose boot messages are not stretched but rather have VGA like resolution. Any fix of the AMD vBIOS would be highly appreciated. It is more than disappointing to witness such issues with 1000$ GPUs... Fortunately, the 4K boot screen issue is restricted to the Vega DP ports and likely due to the fact that the LG 38UC99-W only supports DP 1.2. Solution: Connect your Vega and your 4K display via the HDMI port and everything will work as expected.
       
      Also Nvidia Kepler Graphics Cards are natively implemented. 
        All Users with Maxwell and Pascal Nvidia Graphics Cards Users and SMBIOS MacPro1,1 can employ officially distributed Nvidia 10.13 Web Drivers for their Nvidia Pascal and Maxwell graphics cards! Upon my request from 7 January 2018, Nvidia officially released first WebDriver-387.10.10.10.25.105 for 10.13.2 (17C2120) and first WebDriver-387.10.10.10.25.106 for 10.13.2 SA (17C2205) - Supplemental Update on 11 January 2018. On 25 January 2018, Nvidia released a Web Driver 387.10.10.10.25.157 for 10.13.3 (17D2047), which worked flawless with Pascal GPUs (lagging issues have been reported for Maxwell GPUs). On 20 February 2018, Nvidia released a Web Diver 387.10.10.10.30.159 for 10.13.3 SA (17D2102). On 31 March 2018 and 18 April 2018, Nvidia also released Web Driver 387.10.10.10.30.103 and 387.10.10.10.30.106 for 10.13.4 (17E199). On 25 April 2018,  Web Driver 387.10.10.10.30.107 has been released for 10.13.4 SU (17E202). On 02 June 2018, finally we Driver 387.10.10.10.35.106 followed for 10.13.5. Since Web Driver 387.10.10.10.30.106 former lagging issues have been fully removed. 10.13.6 Public Beta 2 (17G39b) users can use WebDriver-78.10.10.10.35.106 after a simple patching procedure detailed below   How to patch an Nvidia WebDriver:   Download the Nvidia WebDriver-Payload Repackager from InsanelyMac. Credits to Chris111 and Pavo.    The patch procedure is simple and fully described in the implemented Readme.txt and will reveal a Repackaged-WebDriver.pkg, which can be used for installing the patched Nvidia Web Driver Installation under macOS 10.13.5 Beta distributions.   Nvidia Web Driver Installation and Black Screen Prevention:   Apparently with SMBIOS iMacPro1,1, the Nvidia Black Screen Prevention has become obsolete. Thanks to @fabiosun from InsanelyMac for this finding. Thus, NvidiaGraphicsFixup.kext, subverting AppleMobileFileIntegrity banning the driver can be theoretically removed from the /EFI/CLOVER/kexts/Other/ directory of your macOS Flash Drive Installer and 10.13 System Disk. However, the most actual releases of NvidiaGraphicsFixup.kext v.1.2.7 and Lilu.kext v1.2.3 apparently help in fixing the Nvidia HDAU implementation and sporadic black screen issues while wake from sleep. Thus, the latter kext combination might still represent potential workarounds for few likely remaining system issues.     a.) Install the original or patched Nvidia 10.13 Web Driver Package.   b.) In case of the original Web Driver, just reboot as requested and you will already have a fully functional Web Driver.   c.) In case of the patched Web Driver, perform the following additional steps:   i.) Copy /L/E/ NVDAStartupWeb.kext to your Desktop.   ii.) Right-click on NVDAStartupWeb.kext and select show package content.   iii.) Change to "Contents" and edit the "Info.plist" with Xcode.   iv.) Go to IOKitPersonalities -> NVDAStartup -> change "NVDARequiredOS" from "17F77" to "17G39b", the corresponding build number of 10.13.6 Public Beta 2.   v.) Save the "Info.plist" file and copy the modified "NVDAStartupWeb.kext" to /L/E/ with root permission.   vi.) Open a terminal and enter the following commands:   sudo chmod -R 755 /Library/Extensions/NVDAStartupWeb.kext sudo chown -R root:wheel /Library/Extensions/NVDAStartupWeb.kext sudo touch /System/Library/Extensions && sudo kextcache -u / sudo touch /Library/Extensions && sudo kextcache -u /   vii.) Reboot.   viii.) The patched Web Driver will not be active yet. Therefore, open the Nvidia Driver Manager and select "Nvidia Web Driver".   ix.) Now reboot as requested and you will have a fully functional patched Web Driver under 10.13.6 Public Beta 2 (17G39b).     E.3) Audio Configuration:     Note that opposite to my previous EFI-Folder distributions, EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip does not contain any default audio configuration. You have to implement the audio approach of your choice during the Post Installation process! Please select between one out of three possible audio implementations detailed below. To avoid the loss of analogue onboard audio (S1220A in case of the ASUS Prime X299 Deluxe) on Wake from Sleep, please download, unzip and copy the latest CodecCommander.kext distribution of @Rehabman from gitbucket.org to the /EFI/Clover/kexts/Other directory in the EFI-Folder of your System Disk: https://bitbucket.org/RehabMan/os-x-eapd-codec-commander/downloads/.   E.3.1.) AppleALC Audio Implementation   The actual AppleALC audio implementation traces back to the extensive efforts and brilliant work @vit9696  and @apfelnico. This new AppleALC audio approach bases on AppleALC.kext v1.2.7, which further requires Lilu.kext v1.2.3 in the /EFI/CLOVER/kexts/Other/ directory of your System Disk.   Provided that you use the EFI-Folder contained in EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip, you need to open the config.plist in the /EFI/CLOVER/ directory of your System Disk with the Clover Configurator and add the CAVS -> HDEF DSDT replacement patch in Clover Configurator Section "ACPI" under "DSDT Patches".   Comment: Find*[Hex] Replace [Hex] CAVS -> HDEF 43415653 48444546   When implementing the SSDT in Section 9.2), we will perform the  CAVS -> HDEF ACPI replacement directly within the SSDT. We then have to remove again the CAVS -> HDEF ACPI replacement from the config.plist!   Note that opposite to the alternative VoodooHDA and CLoverALC approach detailed below, the AppleALC audio implementation requires an Audio ID in injection of "7" instead of "1". Implement the latter Audio ID in the config.plist of your System Disk under "Audio" and "Injection" in the Section "Devices" of the Clover Configurator.   The correct HDAU HDMI/DP digital Audio PCI device implementation will be detailed in Section E.9) in line with the HDEF and GPU PCI device implementation.   To remove the AppleALC Audio Approach Implementation perform the following steps:   1.) Remove AppleALC.kext v1.2.6  from the /EFI/CLOVER/kexts/Other/ directory of your System Disk.   2.) Disable in the config. plist the CAVS -> HDEF DSDT Replacement Patch in Clover Configurator Section "ACPI" under "DSDT Patches".   3.) Adopt the Audio ID Injection in your respective config.plist in Clover Configurator Section "Devices" for the alternative audio approach you intent to use.   4.) Reboot  
      E.3.2) VoodooHDA Audio Implementation  
       
      1.) Provided that you use the EFI-Folder contained in EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip, you need to open the config.plist in the /EFI/CLOVER/ directory of your System Disk with the Clover Configurator and add the CAVS -> HDEF DSDT Replacement Patch in Clover Configurator Section "ACPI" under "DSDT Patches".
      Comment Find*[HEX] Replace*[HEX] Rename CAVS to HDEF 43415653 48444546  
      When implementing the SSDT in Section 9.2), we will perform the  CAVS -> HDEF ACPI replacement directly within the SSDT. We then have to remove again the CAVS -> HDEF ACPI replacement from the config.plist!
       
      2.) Download, unzip and copy the VoodooHDA.kext v2.9.0d10 to your Desktop. Mouse Right-Click on VoodooHDA.kext -> select "Show Package Contents" -> click on "Contents" -> Right-Click on "Info.plist" -> "Open With" -> "Other" -> select "TextEdit.app"  
       
      3.) a.) In the TextEdit.app select in the menu "Edit" -> "Find" -> "Find..." -> search for  "IOPCIClassMatch" and replace
      <key>IOPCIClassMatch</key> <string>0x04020000&0xfffe0000</string> with
      <key>IOPCIPrimaryMatch</key> <string>0x43831002</string>   b.) Download, unzip and run the  attached at the end of this originating post/guide.   Search for HDEF and write down the "IOName"-entry under e.g. PC00@0/AppleACPIPCI/HDEF@1F,3 which can slightly deviate on mainboards different from the ASUS Prime X299 Deluxe.     
       
      The HDEF-IOName on the ASUS Prime X299 Deluxe is "pci8086,a2f0"   Concert the IOName as shown below in case of the HDEF-IOName of the ASUS Prime X299 Deluxe:   "0xa2f08086"   c.) Now replace in the "Info.plist" of "VoodooHDA.kext"   "0x43831002"   by   "0xa2f08086"   and save the "Info.plist".   d.) Copy the modified "VoodooHDA.kext" to the /EFI/Clover/kexts/Other/ - directory of your System Disk.   4.) Download, unzip and copy the VoodooHDA.prefPane v1.2 attached below to ~/Library/PreferencePanes/   5.) Note that the VoodooHDA audio approach requires an Audio ID in injection of "1". The corresponding modification of the config.plist has to be implemented by means of the Clover Configurator by modifying the respective entry in Section "Devices".   6.) Reboot   To remove the VoodooHDA audio implementation, perform the following steps:   1.)  Disable in the config. plist the CAVS -> HDEF DSDT Replacement Patch in Clover Configurator Section "ACPI" under "DSDT Patches".   2.) Remove VoodooHDA.kext  from the /EFI/CLOVER/kexts/Other/ directory of your System Disk.   3.) Remove VoodooHDA.prefPane from ~/Library/PreferencePanes/   4.) Adopt the Audio ID Injection in your config.plist in Section "Devices" of the Clover Configurator for the alternative audio approach you intent to use   5.) Reboot   E.3.3) cloverALC Audio Implementation  
      @Toldea's cloverALC audio approach has been implemented thanks to the respective advices and help of user @Ramalama. Note that in contrary to the AppleALC and VoodooHDA approaches, the cloverALC audio approach detailed below will patch the native vanilla AppleHDA.kext in the /S/L/E directory of your System Disk! This before implementing the cloverALC audio approach, backup your native vanilla AppleHDA.kext from the /S/L/E directory on your System Disk! You will have to reinstall the native vanilla AppleHDA.kext from the /S/L/E directory on your System Disk with the appropriate permissions during a removal of the cloverALC Audio Implementation! Thus you need a backup of the latter native vanilla kext in any case!      CloverALC audio approach installation:   1.) Provided that you use the EFI-Folder contained in EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip, you need to open the config.plist in the /EFI/CLOVER/ directory of your System Disk with the Clover Configurator and add the CAVS -> HDEF DSDT Replacement Patch in Clover Configurator Section "ACPI" under "DSDT Patches".   Comment Find*[Hex] Replace[Hex] Rename CAVS to HDEF 43415653 48444546 When implementing the SSDT in Section 9.2), we will perform the  CAVS -> HDEF ACPI replacement directly within the SSDT. We then have to remove again the CAVS -> HDEF ACPI replacement from the config.plist!
       
      2.) Change the Audio ID Injection in the config.plist on your System Disk in Section "Devices" under "Audio" and "Inject" to "1".  3.) Add the following cloverALC related KextToPatch entries to your config.plist on your System Disk in section "Kerneland Kext Patches" of Clover Configurator in the "KextsToPatch" listing:
      Name* Find*[Hex] Replace* [Hex] Comment AppleHDA 8a19d411 00000000 t1-10.12-AppleHDA/Realtek ALC... AppleHDA 8b19d411 2012ec10 t1-10.12-AppleHDA/RealtekALC1220 AppleHDA 786d6c2e 7a6c 7a6d6c2e 7a6c t1-AppleHDA/Resources/xml>zml   3.) Download, unzip and copy the realtekALC.kext v2.8  to the /EFI/CLOVER/kexts/Other/ directory on your System Disk   4.) Download and execute audio_cloverALC-130.sh, which will patch the native vanilla AppleHDA.kext in the /S/L/Edirectory of your System Disk   5.) Reboot     To remove the cloverALC audio implementation, perform the following steps:   1.) Remove realtekALC.kext from the /EFI/CLOVER/kexts/Other/ directory on your System Disk   2.) Remove all cloverALC related KextToPatch entries from the config.plist on your System Disk  in the "Kernel andKext Patches" section of Clover Configurator.   3.) Disable in the config. plist the CAVS -> HDEF DSDT Replacement Patch in Clover Configurator Section "ACPI" under"DSDT Patches".   4.) Delete the patched AppleHDA.kext in the /S/L/E/ Directory on your System Disk   5.) Reinstall the original vanilla AppleHDA.kext with the appropriate permission in the /S/L/E/ directory on yourSystem Disk using Kext Utility   6.) Adopt the Audio ID Injection in your config.plist in Section "Devices" of the Clover Configurator for the alternative audioapproach you intent to use   7.) Reboot     E.4) USB Configuration 
       
      Since 10.13 SU and with AppleIntelPCHPMC, Apple now implements IOPCIPrimaryMatchID "a2af8068" and AppleUSBXHCISPT on the ASUS Prime X299 Deluxe. All external and internal XHC USB 3.0 (USB 3.1 Gen 1 Type-A) and USB 2.0 (USB 2.0 Gen 1 Type-A) ports should work at expected data transfer rates on all X299 mainboards.  All external and internal USB 3.1 (USB 3.1 Gen 2 Type-A and Type-C) ports are anyway natively implemented on different controllers than XHC.   All ASUS Prime X299 Deluxe users, not content with the current OSX XHC USB implementation,  can download, unzip and use my board-specific XHC USB Kext KGP-iMacPro-XHCI.kext. All users of mainboards different from the ASUS Prime X299 Deluxe, can create their own board specific XHC USB kext by following my XHC USB Kext Creation guide line in the other forum.  
      Note that in addition one needs to implement the XHC USB port limit patch in the config.plist under "KextsToPatch"  in Section "Kernel and Kext Patches" of Clover Configurator, as else not all available XHC USB ports will be implemented.
       
      Name* Find*[Hex] Replace* [Hex] Comment AppleUSBXHCI 837d940f 0f839704 0000 837d941a 90909090 9090 10.13.4 USB Port Limit Patch Many thanks to @PMHeart from InsanelyMac for providing the respective XHC USB port limit patches. 
       
      USB 2.0 and USB 3.0 Benchmark Results  
          
       
      USB 3.1 Type-A and Type-C Benchmark Results  
          
       
      E.5) ASUS Prime X299 Deluxe Thunderbolt EX3 PCIe Add-On Implementation  
       
      For the successful implementation of the Thunderbolt EX3 PCIe Add-On Adapter, a fully working Dual Boot System with an UEFI Windows Implementation is unfortunately absolutely mandatory. You will not be able to configure your Thunderbolt EX3 PCIe Add-On Adapter in the mainboard BIOS, until the Adapter has been successfully recognised and initialised by the UEFI Windows System. Fortunately legal and official License Keys for the actual Windows 10 Pro distribution can be purchased with a little bit of temporal effort on Google for an actual price of 20 $ or even below! Thus, the installation of a dual boot system with Windows will require some additional temporal user effort but will not noticeably further affect the users's budget.   Please note that I especially emphasize the term UEFI, when speaking about the parallel Windows implementation. Don't use or perform a Legacy Implementation of Windows! In order to properly implement your Windows partition later-on in the Clover Bootloader and to comply with the actual Mainbaord-BIOS settings requirements, it is absolutely mandatory to run or perform an UEFI Windows implementation!   So if not already implemented, how to achieve a fully working UEFI Windows Implementation and Dual boot System with Windows?   1.) Important Note! For the implementation of the UEFI Windows Distribution disconnect all usually plugged macOSDrives from your rig! The Windows installer will implement a Windows Boot Loader! If you have any macOS Drive connected during installation, the latter Windows Boot Loader might overwrite and destroy your current Clover Boot Loader. This is the last thing you want! Thus for the windows installation just connect the destination drive for the installation and the Windows USB Flash Drive Installer your will create in the subsequent step below!   2.) This Tutorial explains in all necessary detail how to download an actual Windows 10 Creator distribution,  and how tosubsequently create a bootable USB Flash Drive Installer for a subsequent UEFI Windows 10 installation by means RUFUS! Don't put emphasis on alternative optional methods and always take care that you just follow the instructions for a successful subsequent UEFI Windows Installation!     
       
      3.) This Tutorial explains in all necessary detail how to properly perform the actual Windows 10 Pro Creator UEFIInstallation, subsequent to the a bootable Windows USB Flash Drive Installer realisation detailed in 2.) above. 
       
        
       
      4.) This Tutorial explains in all necessary detail, how to migrate/clone/backup your Windows 10 UEFI System Disk afterinstallation for future maintenance and safety.
       
       
       
      5.) After successfully performing the UEFI Windows 10 Pro Creator Implementation, you can reconnect your macOS driveto your rig. The newly created UEFI Windows 10 Pro Creator Partition will automatically appear as a further boot option in both BIOS Boot Option Menu (F8) and Clover Boot Menu! No additional or further actions or measurements have to be taken!
       
        
       
      6.) Once your Windows 10 Pro Creator Partition is fully operational, install all drivers and programs implemented on theASUS Prime X299 Series DVD attached to your mainboard. This will further allow you to properly adjust the desired AURA Mainboard Settings and offer many other  mainboard configuration options.
       
        
       
      7.) Now switch of your rig and start with the installation of the Thunderbolt EX3 PCIe Add-On Adapter   a.) I recommend to install the adapter in third PCIe Slot from the bottom which is PCIEX_3  

       
      b.)  For full TB hot plug functionality skip or remove the THB_C cable between the TBEX 3 and the respective mainboard connector!   8.) Reboot into windows and install the ASUS ThunderboltEX 3 DVD accompanying your ASUS Prime X299 Deluxe mainboard.  
        
       
      9.) Reboot and enter the Mainboard BIOS (F2)   a.) Go to /Advanced/ Thunderbolt(TM) Configuration/ and apply the following BIOS Settings detailed below: TBT Root por Selector PCIE16_3 Thunderbolt USB Support Enabled Thunderbolt Boot Support Enabled Wake From Thunderbolt(TM Devices) Off Thunderbolt(TM) PCIe Cache-line Size 128 GPIO3 Force Pwr On Wait time in ms after applying Force Pwr 200 Skip PCI OptionRom Enabled Security Level SL0-No Security Reserve mem per phy slot 32 Reserve P mem per phy slot 32 Reserve IO per phy slot 20 Delay before SX Exit 300 GPIO Filter Enabled Enable CLK REQ Disabled Enable ASPM Enabled Enable LTR Disabled Extra Bus Reserved 65 Reserved Memory 386 Memory Alignment 26 Reserved PMemory 960 PMemory Alignment 28 Reserved I/O 0 Alpine Ridge XHCI WA Disabled  
      b.) Verify in /Boot/ that Above 4G Decoding is Off
      Above 4G Decoding Off   10.) Shut down your rig, connect the Thunderbolt Device with the Thunderbolt EX3 Adaptor and boot   11.) You are done!  Your Thunderbolt EX3 PCIe Adapter and connected devices should be now fully implemented andfunctional.   12.) We will add TB XHC USB and TB Hot Plug functionality by means of the SSDT-X299-TB3-iMacPro-KGP.aml.zip described in Section E.9.3) of this guide.      Thunderbolt Benchmarks:    For the sake fo completeness and for testing the overall Thunderbolt Functionality and Performance, I benchmarked the the data rates of an external Thunderbolt Drive connected via Apple's Thunderbolt-3 to Thunderbolt-2 Adapter. As External Thunderbolt Drive, I once more used the Lacie Rugged Thunderbolt / USB Type-A and Type-C HDD.             E.6) NVMe compatibility    In contrary to macOS Sierra 10.12, in macOS High Sierra 10.13 there is native support of non-4Kn NVMe SSDs, like my Samsung EVO 960 M.2 NVME. All patches applied under macOS Sierra 10.12 are therefore obsolete. The native support of non-4Kn NVMe SSDs enables the unique opportunity to directly perform a clean-install of macOS High Sierra 10.13 on M.2 NVMEs like the Samsung EVO 960.     E.7.) SSD/NVMe TRIM Support    Macs only enable TRIM for Apple-provided solid-state drives they come with. If you upgrade a Mac with an aftermarket SSD/NVMe, the Mac won’t use TRIM with it. The same applies for SSDs/NVMes used by a Hackintosh. When an operating system uses TRIM with a solid-state drive, it sends a signal to the SSD/NVMe every time you delete a file. The SSD/NVMe knows that the file is deleted and it can erase the file’s data from its flash storage. With flash memory, it’s faster to write to empty memory — to write to full memory, the memory must first be erased and then written to. This causes your SSD/NVMe to slow down over time unless TRIM is enabled. TRIM ensures the physical NAND memory locations containing deleted files are erased before you need to write to them. The SSD/NVMe can then manage its available storage more intelligently..    Note that the config.plist in the EFI-folder of EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip, contains an SSD/NVMe "TRIM Enabler" KextsToPatch entry, which can be found in the " Kernel and Kext Patches" Section of the Clover Configurator.   Name* Find*[HEX] Replace*[HEX] Comment MatchOS IOAHCIBlockStorage 4150504c 45205353 4400 00000000 00000000 0000 Trim Enabler 10.12.x,10.13.x  
      With this KextToPatch entry, SSD/NVMe TRIM should be  fully enabled on your 10.13 System, see Apple's System Report below.
       
        
       
      For the sake of completeness please find below the Benchmark of connected NVMe and SDD Drives.
       
          
       
      E.8) Gbit and 10-Gbit Ethernet Implementations
       
      Section E.8.1) and and E.8.2.) below, describe in the necessary detail how to gain full Gbit and 10-Gbit LAN functionality on Skylake-X/X299 systems.
       
      E.8.1) ASUS Prime X299 Deluxe on-board Gbit Ethernet Functionality
       
      Thanks to the SmallTree-Intel-211-AT-PCIe-GBE.kext, also the Intel I211_AT Gigabit on-board LAN controller of the ASUS Prime X299 Deluxe will be correctly implemented and fully functional, in addition to the Intel I219-V Gigabyte on-board LAN controller of the ASUS Prime X299 Deluxe implemented by means of IntelMausiEthernet.kext (already part of my EFI-Folder distributions). Thus, both ethernet ports on the ASUS Prime X299 Deluxe should now be fully operational.
       
      Just download , unzip  and copy the SmallTree-Intel-211-AT-PCIe-GBE.kext to the /EFI/Clover/kexts/Other/, reboot and you should be done
       
      E.8.2) 10-GBit Lan Implementations ASUS Prime X299 Deluxe on-board Gbit Ethernet Functionality
       
      E.8.2.1) ASUS XG-C100C Aquantia AQC107 10-Gbit NIC   Starting with 10.13.2 there is native support for Aquantia based 10GBit network cards, which are implemented by means of a Apple Vanilla kext called "AppleEthernetAquantiaAqtion.kext", which is further part of "IONetworkingFamily.kext/Contents/PlugIns/" placed in  /System/Library/Extensions/ (credits to @mikeboss). First success with the ASUS XG-C100C under MacOS 10.13.3 has been reported by @d5aqoep. @Mieze finally came up with a AppleEthernetAquantiaAqtion KextPatch for the use of the ASUS XG-C100C also under 10.13.4 and and later macOS versions.   How to successfully implement the ASUS XG-C100C AQC107 PCIe x4 10GBit Ethernet Adapter:   1.) A temporal macOS High Sierra 10.13.3 (17D2047 in case of the iMac Pro) installation is absolutely mandatory at first place. Only within the latter macOS High Sierra build, the ASUS XG-C100C will receive the proper AQC107 Apple firmware to be recognised and fully implemented by OSX. The firmware update will be performed during system boot. Several boot intents might be necessary until the firmware update finally succeeds. Only subsequently, the ASUS XG-C100C will be natively implemented in macOS High Sierra 10.13.3 and fully functional.   2.) To finally use the ASUS XG-C100C with macOS builds >10.13.4 and finally also with 10.14, one has to implement the following AppleEthernetAquantiaAqtion KextPatch provided by @Mieze:     Name*                            Find*[HEX]         Replace*[HEX]      Comment AppleEthernetAquantiaAqtion      0F84C003 0000      90909090 9090      Aquantia patch ©Mieze  
      3.) The proper XGBE ASUS XG-C100C PCI SSDT implementation is detailed in Section E.9.2)   4.) Note that after the firmware update under macOS High Sierra 10.13.3, the ASUS XG-C100C will refuse the official Windows Lan drivers provided by ASUS and will only work with Apple's customised Aquantia64v2.0.015.0 boot camp drivers attached below.   E.8.2.2) Intel X540-T1 10-Gbit NIC   Thanks to some Ubuntu EEPROM modding, I also achieved the successful implementation of the Intel X540-T1 single port 10GB LAN PCIe Adapter by means of the Small-Tree 10GB macOS 10.13 driver.   Some additional notes to the EEPROM modding guideline provided by the above link.   1.) When creating your Ubuntu USB Flash Drive, use RUFUS 3.0 and select the GPT option to obtain a Ubuntu USB boot drive, fully compatible with your UEFI BIOS implementation!   2.) To install "net-tools", enter the following terminal command sudo apt install net-tools  
      3.) To install "ethtool" enter the following terminal command: sudo apt-get install ethtool  
        4.) Within the latest Ubuntu distributions, ETH0, ETH1, etc. have been replaced by some weird "enp" port-nomenclature, thus the command "ifconfig" would reveal something like the following:     My Intel X540-T1 was assigned to enp225s0.   5.) With the command "lspci -nn -vvv | grep Ethernet" you have to use in 6.) the Vendor/Device-ID entry highlighted by the green rectangle.     6.) By running the "sudo ethtool -e enp225s0 | less" command and eyeballing the offsets, be aware that the latter can be distributed over two lines:       You have to count from left to right 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f for each pair of digits for each offset.   Thus, the commands I had to run to mod the Intel X540-T1 EEPROM were: sudo ethtool -E enp225s0 magic 0x15288086 offset 0x48e value 0x0a sudo ethtool -E enp225s0 magic 0x15288086 offset 0x48f value 0x00  
      Note that the "magic" value implemented in this command has been taken from the "lspci -nn -vvv | grep Ethernet" command output, again encircled by a green rectangle:     The rest is as described in the EEPROM modding guideline linked above.   The proper Intel X540-T1 PCI SSDT implementation is detailed in Section E.9.2)   Actually, I am now currently using this adaptor in my X99 system configuration.   E.8.2.3) Small-Tree P2EI0G-2T 10-Gbit NIC   The Small-Tree P2EI0G-2T 2-Port 10GB LAN PCIe Adapter constitutes the actual base line in my X299 10Gbit LAN configuration. It works OoB with the Small-Tree 10GB macOS 10.13 driver.   The proper Small-Tree P2EI0G-2T PCI SSDT implementation is detailed in Section E.9.2)   E.8.2.4) NetGear ProSave XS508M 8-port 10-Gbit Switch   As already mentioned above, the NetGear ProSave XS508M 8-port 10GBit switch constitutes the turntable of my 10-GBit Ethernet Network. It further connects with a QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port.   E.8.2.5) QNAP TS-431X2 Quad-core 4-Bay NAS tower   The QNAP TS-431X2 Quad-core 4-Bay NAS tower finally harbours 4x 12 TB Seagate IronWolf drives in RAID 0 configuration (as I rather opt for read/write speed than redundancy).   E.8.2.6) 10-GBit Ethernet Optimisation   1.) Use SMB 3.0 instead of AFS for your Ethernet communication. 2.) Enable Jumbo Frames on your NAS and macOS network settings. 3.) The service order in your macOS network settings should have your 10-Gbit NIC at first position. 4.) You can turn off the SMB packet signing of the client and server in a secure network.   Incoming SMB Enter the following terminal commands: sudo -s
 echo "[default]" >> /etc/nsmb.conf 
echo "signing_required=no" >> /etc/nsmb.conf 
exit  
      Outgoing SMB:   Enter the following terminal commands: smbutil statshares -a sudo defaults write /Library/Preferences/SystemConfiguration/com.apple.smb.server SigningRequired 0  
      E.9) ASUS Prime X299 Deluxe PCI Device Implementation   In order to properly implement all PCI device drivers on his/her system and build, one needs adequate ACPI DSDT Replacements and a sophisticated SSDT. Both requirements have been originally successfully implemented for the ASUS Prime X299 Deluxe by our gorgeous @apfelnico with partial contributions of @TheOfficialGypsy. Many thanks for the extensive efforts and extremely fruitful and brilliant work! Subsequently, I adopted the ACPI DSDT Replacement Patches and SSDT in concordance with SMBIOS iMacPro1,1. The actual ACPI DSDT Replacements are part of the config.plist contained in EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip. I also link the SSDT-X299-iMacPro.aml and SSDT-X299-TB3-iMacPro-KGP.aml further developed with @apfelnico and @nmano .   Note that the ACPI DSDT Replacements, SSDT-X299-iMacPro.aml and SSDT-X299-TB3-iMacPro-KGP.aml can be build and PCIe slot population dependend and have to be verified and likely adopted or modified for all mainboards different from the ASUS Prime X299 Deluxe and builds or PCIe slot populations different from the one that constitutes the baseline of this guide.   For the ASUS Prime X299 Deluxe I will use in the following the PCIe Slot nomenclature depicted below:  
        
       
      The verification and likely adaptation/modification can be performed by the help of IORegistryExplorer.
       
      How to adopted or modify the ACPI DSDT Replacement Patches and SSDT-X299-iMacPro.aml is detailed in post  #225  by means of the OSXWIFI PCIe Adaptor implementation in PCIe Slot-3. I hope that by this specific example it rapidly becomes evident that the correct PCI Device implementation cannot be outlined for each individual "build-in" or "slot-specific" PCI device within this guide. The complexity and effort would just exceed by far all available capacities and indeed require the implementation of a separate guide and thread in addition. I therefore hope on your skills and flexibility to extend and apply the approach and methodology detailed above to any other "build-in" or "slot-specific" PCI device yet to be adopted or implemented.
        Important Note: It is strongly recommend to perform a stepwise PCI Device implementation by means of a minimalistic starter SSDT-X299-iMacPro.aml, which just contains the Definition Block and Device Implementation for one single specific device. Once this PCI device has been successfully implemented, other PCI Device definitions can be added to the SSDT-X299-iMacPro.aml. In case that subsequently the implementation of a specific PCI Device would be erroneous and fail, also all other already successfully implemented PCI devices would disappear from Section "PCI" of Apple's System report and the entire "PCI" Device implementation would fail. Thus a stepwise PCI device implementation/adaptation is highly recommended and sometimes deemed necessary!   Also keep always in mind to modify/adopt the ACPI replacements in your config.plist in parallel when ever necessary!   Note once more that the ACPI DSDT Replacement Patches and SSDT-X299-iMacPro.aml implementation detailed below requires SMBIOS iMacPro1,1.  
      E.9.1)  ACPI DSDT Replacement Implementation   All required ACPI DSDT Replacements are already implemented in the config.plist in the /EFI/CLOVER/ directory of the EFI-Folder contained in EFI-X299-10.13.5-Release-iMacPro1,1-160618.zip or are directly part of the SSDT-X299-iMacPro.aml and SSDT-X299-TB3-iMacPro-KGP.aml. In the config.plist, the ACPI DSDT Replacements are disabled by default, thus we will now open the config.plist in the /EFI/CLOVER/ directory of your 10.14 System Disk EFI-Folder with Clover Configurator and stepwise adopt (if necessary) and enable the different required DSDT replacement patches in Clover Configurator Section "ACPI" under "DSDT patches", by also discussing their respective function and impact.   a.) The PC00 -> PCI0 ACPI DSDT replacement patch has the main aim to achieve a SMBIOS iMacPro1,1specific PCI implementation. Note that under SMBIOS iMacPro1,1 all other PC0x definitions remain unchanged.   Please enable now the PC0x -> PCIx ACPI DSDT replacement patch. Comment:            Find*[Hex]     Replace [Hex] PC00 -> PCI0        50433030       50434930  
      b.) OSI -> XOSI, EC0_ -> EC__ and H_EC  -> EC__ are once more ACPI DSDT replacement patches to achieveconsistency with the SMBIOS iMacPro1,1 variable naming.   i.) XOSI functionality is required as explained by @RehabMan.   The ACPI code can use the_OSI method (implemented by the ACPI host) to check which Windows version is running. Most DSDT implementations will vary the USB configuration depending on the active Windows version. When running OS X, none of the DSDT _OSI("Windows <version>") checks will return "true" as there is only response from "Darwin". This issue can be solved by implementing the "OS Check Fix" family of DSDT patches in the SSDT. By DSDT patching we can simulate a certain version of Windows although running Darwin and we can obtain a system behaviour similar to a windows version specific environment.   ii.) On the Asus X299 Prime Deluxe and most likely on all other X299 mobos we have the EC0 and H_EC controllers,which have to be renamed to 'EC' for proper USB power management.  Thus once more investigate your mainboard specific IOREG entry and enable both EC0_ -> EC__ or and H_EC  -> EC__ DSDT Replacement Patches. Comment:             Find*[Hex]      Replace [Hex] OSI -> XOSI          5f4f5349        584f5349 EC0_ -> EC__         4543305f        45435f5f H_EC  -> EC__        485f4543        45435f5f  
      c.) The HEC1 -> IMEI and IDER->MEID ACPI DSDT Replacement patches are Intel Management Engine Interface relatedand are vital as MacOS requires the variable names "IMEI" and "MEID" to load the 'AppleIntelMEIDriver'. The latter functionality solves the 'iTunes/Apple Store Content Access Problem' which is discussed here.   Please enable now both ACPI DSDT Replacement patches independent from your mainboard. Comment:             Find*[Hex]       Replace [Hex] HEC1 -> IMEI         48454331         494d4549 IDER->MEID          49444552         4d454944  
      d.) The LPC0 -> LPCB ACPI DSDT Replacement Patch is AppleLPC and SMBus related and is applied for consistency withthe variable naming on a real Mac. Note that LPCB injects AppleLPC, which however is not required in the X299 environment. X299 Systems seem to have sleep problems with the SMBus properties injected. Thus, the LPCB functionality will be disabled within the SSDT-X299-iMacPro.aml.   Please enable now this ACPI DSDT replacement patch independent from your mainboard. Comment:             Find*[Hex]         Replace [Hex] LPC0 -> LPCB         4c504330           4c504342  
      e.) FPU_->MATH, TMR_->TIMR, PIC_->IPIC are all ACPI DSDT Replacement Patches for consistency with the variablenaming on a real Mac. The variables are however functionless on either our X299 boards or real Macs.   Please enable now all three ACPI DSDT Replacement Patches independent from your mainboard. Comment:             Find*[Hex]        Replace [Hex] FPU_ -> MATH         4650555f          4d415448 TMR_ -> TIMR         544d525f          54494d52 PIC_ -> IPIC         5049435f          49504943  
      f.) The SMBS._ADR -> XSBU.XADR Replacement frees SBUS two show up in IOREG. In principle we have two devices with the same address, one called SMBS and the other one called SBUS. SBUS will never show up in IOREG as long SMBS exists. But SBUS is exactly the variable we need in concordance with the IOREG from the iMacPro Dump.   Please enable now this ACPI DSDT replacement patch independent from your mainboard. Comment:                       Find*[Hex]                     Replace [Hex] SMBS._ADR -> XSBU.XADR         534d4253 085f4144 52           58534255 08584144 52  
      g.) The DSM -> XDSM DSDT replacement patch is vital for loading the SSDT-X299-iMacPro.aml, as all DSM methods used in theoriginal DSDT do have a not compatible structure totally different from the real Mac environment. Without any fix, all DSM methods would be simply ignored. Note that one single device can have only one DSM method, which can assign additional properties to the respective device.   Thus please enable the latter DSDT replacement patch completely independent from your mainboard! Comment:             Find*[Hex]         Replace [Hex] _DSM -> XDSM         5f44534d            5844534d  
      h.) The 56 CPxx -> PRxx replacements are i9-7980XE specific and result in a proper CPU core reordering as well as in a iMac Pro specific CPU core variable naming.   All i9-7980XE users can now enable all 56 CPxx -> PRxx replacements. All users of CPUs different from the i9-7980XE have to adopt/modify the 56 CPxx -> PRxx replacements in concordance with their original IOREG CPU core values. Comment:             Find*[Hex]        Replace [Hex] CP00 -> PR00         43503030          50523030 CP01 -> PR01         43503031          50523031 CP02 -> PR02         43503032          50523032 CP03 -> PR03         43503033          50523033 CP04 -> PR04         43503034          50523034 CP05 -> PR05         43503035          50523035 CP06 -> PR06         43503036          50523036 CP07 -> PR07         43503037          50523037 CP08 -> PR08         43503038          50523038 CP09 -> PR09         43503039          50523039 CP0E -> PR10         43503045          50523130 CP0F -> PR11         43503046          50523131 CP10 -> PR12         43503130          50523132 CP11 -> PR13         43503131          50523133 CP12 -> PR14         43503132          50523134 CP13 -> PR15         43503133          50523135 CP14 -> PR16         43503134          50523136 CP15 -> PR17         43503135          50523137 CP1C -> PR18         43503143          50523138 CP1D -> PR19         43503144          50523139 CP1E -> PR20         43503145          50523230 CP1F -> PR21         43503146          50523231 CP20 -> PR22         43503230          50523232 CP21 -> PR23         43503231          50523233 CP22 -> PR24         43503232          50523234 CP23 -> PR25         43503233          50523235 CP24 -> PR26         43503234          50523236 CP25 -> PR27         43503235          50523237 CP2A -> PR28         43503241          50523238 CP2B -> PR29         43503242          50523239 CP2C -> PR30         43503243          50523330 CP2D -> PR31         43503244          50523331 CP2E -> PR32         43503245          50523332 CP2F -> PR33         43503246          50523333 CP30 -> PR34         43503330          50523334 CP31 -> PR35         43503331          50523335 CP0A -> PR36         43503041          50523336 CP0B -> PR37         43503042          50523337 CP0C -> PR38         43503043          50523338 CP0D -> PR39         43503044          50523339 CP16 -> PR40         43503136          50523430 CP17 -> PR41         43503137          50523431 CP18 -> PR42         43503138          50523432 CP19 -> PR43         43503139          50523433 CP1A -> PR44         43503141          50523434 CP1B -> PR45         43503142          50523435 CP26 -> PR46         43503236          50523436 CP27 -> PR47         43503237          50523437 CP28 -> PR48         43503238          50523438 CP29 -> PR49         43503239          50523439 CP32 -> PR50         43503332          50523530 CP33 -> PR51         43503333          50523531 CP34 -> PR52         43503334          50523532 CP35 -> PR53         43503335          50523533 CP36 -> PR54         43503336          50523534 CP37 -> PR55         43503337          50523535  
      Resulting CPU Core Implementation:     E.9.2)  SSDT-X299-iMacPro.aml PCI Implementation     For the proper PCI device driver implementation (detailed in the Figure above), which is mostly directly related with the PCI device functionality, we now have to revise and likely adopt or modify the attached SSDT-X299-iMacPro.aml wit MaciASL to your specific build and system configuration with the help of IORegistryExplorer.   Note that for each device, the SSDT-X299-iMacPro.aml contains a DefinitionBlock entry and the underlying PCI device implementation. In case of necessary modifications/adaptations, don't forget to also modify/adapt the respective DefinitionBlock entries in concordance with your IOREG entries. The entire SSDT structure is module like. Each module can be independently added, changed or removed in dependence of your specific build, needs and requirements. A stepwise implementation of the individual PCI devices is recommended!   E.9.2.1) - HDEF - onboard PCI Audio Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0.CAVS, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0)     {         Scope (CAVS)         {             Name (_STA, Zero)  // _STA: Status         }         Device (HDEF)         {             Name (_ADR, 0x001F0003)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x16)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "model",                         Buffer (0x1C)                         {                             "Realtek ALC S1220A HD Audio"                         },                         "name",                         Buffer (0x27)                         {                             "Realtek ALC S1220A HD Audio Controller"                         },                         "hda-gfx",                         Buffer (0x0A)                         {                             "onboard-1"                         },                         "device_type",                         Buffer (0x14)                         {                             "HD-Audio-Controller"                         },                         "device-id",                         Buffer (0x04)                         {                              0xF0, 0xA2, 0x00, 0x00                         },                         "compatible",                         Buffer (0x0D)                         {                             "pci8086,0C0C"                         },                         "MaximumBootBeepVolume",                         Buffer (One)                         {                              0xEE                                        },                         "MaximumBootBeepVolumeAlt",                         Buffer (One)                         {                              0xEE                                        },                         "layout-id",                         Buffer (0x04)                         {                              0x07, 0x00, 0x00, 0x00                         },                         "PinConfigurations",                         Buffer (Zero) {}                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The HDEF PCI device implementation is valid for the ASUS Prime X299 Deluxe and likely for all other mainboards with the Realtek ALC S1220A Audio Controller chipset. It is a build-in device and does not have any slot specific dependency. Note the CAVS -> HDEF replacement directly performed within the SSDT!     E.9.2.2) - GFX0, HDAU - Nvidia Graphics Card and HDMI/DP Audio PCI implementation    DefintionBlock entry: External (_SB_.PC02.BR2A, DeviceObj)    // (from opcode) External (_SB_.PC02.BR2A.SL05, DeviceObj)    // (from opcode) External (_SB_.PC02.BR2A.PEGP, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (_SB.PC02.BR2A)     {         Scope (SL05)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (PEGP)         {             Name (_STA, Zero)  // _STA: Status         }         Device (GFX0)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x14)                     {                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "device-id",                         Buffer (0x04)                         {                              0x06, 0x1B, 0x00, 0x00                         },                         "hda-gfx",                         Buffer (0x0A)                         {                             "onboard-2"                         },                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-1"                         },                         "@0,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@1,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@2,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@3,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@4,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@5,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }         Device (HDAU)         {             Name (_ADR, One)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0C)                     {                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "device-id",                         Buffer (0x04)                         {                              0xEF, 0x10, 0x00, 0x00                         },                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-1"                         },                         "device_type",                         Buffer (0x16)                         {                             "Multimedia Controller"                         },                         "name",                         Buffer (0x1D)                         {                             "NVIDIA High Definition Audio"                         },                         "hda-gfx",                         Buffer (0x0A)                         {                             "onboard-2"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        The actual GFX0 and HDAU PCI device implementation is valid for SMBIOS iMacPro1,1 (GFX0), the ASUS Prime X299 Deluxe and any Nvidia Graphics Card implemented in PCIe Slot 1.   It is a build and PCIe slot population dependent device implementation. Nvidia Graphics Card users with more than one graphics card, or with an Nvidia graphics card in a PCIe slot different from PCIe Slot 1, will have to adopt the respective device path entries PC02.BR2A, PCIe Slot definitions and PCI device properties following their respective IOREG entries. Note the SL05 -> PEGP and PEGP -> GFX0 ACPI replacements directly performed within the SSDT.   Also note that with 10.13.4, Apple changed the com.apple.driver.AppleHDAController implementation. To make the NVIDIA HDAU PCI device driver work for e.g. a GeForce GTX 1080, one needs to add the following KextToPatch entry in Section "Kernel and kext Patches" of Clover Configurator, as already implemented in the config.plist contained in EFI-X299-10.14-DP1-Release-iMacPro1,1-060618: Name*                                 Find* [HEX]         Replace* [HEX]        Comment com.apple.driver.AppleHDAController   DE100B0E            DE10EF10              FredWst DP/HDMI patch  
      Credits to @FreedWst and thanks to @fabiosun for pointing me to this solution. The KextToPatch entry might defer for Nvidia GPUs different from the Geforce GTX 1080.     Users of NvidiaGraphicsfixup.kext v1.2.6 and above might be able to drop this KextToPatch entry, as the latter kext already properly implements the Nvidia HDAU PCI driver.    Below one finds an example of @apfelnico for a GFX and HDAU PCI implementation of 1x Radeon Vega Frontier in PCIe Slot 1:   DefintionBlock entry: External (_SB_.PC02.BR2A, DeviceObj) // (from opcode) External (_SB_.PC02.BR2A.PEGP, DeviceObj) // (from opcode) External (_SB_.PC02.BR2A.SL05, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PC02.BR2A) { Scope (SL05) { Name (_STA, Zero) // _STA: Status } Scope (PEGP) { Device (EGP0) { Name (_ADR, Zero) // _ADR: Address Device (GFX0) { Name (_ADR, Zero) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x18) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "model", Buffer (0x16) { "Vega Frontier Edition" }, "name", Buffer (0x08) { "ATY_GPU" }, "@0,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@1,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@2,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@3,connector-type", Buffer (0x04) { 0x00, 0x08, 0x00, 0x00 }, "@0,name", Buffer (0x0D) { "ATY,Kamarang" }, "@1,name", Buffer (0x0D) { "ATY,Kamarang" }, "@2,name", Buffer (0x0D) { "ATY,Kamarang" }, "@3,name", Buffer (0x0D) { "ATY,Kamarang" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (HDAU) { Name (_ADR, One) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0A) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "name", Buffer (0x1F) { "Vega Frontier Edition HD-Audio" }, "model", Buffer (0x1F) { "Vega Frontier Edition HD-Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } } } }  
      as well as one example of @apfelnico for the GFX and HDAU PCI implementation of 1x Radeon Vega 64 in PCIe Slot 1, pimped to 1442 Mhz:
       
      DefintionBlock entry: External (_SB_.PC02.BR2A, DeviceObj) // (from opcode) External (_SB_.PC02.BR2A.PEGP, DeviceObj) // (from opcode) External (_SB_.PC02.BR2A.SL05, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PC02.BR2A) { Scope (SL05) { Name (_STA, Zero) // _STA: Status } Scope (PEGP) { Device (EGP0) { Name (_ADR, Zero) // _ADR: Address Device (GFX0) { Name (_ADR, Zero) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x20) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "model", Buffer (0x12) { "Radeon RX Vega 64" }, "name", Buffer (0x08) { "ATY_GPU" }, "@0,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@1,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@2,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@3,connector-type", Buffer (0x04) { 0x00, 0x08, 0x00, 0x00 }, "@0,name", Buffer (0x0D) { "ATY,Kamarang" }, "@1,name", Buffer (0x0D) { "ATY,Kamarang" }, "@2,name", Buffer (0x0D) { "ATY,Kamarang" }, "@3,name", Buffer (0x0D) { "ATY,Kamarang" }, "PP_PhmSoftPowerPlayTable", Buffer (One) { /* 0000 */ 0xB6, 0x02, 0x08, 0x01, 0x00, 0x5C, 0x00, 0xE1, /* 0008 */ 0x06, 0x00, 0x00, 0xEE, 0x2B, 0x00, 0x00, 0x1B, /* 0010 */ 0x00, 0x48, 0x00, 0x00, 0x00, 0x80, 0xA9, 0x03, /* 0018 */ 0x00, 0xF0, 0x49, 0x02, 0x00, 0x8E, 0x00, 0x08, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0028 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, /* 0030 */ 0x5C, 0x00, 0x4F, 0x02, 0x46, 0x02, 0x94, 0x00, /* 0038 */ 0x9E, 0x01, 0xBE, 0x00, 0x28, 0x01, 0x7A, 0x00, /* 0040 */ 0x8C, 0x00, 0xBC, 0x01, 0x00, 0x00, 0x00, 0x00, /* 0048 */ 0x72, 0x02, 0x00, 0x00, 0x90, 0x00, 0xA8, 0x02, /* 0050 */ 0x6D, 0x01, 0x43, 0x01, 0x97, 0x01, 0xF0, 0x49, /* 0058 */ 0x02, 0x00, 0x71, 0x02, 0x02, 0x02, 0x00, 0x00, /* 0060 */ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, /* 0068 */ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x07, 0x00, /* 0070 */ 0x03, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0078 */ 0x00, 0x00, 0x01, 0x08, 0x84, 0x03, 0x84, 0x03, /* 0080 */ 0xB6, 0x03, 0xE8, 0x03, 0x1A, 0x04, 0x4C, 0x04, /* 0088 */ 0x60, 0x04, 0x7E, 0x04, 0x01, 0x01, 0x33, 0x04, /* 0090 */ 0x01, 0x01, 0x84, 0x03, 0x00, 0x08, 0x60, 0xEA, /* 0098 */ 0x00, 0x00, 0x00, 0x40, 0x19, 0x01, 0x00, 0x01, /* 00A0 */ 0x80, 0x38, 0x01, 0x00, 0x02, 0xDC, 0x4A, 0x01, /* 00A8 */ 0x00, 0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0x00, /* 00B0 */ 0x77, 0x01, 0x00, 0x05, 0x90, 0x91, 0x01, 0x00, /* 00B8 */ 0x06, 0x50, 0xBD, 0x01, 0x00, 0x07, 0x01, 0x08, /* 00C0 */ 0xD0, 0x4C, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, /* 00C8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x8D, 0x01, /* 00D0 */ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00D8 */ 0x00, 0x00, 0xDC, 0xC7, 0x01, 0x00, 0x02, 0x00, /* 00E0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, /* 00E8 */ 0xFC, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* 00F0 */ 0x00, 0x00, 0x00, 0x00, 0xD8, 0x1B, 0x02, 0x00, /* 00F8 */ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0100 */ 0x00, 0xF4, 0x40, 0x02, 0x00, 0x05, 0x00, 0x00, /* 0108 */ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1C, 0x64, /* 0110 */ 0x02, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x01, /* 0118 */ 0x00, 0x00, 0x00, 0x68, 0x81, 0x02, 0x00, 0x07, /* 0120 */ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* 0128 */ 0x00, 0x05, 0x60, 0xEA, 0x00, 0x00, 0x00, 0x40, /* 0130 */ 0x19, 0x01, 0x00, 0x00, 0x80, 0x38, 0x01, 0x00, /* 0138 */ 0x00, 0xDC, 0x4A, 0x01, 0x00, 0x00, 0x90, 0x5F, /* 0140 */ 0x01, 0x00, 0x00, 0x00, 0x08, 0x28, 0x6E, 0x00, /* 0148 */ 0x00, 0x00, 0x2C, 0xC9, 0x00, 0x00, 0x01, 0xF8, /* 0150 */ 0x0B, 0x01, 0x00, 0x02, 0x80, 0x38, 0x01, 0x00, /* 0158 */ 0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0xF4, 0x91, /* 0160 */ 0x01, 0x00, 0x05, 0xD0, 0xB0, 0x01, 0x00, 0x06, /* 0168 */ 0x38, 0xC1, 0x01, 0x00, 0x07, 0x00, 0x08, 0x6C, /* 0170 */ 0x39, 0x00, 0x00, 0x00, 0x24, 0x5E, 0x00, 0x00, /* 0178 */ 0x01, 0xFC, 0x85, 0x00, 0x00, 0x02, 0xAC, 0xBC, /* 0180 */ 0x00, 0x00, 0x03, 0x34, 0xD0, 0x00, 0x00, 0x04, /* 0188 */ 0x68, 0x6E, 0x01, 0x00, 0x05, 0x08, 0x97, 0x01, /* 0190 */ 0x00, 0x06, 0xB0, 0xAD, 0x01, 0x00, 0x07, 0x00, /* 0198 */ 0x01, 0x68, 0x3C, 0x01, 0x00, 0x00, 0x01, 0x04, /* 01A0 */ 0x3C, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, /* 01A8 */ 0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x38, /* 01B0 */ 0x01, 0x00, 0x02, 0x00, 0x00, 0x34, 0x98, 0x01, /* 01B8 */ 0x00, 0x04, 0x00, 0x00, 0x01, 0x08, 0x00, 0x98, /* 01C0 */ 0x85, 0x00, 0x00, 0x40, 0xB5, 0x00, 0x00, 0x60, /* 01C8 */ 0xEA, 0x00, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01, /* 01D0 */ 0x80, 0xBB, 0x00, 0x00, 0x60, 0xEA, 0x00, 0x00, /* 01D8 */ 0x94, 0x0B, 0x01, 0x00, 0x50, 0xC3, 0x00, 0x00, /* 01E0 */ 0x02, 0x00, 0xE1, 0x00, 0x00, 0x94, 0x0B, 0x01, /* 01E8 */ 0x00, 0x40, 0x19, 0x01, 0x00, 0x50, 0xC3, 0x00, /* 01F0 */ 0x00, 0x03, 0x78, 0xFF, 0x00, 0x00, 0x40, 0x19, /* 01F8 */ 0x01, 0x00, 0x88, 0x26, 0x01, 0x00, 0x50, 0xC3, /* 0200 */ 0x00, 0x00, 0x04, 0x40, 0x19, 0x01, 0x00, 0x80, /* 0208 */ 0x38, 0x01, 0x00, 0x80, 0x38, 0x01, 0x00, 0x50, /* 0210 */ 0xC3, 0x00, 0x00, 0x05, 0x80, 0x38, 0x01, 0x00, /* 0218 */ 0xDC, 0x4A, 0x01, 0x00, 0xDC, 0x4A, 0x01, 0x00, /* 0220 */ 0x50, 0xC3, 0x00, 0x00, 0x06, 0x00, 0x77, 0x01, /* 0228 */ 0x00, 0x00, 0x77, 0x01, 0x00, 0x90, 0x5F, 0x01, /* 0230 */ 0x00, 0x50, 0xC3, 0x00, 0x00, 0x07, 0x90, 0x91, /* 0238 */ 0x01, 0x00, 0x90, 0x91, 0x01, 0x00, 0x00, 0x77, /* 0240 */ 0x01, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01, 0x18, /* 0248 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, /* 0250 */ 0x00, 0x00, 0xBC, 0x02, 0x48, 0x26, 0x46, 0x00, /* 0258 */ 0x0A, 0x00, 0x54, 0x03, 0x90, 0x01, 0x90, 0x01, /* 0260 */ 0x90, 0x01, 0x90, 0x01, 0x90, 0x01, 0x90, 0x01, /* 0268 */ 0x90, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, /* 0270 */ 0x04, 0x31, 0x07, 0x90, 0x01, 0x90, 0x01, 0x90, /* 0278 */ 0x01, 0x90, 0x01, 0x00, 0x00, 0x59, 0x00, 0x69, /* 0280 */ 0x00, 0x4A, 0x00, 0x4A, 0x00, 0x5F, 0x00, 0x73, /* 0288 */ 0x00, 0x73, 0x00, 0x64, 0x00, 0x40, 0x00, 0x90, /* 0290 */ 0x92, 0x97, 0x60, 0x96, 0x00, 0x90, 0x55, 0x00, /* 0298 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 02A0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 02A8 */ 0x02, 0x02, 0xD4, 0x30, 0x00, 0x00, 0x02, 0x10, /* 02B0 */ 0x60, 0xEA, 0x00, 0x00, 0x02, 0x10 }, "hda-gfx", Buffer (0x0A) { "onboard-2" }, "PP_DisablePowerContainment", Buffer (One) { 0x01 }, "PP_FuzzyFanControl", Buffer (One) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (HDAU) { Name (_ADR, One) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0A) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "name", Buffer (0x14) { "Radeon RX HD-Audio" }, "model", Buffer (0x14) { "Radeon RX HD-Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } } }  
      E.9.2.3) - PMCR - onboard Power Management Controller (PMC) PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0.PMC1, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0)     {         Scope (PMC1)         {             Name (_STA, Zero)  // _STA: Status         }         Device (PMCR)         {             Name (_ADR, 0x001F0002)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0E)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "model",                         Buffer (0x1E)                         {                             "Intel X299 Series Chipset PMC"                         },                         "name",                         Buffer (0x0A)                         {                             "Intel PMC"                         },                         "device-id",                         Buffer (0x04)                         {                              0xA1, 0xA2, 0x00, 0x00                         },                         "device_type",                         Buffer (0x0F)                         {                             "PMC-Controller"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "compatible",                         Buffer (0x0D)                         {                             "pci8086,a2a1"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The PMCR PCI device implementation should be valid for all X299 mainboards and should not require any build specific adaptation/modification. Note the PMC1 -> PMCR ACPI replacement directly performed within the SDDT.   E.9.2.4) - USBX:   PCI Device Implementation: Device (_SB.USBX)     {         Name (_ADR, Zero)  // _ADR: Address         Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method         {             If (LNot (Arg2))             {                 Return (Buffer (One)                 {                      0x03                 })             }             Return (Package (0x08)             {                 "kUSBSleepPortCurrentLimit",                 0x0834,                 "kUSBSleepPowerSupply",                 0x13EC,                 "kUSBWakePortCurrentLimit",                 0x0834,                 "kUSBWakePowerSupply",                 0x13EC             })         }     }  
      When using the XHCI device name for USB (see the XHCI PCI Device Implementation below), one observes a bunch of USB Power Errors when booting the system. The USBX PCI device implementation fixes this errors.     E.9.2.5) - XHCI - onboard Extended Host Controller Interface (XHCI) PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0.XHCI, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.XHCI)     {         Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method         {             Store (Package (0x1B)                 {                     "AAPL,slot-name",                     Buffer (0x09)                     {                         "Built In"                     },                     "built-in",                     Buffer (One)                     {                          0x00                     },                     "device-id",                     Buffer (0x04)                     {                          0xAF, 0xA2, 0x00, 0x00                     },                     "name",                     Buffer (0x34)                     {                         "ASMedia / Intel X299 Series Chipset XHCI Controller"                     },                     "model",                     Buffer (0x34)                     {                         "ASMedia ASM1074 / Intel X299 Series Chipset USB 3.0"                     },                     "AAPL,current-available",                     0x0834,                     "AAPL,current-extra",                     0x0A8C,                     "AAPL,current-in-sleep",                     0x0A8C,                     "AAPL,max-port-current-in-sleep",                     0x0834,                     "AAPL,device-internal",                     Zero,                     "AAPL,clock-id",                     Buffer (One)                     {                          0x01                     },                     "AAPL,root-hub-depth",                     0x1A,                     "AAPL,XHC-clock-id",                     One,                     Buffer (One)                     {                          0x00                     }                 }, Local0)             DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))             Return (Local0)         }     }  
      The XHCI USB3.0 ASMedia ASM1074 / Intel X299 Series Chipset PCI device implementation is valid for the ASUS Prime X299 Deluxe and for all other X299 mainboards with the same XHC controller chipset. Verify and adopt/modify if necessary device path "PCI0.XHCI" and PCI device implementations by means of IOREG.   E.9.2.6) - XHC2,3,4 - ASMedia ASM3142 USB 3.1 Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0.RP01, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP01.PXSX, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP05, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP05.PXSX, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP07, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP07.PXSX, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.RP01)     {         Scope (PXSX)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XHC2)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                    })                 }                 Store (Package (0x1B)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "device-id",                         Buffer (0x04)                         {                              0x42, 0x21, 0x00, 0x00                         },                         "name",                         Buffer (0x17)                         {                             "ASMedia XHC Controller"                         },                         "model",                         Buffer (0x2F)                         {                             "ASMedia ASM3142 #1 1x USB 3.1 Type-C Internal "                         },                         "AAPL,current-available",                         0x0834,                         "AAPL,current-extra",                         0x0A8C,                         "AAPL,current-in-sleep",                         0x0A8C,                         "AAPL,max-port-current-in-sleep",                         0x0834,                         "AAPL,device-internal",                         Zero,                         "AAPL,clock-id",                         Buffer (One)                         {                              0x01                                        },                         "AAPL,root-hub-depth",                         0x1A,                         "AAPL,XHC-clock-id",                         One,                         Buffer (One)                         {                              0x00                                        }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }     Scope (\_SB.PCI0.RP05)     {         Scope (PXSX)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XHC3)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                    })                 }                 Store (Package (0x1B)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "device-id",                         Buffer (0x04)                         {                              0x42, 0x21, 0x00, 0x00                         },                         "name",                         Buffer (0x17)                         {                             "ASMedia XHC Controller"                         },                         "model",                         Buffer (0x2E)                         {                             "ASMedia ASM3142 #2 2x USB 3.1 Type-A External"                         },                         "AAPL,current-available",                         0x0834,                         "AAPL,current-extra",                         0x0A8C,                         "AAPL,current-in-sleep",                         0x0A8C,                         "AAPL,max-port-current-in-sleep",                         0x0834,                         "AAPL,device-internal",                         Zero,                         "AAPL,clock-id",                         Buffer (One)                         {                              0x01                                        },                         "AAPL,root-hub-depth",                         0x1A,                         "AAPL,XHC-clock-id",                         One,                         Buffer (One)                         {                              0x00                                        }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }     Scope (\_SB.PCI0.RP07)     {         Scope (PXSX)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XHC4)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, 0x00020000))                 {                     Return (Buffer (One)                     {                          0x03                                    })                 }                 Store (Package (0x1B)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "device-id",                         Buffer (0x04)                         {                              0x42, 0x21, 0x00, 0x00                         },                         "name",                         Buffer (0x17)                         {                             "ASMedia XHC Controller"                         },                         "model",                         Buffer (0x4A)                         {                             "ASMedia ASM3142 #3 1x USB 3.1 Type-A / ASM1543 1x USB 3.1 Type-C External"                         },                         "AAPL,current-available",                         0x0834,                         "AAPL,current-extra",                         0x0A8C,                         "AAPL,current-in-sleep",                         0x0A8C,                         "AAPL,max-port-current-in-sleep",                         0x0834,                         "AAPL,device-internal",                         Zero,                         "AAPL,clock-id",                         Buffer (One)                         {                              0x01                                        },                         "AAPL,root-hub-depth",                         0x1A,                         "AAPL,XHC-clock-id",                         One,                         Buffer (One)                         {                              0x00                                        }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The XHC2,XHC3,XHC4 ASMedia ASM3142/ASM1543 USB 3.1 onboard Intel XHCI controller PCI device implementation is valid for the ASUS Prime X299 Deluxe and for all other X299 mainboards with the same XHC USB3.1 controller ASMedia ASM3142 chipset configuration. Note that this SSDT-X299-iMacPro.aml device implementation also performs the following ACPI Replacements
        PCI0.RP01.PXSX -> PCI0.RP01.XHC2 PCI0.RP05.PXSX -> PCI0.RP01.XHC3 PCI0.RP07.PXSX -> PCI0.RP01.XHC4   in concordance with the respective SMBIOS iMacPro1,1 variable naming. Verify and adopt/modify if necessary the corresponding "PCI0.RP01.XHC2", "PCI0.RP05.XHC3", "PCI0.RP07.XHC4" PCI device implementations by means of IOREG.   E.9.2.7) ANS1, ANS2 - Apple NVMe Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0.RP09, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP09.PXSX, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP21, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP21.PXSX, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.RP09)     {         Scope (PXSX)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ANS1)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                    })                 }                 Store (Package (0x08)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "name",                         Buffer (0x17)                         {                             "Apple SSD Controller I"                         },                         "model",                         Buffer (0x14)                         {                             "Apple SSD AP1024M I"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }     Scope (\_SB.PCI0.RP21)     {         Scope (PXSX)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ANS2)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                    })                 }                 Store (Package (0x08)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "name",                         Buffer (0x18)                         {                             "Apple SSD Controller II"                         },                         "model",                         Buffer (0x15)                         {                             "Apple SSD AP1024M II"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The current ANS2 Apple NVMe Controller PCI implementation is of purely cosmetic nature and is valid for the ASUS Prime X299 Deluxe. Note that this SSDT-X299-iMacPro.aml device implementation also performs the following ACPI Replacements   PCI0.RP09.PXSX -> PCI0.RP09.ANS1 PCI0.RP21.PXSX -> PCI0.RP21.ANS2   in concordance with the respective SMBIOS iMacPro1,1 variable naming.   Verify and adopt/modify if necessary the "PCI0.RP09.ANS2" PCI device implementations by means of IOREG.     E.9.2.8) - SAT1 - Intel AHCI SATA Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0, DeviceObj)    // (from opcode) External (_SB_.PCI0.SAT1, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0)     {         Scope (SAT1)         {             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0C)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "name",                         Buffer (0x16)                         {                             "Intel AHCI Controller"                         },                         "model",                         Buffer (0x1F)                         {                             "Intel X299 Series Chipset SATA"                         },                         "device_type",                         Buffer (0x15)                         {                             "AHCI SATA Controller"                         },                         "device-id",                         Buffer (0x04)                         {                              0x82, 0xA2, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        The SAT1 onboard Intel AHCI SATA controller PCI device implementation is valid for the ASUS Prime X299 Deluxe and for all other X299 mainboards with the same AHCI SATA controller chipset. Verify and adopt/modify if necessary device path "PCI0.SAT1" and PCI device implementations by means of IOREG.   E.9.2.9) XGBE - 10GBit NIC Implementation:   DefintionBlock entry: External (_SB_.PC03.BR3A, DeviceObj)    // (from opcode) External (_SB_.PC03.BR3A.PEGP, DeviceObj)    // (from opcode) External (_SB_.PC03.BR3A.SL09, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      ASUS XG-C100C AQC107 PCI Device Implementation: Scope (\_SB.PC03.BR3A)     {         Scope (SL09)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (PEGP)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                     })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                         },                         "name",                         Buffer (0x33)                         {                             "ASUS XG-C100C Aquantia AQC107 10-Gigabit Ethernet"                         },                         "model",                         Buffer (0x11)                         {                             "Apple AQC107-AFW"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x87, 0x01, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0xB1, 0x07, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x6B, 0x10, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        Intel X540-T1 PCI Device Implementation: Scope (\_SB.PC03.BR3A)     {         Scope (SL09)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (PEGP)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                   })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                       },                         "name",                         Buffer (0x22)                         {                             "Intel X540-T1 10-Gigabit Ethernet"                         },                         "model",                         Buffer (0x22)                         {                             "Intel X540-T1 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      Small-Tree P2EI0G-2T PCI Device Implementation: Scope (\_SB.PC03.BR3A)     {         Scope (SL09)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (PEGP)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                   })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                       },                         "name",                         Buffer (0x30)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 1"                         },                         "model",                         Buffer (0x29)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }         Device (XGBF)         {             Name (_ADR, One)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                   })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                       },                         "name",                         Buffer (0x30)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 2"                         },                         "model",                         Buffer (0x29)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The 10-Gigabit NIC XGBE PCI implementation is mainly of cosmetic nature. For each PCIe Adapter and for different slot populations the XGBE PCI device implementation needs to be adopted/modified (see details above). This also states for the respective ACPI path entries "PC03", "BR3A" and respective SL09 -> PEGP and PEGP -> XGBE ACPI Replacements (in compliance with the iMac Pro 10GB ACPI variable nomenclature), directly performed within the SSDT-X299-iMacPro.aml. Those not employing any 10-GBit NIC in their system, can simply remove the corresponding SSDT PCI device implementation.   E.9.2.10) - ETH0/ETH1 - onboard LAN Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0, DeviceObj)    // (from opcode) External (_SB_.PCI0.GBE1, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP02, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP02.D0A4, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP02.PXSX, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0)     {         Scope (GBE1)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ETH0)         {             Name (_ADR, 0x001F0006)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "name",                         Buffer (0x16)                         {                             "Intel I219V2 Ethernet"                         },                         "model",                         Buffer (0x2A)                         {                             "Intel I219V2 PCI Express Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "2"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x72, 0x86, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0xB8, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x43, 0x10, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }     Scope (\_SB.PCI0.RP02)     {         Scope (D0A4)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (PXSX)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ETH1)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "name",                         Buffer (0x16)                         {                             "Intel I211VA Ethernet"                         },                         "model",                         Buffer (0x2A)                         {                             "Intel I211VA PCI Express Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "2"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0xF0, 0x85, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x39, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x43, 0x10, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        Note that the ETH0/ETH1 Intel I219V2 PCI Express Gigabit Ethernet and Intel I211VA PCI Express Gigabit Ethernet onboard LAN controller PCI implementations are of pure cosmetic nature and only valid for ASUS Prime X299 Deluxe or X299 mainboards with the same LAN Controller configuration. Owners of different X299 mainboards have to verify and adopt/modify if necessary the device these PCI device implementations by means of IOREG. Note the PCI0.GBE1 -> PCI0.ETH0, PCI0.RP02.D0A4 -> PCI0.RP02.PXSX and PCI0.RP02.PXSX -> PCI0.RP02.ETH1 ACPI replacements directly performed within the DSDT.   E.9.2.11) - ARPT - OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PC03.BR3D, DeviceObj)    // (from opcode) External (_SB_.PC03.BR3D.PEGP, DeviceObj)    // (from opcode) External (_SB_.PC03.BR3D.SL0C, DeviceObj)    // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (_SB.PC03.BR3D)     {         Scope (SL0C)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (PEGP)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ARPT)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0E)                     {                         "built-in",                         Buffer (One)                         {                              0x00                                        },                         "device-id",                         Buffer (0x04)                         {                              0xA0, 0x43, 0x00, 0x00                         },                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-3"                         },                         "device_type",                         Buffer (0x13)                         {                             "AirPort Controller"                         },                         "model",                         Buffer (0x4A)                         {                             "OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 Controller"                         },                         "compatible",                         Buffer (0x0D)                         {                             "pci14e4,43a0"                         },                         "name",                         Buffer (0x10)                         {                             "AirPort Extreme"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The ARPT OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI device implementation is of pure cosmetic nature and only valid for users of the latter WIFI/Bluetooth PCIe Adapter in PCIe Slot 3. Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 3 have to adapt/modify the respective device path "PC03","BR3D","ARPT" and likely also the respective ACPI Replacements PC03.BR3D.SL0C -> PC03.BR3D.PEGP and PC03.BR3D.PEGP -> PC03.BR3D.ARPT, directly performed within the SSDT. Users of the Asus Prime X299 Deluxe onboard Bluetooth chipset controller or with a completely different WIFI/Bluetooth configuration have to adopt the entire Airport PCI implementation by means of IOREG.   E.9.2.12) - DTGP Method: Method (DTGP, 5, NotSerialized)     {         If (LEqual (Arg0, ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))         {             If (LEqual (Arg1, One))             {                 If (LEqual (Arg2, Zero))                 {                     Store (Buffer (One)                         {                              0x03                         }, Arg4)                     Return (One)                 }                 If (LEqual (Arg2, One))                 {                     Return (One)                 }             }         }         Store (Buffer (One)             {                  0x00             }, Arg4)         Return (Zero)     } }  
        The DTG Method Implementation is required for SSDT functionality and has not to be modified or adopted in any case.     E.9.2.13) - Debugging Sleep Issues:   For debugging sleep issues as proposed by Pike Alpha, one can add SSDT-SLEEP.aml to /EFI/CLOVER/ACPI/patched and follow Pike's comment and advices provided at https://pikeralpha.wordpress.com/2017/01/12/debugging-sleep-issues/     E.9.3)  SSDT-X299-TB3-iMacPro-KGP.aml PCI Implementation   The Thunderbolt PCI device implementation was formerly part of the SSDT-X299-iMacPro.aml. Due to it's exponentially growing complexity and length, this latter PCI device implementation has now been outsourced from SSDT-X299-iMacPro.aml and newly realised within it's proper and mostly independent aml-file, namely SSDT-X299-TB3-iMacPro-KGP.aml.   The current Thunderbolt PCI device implementation is kept has close as possible to SSDT-9.aml of @TheOfficialGypsy's iMac Pro dumb. It also contains implementations mainly developed by @apfelnico and @nmano, but also @Mork vom Ork, @Matthew82, @maleorderbride and @TheRacerMaster.   It is valid for both, the ASUS TBEX 3 and Gigabyte Alpine Ridge and allows for TB and XHC USB sleep/wake functionality with the THB_C cable plugged to the thunderbolt onboard header of the ASUS Prime X299 Deluxe. While XHC USB hot plug seems to work fine within this configuration, TB hot plug seems to require the removal of the THB_C cable. Thank's to @crismac2013 and @LeleTuratti for their findings!   >>> https://youtu.be/Jakp5dCoFvY <<<   Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 4 have to adapt/modify the respective ACPI path entries "PC01", "BR1A" and respective SL01 -> PEGP and PEGP -> UPSB ACPI Replacements, directly performed within the SSDT.    DefintionBlock entry: External (_SB_.PC01, DeviceObj)    // (from opcode) External (_SB_.PC01.BR1A, DeviceObj)    // (from opcode) External (_SB_.PC01.BR1A.PEGP, DeviceObj)    // (from opcode) External (_SB_.PC01.BR1A.SL01, DeviceObj)    // (from opcode) External (_SB_.PWRB, DeviceObj)    // (from opcode) External (AG12, UnknownObj)    // (from opcode) External (DTGP, MethodObj)    // 5 Arguments (from opcode) External (IO80, UnknownObj)    // (from opcode) External (PG12, UnknownObj)    // (from opcode) External (PICM, UnknownObj)    // (from opcode) External (PWRB, DeviceObj)    // (from opcode)  
      PCI Device Implementation:     OperationRegion (GNVS, SystemMemory, 0x4FEE6918, 0x0403)     Field (GNVS, AnyAcc, Lock, Preserve)     {         OSYS,   16     }     Method (OSDW, 0, NotSerialized)     {         If (LEqual (OSYS, 0x2710))         {             Return (One)         }         Else         {             Return (Zero)         }     }     Method (PINI, 0, NotSerialized)     {         Store (0x07DC, OSYS)         If (XOSI ("Darwin"))         {             Store (0x2710, OSYS)         }         ElseIf (XOSI ("Linux"))         {             Store (0x03E8, OSYS)         }         ElseIf (XOSI ("Windows 2009"))         {             Store (0x07D9, OSYS)         }         ElseIf (XOSI ("Windows 2012"))         {             Store (0x07DC, OSYS)         }         Else         {             Store (0x07DC, OSYS)         }     }     Method (XOSI, 1, NotSerialized)     {         Store (Package (0x0E)             {                 "Darwin",                 "Linux",                 "Windows",                 "Windows 2001",                 "Windows 2001 SP2",                 "Windows 2001.1",                 "Windows 2001.1 SP1",                 "Windows 2006",                 "Windows 2006 SP1",                 "Windows 2006.1",                 "Windows 2009",                 "Windows 2012",                 "Windows 2013",                 "Windows 2015"             }, Local0)         Return (LNotEqual (Ones, Match (Local0, MEQ, Arg0, MTR, Zero, Zero)))     }     Scope (\_SB.PC01)     {         Scope (BR1A.SL01)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (BR1A.PEGP)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (BR1A)         {             Name (_STA, Zero)  // _STA: Status         }         Device (BR1X)         {             Name (_ADR, Zero)  // _ADR: Address             OperationRegion (MCTL, SystemMemory, 0x60000188, 0x04)             Field (MCTL, ByteAcc, NoLock, Preserve)             {                     ,   3,                 HGPE,   1,                     ,   7,                     ,   8,                     ,   8             }             Method (_INI, 0, NotSerialized)  // _INI: Initialize             {                 Store (One, HGPE)             }             Name (_HPP, Package (0x04)  // _HPP: Hot Plug Parameters             {                 0x08,                 0x40,                 One,                 Zero             })             Name (SHPC, 0x40)             Name (SPDS, 0x40)             Name (MRLS, Zero)             Name (CCOM, 0x10)             Name (SPDC, 0x08)             Name (MRLC, 0x04)             Name (SPFD, 0x02)             Name (SABP, One)             Name (SPOF, 0x10)             Name (SPON, 0x0F)             Name (ALMK, 0x1C)             Name (ALON, One)             Name (ALBL, 0x02)             Name (ALOF, 0x03)             Name (PLMK, 0x13)             Name (PLON, 0x04)             Name (PLBL, 0x08)             Name (PLOF, 0x0C)             Name (HPEV, 0x0F)             OperationRegion (PPA4, PCI_Config, Zero, 0x0100)             Field (PPA4, ByteAcc, NoLock, Preserve)             {                 Offset (0xA0),                     ,   4,                 LDIS,   1,                 Offset (0xA2),                 Offset (0xA4),                 ATBP,   1,                     ,   1,                 MRSP,   1,                 ATIP,   1,                 PWIP,   1,                     ,   14,                 PSNM,   13,                 ABIE,   1,                 PFIE,   1,                 MSIE,   1,                 PDIE,   1,                 CCIE,   1,                 HPIE,   1,                 SCTL,   5,                 Offset (0xAA),                 SSTS,   7,                 Offset (0xAB),                 Offset (0xB0),                 Offset (0xB2),                 PMES,   1,                 PMEP,   1,                 Offset (0xB4)             }             Method (ATID, 0, NotSerialized)             {                 Return (And (SCTL, 0x03))             }             Method (PWID, 0, NotSerialized)             {                 Return (ShiftRight (And (SCTL, 0x0C), 0x02))             }             Method (PWCC, 0, NotSerialized)             {                 Return (ShiftRight (And (SCTL, 0x10), 0x04))             }             Method (ABPS, 1, NotSerialized)             {                 If (LEqual (Arg0, One))                 {                     Or (SSTS, One, SSTS)                 }                 Return (And (SSTS, One))             }             Method (PFDS, 1, NotSerialized)             {                 If (LEqual (Arg0, One))                 {                     Or (SSTS, 0x02, SSTS)                 }                 Return (ShiftRight (And (SSTS, 0x02), One))             }             Method (MSCS, 1, NotSerialized)             {                 If (LEqual (Arg0, One))                 {                     Or (SSTS, 0x04, SSTS)                 }                 Return (ShiftRight (And (SSTS, 0x04), 0x02))             }             Method (PDCS, 1, NotSerialized)             {                 If (LEqual (Arg0, One))                 {                     Or (SSTS, 0x08, SSTS)                 }                 Return (ShiftRight (And (SSTS, 0x08), 0x03))             }             Method (CMCS, 1, NotSerialized)             {                 If (LEqual (Arg0, One))                 {                     Or (SSTS, 0x10, SSTS)                 }                 Return (ShiftRight (And (SSTS, 0x10), 0x04))             }             Method (MSSC, 1, NotSerialized)             {                 If (LEqual (Arg0, One))                 {                     Or (SSTS, 0x20, SSTS)                 }                 Return (ShiftRight (And (SSTS, 0x20), 0x05))             }             Method (PRDS, 1, NotSerialized)             {                 If (LEqual (Arg0, One))                 {                     Or (SSTS, 0x40, SSTS)                 }                 Return (ShiftRight (And (SSTS, 0x40), 0x06))             }             Method (OSHP, 0, NotSerialized)             {                 Store (SSTS, SSTS)                 Store (Zero, HGPE)             }             Method (HPCC, 1, NotSerialized)             {                 Store (SCTL, Local0)                 Store (Zero, Local1)                 If (LNotEqual (Arg0, Local0))                 {                     Store (Arg0, SCTL)                     While (LAnd (LNot (CMCS (Zero)), LNotEqual (0x64, Local1)))                     {                         Store (0xFB, IO80)                         Sleep (0x02)                         Add (Local1, 0x02, Local1)                     }                     CMCS (One)                 }             }             Method (ATCM, 1, NotSerialized)             {                 Store (SCTL, Local0)                 And (Local0, ALMK, Local0)                 If (LEqual (Arg0, One))                 {                     Or (Local0, ALON, Local0)                 }                 If (LEqual (Arg0, 0x02))                 {                     Or (Local0, ALBL, Local0)                 }                 If (LEqual (Arg0, 0x03))                 {                     Or (Local0, ALOF, Local0)                 }                 HPCC (Local0)             }             Method (PWCM, 1, NotSerialized)             {                 Store (SCTL, Local0)                 And (Local0, PLMK, Local0)                 If (LEqual (Arg0, One))                 {                     Or (Local0, PLON, Local0)                 }                 If (LEqual (Arg0, 0x02))                 {                     Or (Local0, PLBL, Local0)                 }                 If (LEqual (Arg0, 0x03))                 {                     Or (Local0, PLOF, Local0)                 }                 HPCC (Local0)             }             Method (PWSL, 1, NotSerialized)             {                 Store (SCTL, Local0)                 If (Arg0)                 {                     And (Local0, SPON, Local0)                 }                 Else                 {                     Or (Local0, SPOF, Local0)                 }                 HPCC (Local0)             }             Method (_OST, 3, Serialized)  // _OST: OSPM Status Indication             {                 Name (_T_1, Zero)  // _T_x: Emitted by ASL Compiler                 Name (_T_0, Zero)  // _T_x: Emitted by ASL Compiler                 While (One)                 {                     Store (And (Arg0, 0xFF), _T_0)                     If (LEqual (_T_0, 0x03))                     {                         While (One)                         {                             Store (ToInteger (Arg1), _T_1)                             If (LNotEqual (Match (Package (0x04)                                             {                                                 0x80,                                                 0x81,                                                 0x82,                                                 0x83                                             }, MEQ, _T_1, MTR, Zero, Zero), Ones))                             {                                 If (LNot (PWCC ()))                                 {                                     PWCM (One)                                     Store (One, ABIE)                                 }                             }                             Break                         }                     }                     Break                 }             }             Method (EJ0L, 0, NotSerialized)             {                 Store (0xFF, IO80)                 Store (SCTL, Local0)                 If (LNotEqual (ATID (), One))                 {                     And (Local0, ALMK, Local0)                     Or (Local0, ALBL, Local0)                 }                 HPCC (Local0)                 Store (SCTL, Local0)                 Or (Local0, SPOF, Local0)                 HPCC (Local0)                 Store (SCTL, Local0)                 Or (Local0, PLOF, Local0)                 HPCC (Local0)                 Store (SCTL, Local0)                 Or (Local0, ALOF, Local0)                 HPCC (Local0)             }             Method (PMEH, 1, NotSerialized)             {                 If (And (HPEV, SSTS))                 {                     If (ABPS (Zero))                     {                         Store (Arg0, IO80)                         ABPS (One)                         Sleep (0xC8)                     }                 }                 Return (0xFF)             }             Method (HPEH, 1, NotSerialized)             {                 Store (0xFE, IO80)                 Sleep (0x64)                 Store (Zero, CCIE)                 If (And (HPEV, SSTS))                 {                     Store (0xFD, IO80)                     Sleep (0x0A)                     Store (Arg0, IO80)                     Sleep (0x0A)                     Store (PPXH (), Local0)                     Return (Local0)                 }                 Else                 {                     Return (0xFF)                 }                 Store (0xFC, IO80)                 Sleep (0x0A)             }             Method (PPXH, 0, NotSerialized)             {                 Sleep (0xC8)                 If (ABPS (Zero))                 {                     If (LNot (PRDS (Zero)))                     {                         Store (One, LDIS)                         PWSL (Zero)                         PWCM (0x03)                         If (LEqual (MSSC (Zero), MRLS))                         {                             ATCM (0x02)                         }                         Else                         {                             ATCM (0x03)                         }                         Store (Zero, ABIE)                         ABPS (One)                         Sleep (0xC8)                         Return (0xFF)                     }                     Store (Zero, ABIE)                     ABPS (One)                     Sleep (0xC8)                     If (PWCC ())                     {                         PWCM (0x03)                         ATCM (0x02)                         Return (0xFF)                     }                     Else                     {                         PWCM (0x02)                         Sleep (0x0258)                         Store (0x0258, Local0)                         ABPS (One)                         Sleep (0xC8)                         While (LNot (ABPS (Zero)))                         {                             Sleep (0xC8)                             Add (Local0, 0xC8, Local0)                             If (LEqual (0x1388, Local0))                             {                                 ABPS (One)                                 Sleep (0xC8)                                 Return (0x03)                             }                         }                         PWCM (One)                         ABPS (One)                         Sleep (0xC8)                         Store (One, ABIE)                         Return (0xFF)                     }                 }                 If (PFDS (Zero))                 {                     PFDS (One)                     PWSL (Zero)                     PWCM (0x03)                     ATCM (One)                     Store (One, LDIS)                     Return (0x03)                 }                 If (MSCS (Zero))                 {                     MSCS (One)                     If (LEqual (MSSC (Zero), MRLS))                     {                         If (PRDS (Zero))                         {                             ATCM (0x03)                             PWCM (0x02)                             Sleep (0x0258)                             Store (0x0258, Local0)                             ABPS (One)                             While (LNot (ABPS (Zero)))                             {                                 Sleep (0xC8)                                 Add (Local0, 0xC8, Local0)                                 If (LEqual (0x1388, Local0))                                 {                                     Store (One, ABIE)                                     ATCM (0x03)                                     Store (Zero, LDIS)                                     PWSL (One)                                     Sleep (0x01F4)                                     If (LNot (PFDS (Zero)))                                     {                                         PWCM (One)                                         Store (Zero, Local1)                                         Store (One, ABIE)                                     }                                     Else                                     {                                         PWSL (Zero)                                         PWCM (0x03)                                         ATCM (One)                                         Store (One, LDIS)                                         Store (0x03, Local1)                                     }                                     ABPS (One)                                     Sleep (0xC8)                                     Return (Local1)                                 }                             }                             ABPS (One)                             Sleep (0xC8)                             PWSL (Zero)                             PWCM (0x03)                             ATCM (0x02)                             Store (One, LDIS)                             Return (0xFF)                         }                         PWSL (Zero)                         PWCM (0x03)                         ATCM (0x02)                         Store (One, LDIS)                         Return (0xFF)                     }                     Else                     {                         If (PRDS (Zero))                         {                             ATCM (0x02)                             If (LNot (PWCC ()))                             {                                 PWSL (Zero)                                 PWCM (0x03)                                 Store (One, LDIS)                                 Return (0x03)                             }                             Else                             {                                 Return (0xFF)                             }                         }                         ATCM (0x03)                         Return (0xFF)                     }                 }                 If (PDCS (Zero))                 {                     PDCS (One)                     If (LNot (PRDS (Zero)))                     {                         PWSL (Zero)                         PWCM (0x03)                         If (LEqual (MSSC (Zero), MRLS))                         {                             ATCM (0x02)                         }                         Else                         {                             ATCM (0x03)                         }                         Store (One, LDIS)                         Return (0xFF)                     }                     Else                     {                         Store (Zero, LDIS)                         PWSL (One)                         Sleep (0x01F4)                         If (LNot (PFDS (Zero)))                         {                             PWCM (One)                             Store (Zero, Local1)                             Store (One, ABIE)                             ATCM (0x03)                         }                         Else                         {                             PWSL (Zero)                             PWCM (0x03)                             ATCM (One)                             Store (One, LDIS)                             Store (0x03, Local1)                         }                         ABPS (One)                         Sleep (0xC8)                         Return (Local1)                     }                 }                 Return (0xFF)             }             Method (SNUM, 0, Serialized)             {                 Store (PSNM, Local0)                 Return (Local0)             }             Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number             {                 Return (SNUM ())             }             Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table             {                 If (PICM)                 {                     Return (AG12)                 }                 Return (PG12)             }             Device (UPSB)             {                 Name (_ADR, Zero)  // _ADR: Address                 OperationRegion (A1E0, PCI_Config, Zero, 0x40)                 Field (A1E0, ByteAcc, NoLock, Preserve)                 {                     AVND,   32,                     BMIE,   3,                     Offset (0x18),                     PRIB,   8,                     SECB,   8,                     SUBB,   8,                     Offset (0x1E),                         ,   13,                     MABT,   1                 }                 OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)                 Field (A1E1, ByteAcc, NoLock, Preserve)                 {                     Offset (0x01),                     Offset (0x02),                     Offset (0x04),                     Offset (0x08),                     Offset (0x0A),                         ,   5,                     TPEN,   1,                     Offset (0x0C),                     SSPD,   4,                         ,   16,                     LACR,   1,                     Offset (0x10),                         ,   4,                     LDIS,   1,                     LRTN,   1,                     Offset (0x12),                     CSPD,   4,                     CWDT,   6,                         ,   1,                     LTRN,   1,                         ,   1,                     LACT,   1,                     Offset (0x14),                     Offset (0x30),                     TSPD,   4                 }                 OperationRegion (A1E2, PCI_Config, 0x80, 0x08)                 Field (A1E2, ByteAcc, NoLock, Preserve)                 {                     Offset (0x01),                     Offset (0x02),                     Offset (0x04),                     PSTA,   2                 }                 Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                 {                     Return (SECB)                 }                 Method (_STA, 0, NotSerialized)  // _STA: Status                 {                     Return (0x0F)                 }                 Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                 {                     Return (One)                 }                 Device (DSB0)                 {                     Name (_ADR, Zero)  // _ADR: Address                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                     Field (A1E0, ByteAcc, NoLock, Preserve)                     {                         AVND,   32,                         BMIE,   3,                         Offset (0x18),                         PRIB,   8,                         SECB,   8,                         SUBB,   8,                         Offset (0x1E),                             ,   13,                         MABT,   1                     }                     OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)                     Field (A1E1, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         Offset (0x08),                         Offset (0x0A),                             ,   5,                         TPEN,   1,                         Offset (0x0C),                         SSPD,   4,                             ,   16,                         LACR,   1,                         Offset (0x10),                             ,   4,                         LDIS,   1,                         LRTN,   1,                         Offset (0x12),                         CSPD,   4,                         CWDT,   6,                             ,   1,                         LTRN,   1,                             ,   1,                         LACT,   1,                         Offset (0x14),                         Offset (0x30),                         TSPD,   4                     }                     OperationRegion (A1E2, PCI_Config, 0x80, 0x08)                     Field (A1E2, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         PSTA,   2                     }                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                     {                         Return (SECB)                     }                     Method (_STA, 0, NotSerialized)  // _STA: Status                     {                         Return (0x0F)                     }                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                     {                         Return (One)                     }                     Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method                     {                         If (LNot (Arg2))                         {                             Return (Buffer (One)                             {                                  0x03                                            })                         }                         Return (Package (0x02)                         {                             "PCIHotplugCapable",                             One                         })                     }                     Device (NHI0)                     {                         Name (_ADR, Zero)  // _ADR: Address                         Name (_STR, Unicode ("Thunderbolt"))  // _STR: Description String                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                         {                             Return (Zero)                         }                         OperationRegion (A1E0, PCI_Config, Zero, 0x40)                         Field (A1E0, ByteAcc, NoLock, Preserve)                         {                             AVND,   32,                             BMIE,   3,                             Offset (0x18),                             PRIB,   8,                             SECB,   8,                             SUBB,   8,                             Offset (0x1E),                                 ,   13,                             MABT,   1                         }                         Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method                         {                             If (LEqual (Arg2, Zero))                             {                                 Return (Buffer (One)                                 {                                      0x03                                                })                             }                             Store (Package (0x13)                                 {                                     "AAPL,slot-name",                                     Buffer (0x07)                                     {                                         "Slot-4"                                     },                                     "built-in",                                     Buffer (One)                                     {                                          0x00                                                    },                                     "device_type",                                     Buffer (0x19)                                     {                                         "Thunderbolt 3 Controller"                                     },                                     "model",                                     Buffer (0x20)                                     {                                         "Intel DSL6540 Thunderbolt 3 NHI"                                     },                                     "name",                                     Buffer (0x25)                                     {                                         "Intel DSL6540 Thunderbolt Controller"                                     },                                     "pathcr",                                     Buffer (One)                                     {                                         /* 0000 */  0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0008 */  0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00,                                         /* 0010 */  0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0018 */  0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00,                                         /* 0020 */  0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x0E, 0x00,                                         /* 0028 */  0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0030 */  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0038 */  0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x01, 0x00,                                         /* 0040 */  0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0048 */  0x00, 0x00, 0x07, 0x00, 0x02, 0x00, 0x01, 0x00                                     },                                     "ThunderboltDROM",                                     Buffer (One)                                     {                                         /* 0000 */  0x6D, 0x01, 0xC5, 0x49, 0xD5, 0x3E, 0x21, 0x01,                                         /* 0008 */  0x00, 0x04, 0xCE, 0x8D, 0x61, 0x01, 0x5E, 0x00,                                         /* 0010 */  0x01, 0x00, 0x0C, 0x00, 0x01, 0x00, 0x08, 0x81,                                         /* 0018 */  0x81, 0x02, 0x81, 0x00, 0x00, 0x00, 0x08, 0x82,                                         /* 0020 */  0x91, 0x01, 0x81, 0x00, 0x00, 0x00, 0x08, 0x83,                                         /* 0028 */  0x81, 0x04, 0x81, 0x01, 0x00, 0x00, 0x08, 0x84,                                         /* 0030 */  0x91, 0x03, 0x81, 0x01, 0x00, 0x00, 0x08, 0x85,                                         /* 0038 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x86,                                         /* 0040 */  0x20, 0x03, 0x87, 0x80, 0x02, 0xC8, 0x05, 0x89,                                         /* 0048 */  0x50, 0x00, 0x00, 0x05, 0x8A, 0x50, 0x00, 0x00,                                         /* 0050 */  0x02, 0xCB, 0x0D, 0x01, 0x41, 0x70, 0x70, 0x6C,                                         /* 0058 */  0x65, 0x20, 0x49, 0x6E, 0x63, 0x2E, 0x00, 0x0C,                                         /* 0060 */  0x02, 0x4D, 0x61, 0x63, 0x69, 0x6E, 0x74, 0x6F,                                         /* 0068 */  0x73, 0x68, 0x00                                        },                                     "ThunderboltConfig",                                     Buffer (One)                                     {                                         /* 0000 */  0x01, 0x02, 0xFF, 0xFF, 0x04, 0x00, 0x03, 0x01,                                         /* 0008 */  0x01, 0x00, 0x04, 0x00, 0x05, 0x01, 0x02, 0x00,                                         /* 0010 */  0x03, 0x00, 0x03, 0x01, 0x01, 0x00, 0x01, 0x00,                                         /* 0018 */  0x03, 0x01, 0x02, 0x00, 0x04, 0x00, 0x03, 0x00                                     },                                     "power-save",                                     One,                                     Buffer (One)                                     {                                          0x00                                                    }                                 }, Local0)                             DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                             Return (Local0)                         }                         Return (Zero)                     }                 }                 Device (DSB1)                 {                     Name (_ADR, 0x00010000)  // _ADR: Address                     Name (_SUN, 0x04)  // _SUN: Slot User Number                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                     Field (A1E0, ByteAcc, NoLock, Preserve)                     {                         AVND,   32,                         BMIE,   3,                         Offset (0x18),                         PRIB,   8,                         SECB,   8,                         SUBB,   8,                         Offset (0x1E),                             ,   13,                         MABT,   1                     }                     OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)                     Field (A1E1, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         Offset (0x08),                         Offset (0x0A),                             ,   5,                         TPEN,   1,                         Offset (0x0C),                         SSPD,   4,                             ,   16,                         LACR,   1,                         Offset (0x10),                             ,   4,                         LDIS,   1,                         LRTN,   1,                         Offset (0x12),                         CSPD,   4,                         CWDT,   6,                             ,   1,                         LTRN,   1,                             ,   1,                         LACT,   1,                         Offset (0x14),                         Offset (0x30),                         TSPD,   4                     }                     OperationRegion (A1E2, PCI_Config, 0x80, 0x08)                     Field (A1E2, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         PSTA,   2                     }                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                     {                         Return (SECB)                     }                     Method (_STA, 0, NotSerialized)  // _STA: Status                     {                         Return (0x0F)                     }                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                     {                         Return (Zero)                     }                     Device (UPS0)                     {                         Name (_ADR, Zero)  // _ADR: Address                         OperationRegion (ARE0, PCI_Config, Zero, 0x04)                         Field (ARE0, ByteAcc, NoLock, Preserve)                         {                             AVND,   16                         }                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                         {                             If (OSDW ())                             {                                 Return (One)                             }                             Return (Zero)                         }                         Device (DSB0)                         {                             Name (_ADR, Zero)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1,                                 Offset (0x3E),                                     ,   6,                                 SBRS,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                             Device (DEV0)                             {                                 Name (_ADR, Zero)  // _ADR: Address                                 Method (_STA, 0, NotSerialized)  // _STA: Status                                 {                                     Return (0x0F)                                 }                                 Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                 {                                     If (OSDW ())                                     {                                         Return (One)                                     }                                     Return (Zero)                                 }                             }                         }                         Device (DSB3)                         {                             Name (_ADR, 0x00030000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                             Device (UPS0)                             {                                 Name (_ADR, Zero)  // _ADR: Address                                 OperationRegion (ARE0, PCI_Config, Zero, 0x04)                                 Field (ARE0, ByteAcc, NoLock, Preserve)                                 {                                     AVND,   16                                 }                                 Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                 {                                     If (OSDW ())                                     {                                         Return (One)                                     }                                     Return (Zero)                                 }                                 Device (DSB0)                                 {                                     Name (_ADR, Zero)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1,                                         Offset (0x3E),                                             ,   6,                                         SBRS,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                     }                                 }                                 Device (DSB3)                                 {                                     Name (_ADR, 0x00030000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB4)                                 {                                     Name (_ADR, 0x00040000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB5)                                 {                                     Name (_ADR, 0x00050000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                                 Device (DSB6)                                 {                                     Name (_ADR, 0x00060000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                             }                         }                         Device (DSB4)                         {                             Name (_ADR, 0x00040000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                             Device (UPS0)                             {                                 Name (_ADR, Zero)  // _ADR: Address                                 OperationRegion (ARE0, PCI_Config, Zero, 0x04)                                 Field (ARE0, ByteAcc, NoLock, Preserve)                                 {                                     AVND,   16                                 }                                 Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                 {                                     If (OSDW ())                                     {                                         Return (One)                                     }                                     Return (Zero)                                 }                                 Device (DSB0)                                 {                                     Name (_ADR, Zero)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1,                                         Offset (0x3E),                                             ,   6,                                         SBRS,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB3)                                 {                                     Name (_ADR, 0x00030000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB4)                                 {                                     Name (_ADR, 0x00040000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB5)                                 {                                     Name (_ADR, 0x00050000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                                 Device (DSB6)                                 {                                     Name (_ADR, 0x00060000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                             }                         }                         Device (DSB5)                         {                             Name (_ADR, 0x00050000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                         }                         Device (DSB6)                         {                             Name (_ADR, 0x00060000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                         }                     }                 }                 Device (DSB2)                 {                     Name (_ADR, 0x00020000)  // _ADR: Address                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                     Field (A1E0, ByteAcc, NoLock, Preserve)                     {                         AVND,   32,                         BMIE,   3,                         Offset (0x18),                         PRIB,   8,                         SECB,   8,                         SUBB,   8,                         Offset (0x1E),                             ,   13,                         MABT,   1                     }                     OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)                     Field (A1E1, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         Offset (0x08),                         Offset (0x0A),                             ,   5,                         TPEN,   1,                         Offset (0x0C),                         SSPD,   4,                             ,   16,                         LACR,   1,                         Offset (0x10),                             ,   4,                         LDIS,   1,                         LRTN,   1,                         Offset (0x12),                         CSPD,   4,                         CWDT,   6,                             ,   1,                         LTRN,   1,                             ,   1,                         LACT,   1,                         Offset (0x14),                         Offset (0x30),                         TSPD,   4                     }                     OperationRegion (A1E2, PCI_Config, 0x80, 0x08)                     Field (A1E2, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         PSTA,   2                     }                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                     {                         Return (SECB)                     }                     Method (_STA, 0, NotSerialized)  // _STA: Status                     {                         Return (0x0F)                     }                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                     {                         Return (Zero)                     }                     Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method                     {                         If (LNot (Arg2))                         {                             Return (Buffer (One)                             {                                  0x03                                            })                         }                         Return (Package (0x02)                         {                             "PCIHotplugCapable",                             Zero                         })                     }                     Device (XHC5)                     {                         Name (_ADR, Zero)  // _ADR: Address                         Name (SDPC, Zero)                         OperationRegion (A1E0, PCI_Config, Zero, 0x40)                         Field (A1E0, ByteAcc, NoLock, Preserve)                         {                             AVND,   32,                             BMIE,   3,                             Offset (0x18),                             PRIB,   8,                             SECB,   8,                             SUBB,   8,                             Offset (0x1E),                                 ,   13,                             MABT,   1                         }                         Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method                         {                             If (LEqual (Arg2, Zero))                             {                                 Return (Buffer (One)                                 {                                      0x03                                                })                             }                             Return (Package (0x10)                             {                                 "AAPL,slot-name",                                 Buffer (0x07)                                 {                                     "Slot-4"                                 },                                 "built-in",                                 Buffer (One)                                 {                                      0x00                                                },                                 "model",                                 Buffer (0x16)                                 {                                     "Intel DSL6540 USB 3.1"                                 },                                 "name",                                 Buffer (0x1D)                                 {                                     "Intel DSL6540 XHC Controller"                                 },                                 "device-id",                                 Buffer (0x04)                                 {                                      0xB6, 0x15, 0x00, 0x00                                 },                                 "USBBusNumber",                                 Zero,                                 "AAPL,XHCI-clock-id",                                 One,                                 "UsbCompanionControllerPresent",                                 One                             })                         }                         Name (HS, Package (0x01)                         {                             "XHC1"                         })                         Name (FS, Package (0x01)                         {                             "XHC1"                         })                         Name (LS, Package (0x01)                         {                             "XHC1"                         })                         Method (_PRW, 0, NotSerialized)  // _PRW: Power Resources for Wake                         {                             Return (Package (0x02)                             {                                 0x6D,                                 Zero                             })                         }                         Device (RHUB)                         {                             Name (_ADR, Zero)  // _ADR: Address                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 Return (Zero)                             }                             Device (SSP1)                             {                                 Name (_ADR, One)  // _ADR: Address                                 Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities                                 {                                     0xFF,                                     0x09,                                     Zero,                                     Zero                                 })                                 Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device                                 {                                     Buffer (0x10)                                     {                                         /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00                                     }                                 })                                 Name (HS, Package (0x02)                                 {                                     "XHC1",                                     0x05                                 })                                 Name (FS, Package (0x02)                                 {                                     "XHC1",                                     0x05                                 })                                 Name (LS, Package (0x02)                                 {                                     "XHC1",                                     0x05                                 })                                 Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method                                 {                                     If (LEqual (Arg2, Zero))                                     {                                         Return (Buffer (One)                                         {                                              0x03                                                        })                                     }                                     Return (Package (0x08)                                     {                                         "UsbCPortNumber",                                         0x03,                                         "kUSBWakePortCurrentLimit",                                         0x0BB8,                                         "kUSBSleepPortCurrentLimit",                                         0x0BB8,                                         "UsbCompanionPortPresent",                                         One                                     })                                 }                             }                             Device (SSP2)                             {                                 Name (_ADR, 0x02)  // _ADR: Address                                 Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities                                 {                                     0xFF,                                     0x09,                                     Zero,                                     Zero                                 })                                 Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device                                 {                                     Buffer (0x10)                                     {                                         /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00                                     }                                 })                                 Name (HS, Package (0x02)                                 {                                     "XHC1",                                     0x06                                 })                                 Name (FS, Package (0x02)                                 {                                     "XHC1",                                     0x06                                 })                                 Name (LS, Package (0x02)                                 {                                     "XHC1",                                     0x06                                 })                                 Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method                                 {                                     If (LEqual (Arg2, Zero))                                     {                                         Return (Buffer (One)                                         {                                              0x03                                                        })                                     }                                     Return (Package (0x08)                                     {                                         "UsbCPortNumber",                                         0x04,                                         "kUSBWakePortCurrentLimit",                                         0x0BB8,                                         "kUSBSleepPortCurrentLimit",                                         0x0BB8,                                         "UsbCompanionPortPresent",                                         One                                     })                                 }                             }                             Device (HS01)                             {                                 Name (_ADR, 0x03)  // _ADR: Address                                 Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities                                 {                                     0xFF,                                     0x09,                                     Zero,                                     Zero                                 })                                 Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device                                 {                                     Buffer (0x10)                                     {                                         /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00                                     }                                 })                             }                             Device (HS02)                             {                                 Name (_ADR, 0x04)  // _ADR: Address                                 Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities                                 {                                     0xFF,                                     0x09,                                     Zero,                                     Zero                                 })                                 Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device                                 {                                     Buffer (0x10)                                     {                                         /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,                                         /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00                                     }                                 })                             }                         }                     }                 }                 Device (DSB4)                 {                     Name (_ADR, 0x00040000)  // _ADR: Address                     Name (_SUN, 0x02)  // _SUN: Slot User Number                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                     Field (A1E0, ByteAcc, NoLock, Preserve)                     {                         AVND,   32,                         BMIE,   3,                         Offset (0x18),                         PRIB,   8,                         SECB,   8,                         SUBB,   8,                         Offset (0x1E),                             ,   13,                         MABT,   1                     }                     OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)                     Field (A1E1, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         Offset (0x08),                         Offset (0x0A),                             ,   5,                         TPEN,   1,                         Offset (0x0C),                         SSPD,   4,                             ,   16,                         LACR,   1,                         Offset (0x10),                             ,   4,                         LDIS,   1,                         LRTN,   1,                         Offset (0x12),                         CSPD,   4,                         CWDT,   6,                             ,   1,                         LTRN,   1,                             ,   1,                         LACT,   1,                         Offset (0x14),                         Offset (0x30),                         TSPD,   4                     }                     OperationRegion (A1E2, PCI_Config, 0x80, 0x08)                     Field (A1E2, ByteAcc, NoLock, Preserve)                     {                         Offset (0x01),                         Offset (0x02),                         Offset (0x04),                         PSTA,   2                     }                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                     {                         Return (SECB)                     }                     Method (_STA, 0, NotSerialized)  // _STA: Status                     {                         Return (0x0F)                     }                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                     {                         Return (Zero)                     }                     Device (UPS0)                     {                         Name (_ADR, Zero)  // _ADR: Address                         OperationRegion (ARE0, PCI_Config, Zero, 0x04)                         Field (ARE0, ByteAcc, NoLock, Preserve)                         {                             AVND,   16                         }                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                         {                             If (OSDW ())                             {                                 Return (One)                             }                             Return (Zero)                         }                         Device (DSB0)                         {                             Name (_ADR, Zero)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1,                                 Offset (0x3E),                                     ,   6,                                 SBRS,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                             Device (DEV0)                             {                                 Name (_ADR, Zero)  // _ADR: Address                                 Method (_STA, 0, NotSerialized)  // _STA: Status                                 {                                     Return (0x0F)                                 }                                 Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                 {                                     If (OSDW ())                                     {                                         Return (One)                                     }                                     Return (Zero)                                 }                             }                         }                         Device (DSB3)                         {                             Name (_ADR, 0x00030000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                             Device (UPS0)                             {                                 Name (_ADR, Zero)  // _ADR: Address                                 OperationRegion (ARE0, PCI_Config, Zero, 0x04)                                 Field (ARE0, ByteAcc, NoLock, Preserve)                                 {                                     AVND,   16                                 }                                 Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                 {                                     If (OSDW ())                                     {                                         Return (One)                                     }                                     Return (Zero)                                 }                                 Device (DSB0)                                 {                                     Name (_ADR, Zero)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1,                                         Offset (0x3E),                                             ,   6,                                         SBRS,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                     }                                 }                                 Device (DSB3)                                 {                                     Name (_ADR, 0x00030000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB4)                                 {                                     Name (_ADR, 0x00040000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB5)                                 {                                     Name (_ADR, 0x00050000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                                 Device (DSB6)                                 {                                     Name (_ADR, 0x00060000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                             }                         }                         Device (DSB4)                         {                             Name (_ADR, 0x00040000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                             Device (UPS0)                             {                                 Name (_ADR, Zero)  // _ADR: Address                                 OperationRegion (ARE0, PCI_Config, Zero, 0x04)                                 Field (ARE0, ByteAcc, NoLock, Preserve)                                 {                                     AVND,   16                                 }                                 Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                 {                                     If (OSDW ())                                     {                                         Return (One)                                     }                                     Return (Zero)                                 }                                 Device (DSB0)                                 {                                     Name (_ADR, Zero)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1,                                         Offset (0x3E),                                             ,   6,                                         SBRS,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB3)                                 {                                     Name (_ADR, 0x00030000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB4)                                 {                                     Name (_ADR, 0x00040000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                     Device (DEV0)                                     {                                         Name (_ADR, Zero)  // _ADR: Address                                         Method (_STA, 0, NotSerialized)  // _STA: Status                                         {                                             Return (0x0F)                                         }                                         Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                         {                                             If (OSDW ())                                             {                                                 Return (One)                                             }                                             Return (Zero)                                         }                                     }                                 }                                 Device (DSB5)                                 {                                     Name (_ADR, 0x00050000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                                 Device (DSB6)                                 {                                     Name (_ADR, 0x00060000)  // _ADR: Address                                     OperationRegion (A1E0, PCI_Config, Zero, 0x40)                                     Field (A1E0, ByteAcc, NoLock, Preserve)                                     {                                         AVND,   32,                                         BMIE,   3,                                         Offset (0x18),                                         PRIB,   8,                                         SECB,   8,                                         SUBB,   8,                                         Offset (0x1E),                                             ,   13,                                         MABT,   1                                     }                                     Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                                     {                                         Return (SECB)                                     }                                     Method (_STA, 0, NotSerialized)  // _STA: Status                                     {                                         Return (0x0F)                                     }                                     Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                                     {                                         If (OSDW ())                                         {                                             Return (One)                                         }                                         Return (Zero)                                     }                                 }                             }                         }                         Device (DSB5)                         {                             Name (_ADR, 0x00050000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                         }                         Device (DSB6)                         {                             Name (_ADR, 0x00060000)  // _ADR: Address                             OperationRegion (A1E0, PCI_Config, Zero, 0x40)                             Field (A1E0, ByteAcc, NoLock, Preserve)                             {                                 AVND,   32,                                 BMIE,   3,                                 Offset (0x18),                                 PRIB,   8,                                 SECB,   8,                                 SUBB,   8,                                 Offset (0x1E),                                     ,   13,                                 MABT,   1                             }                             Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number                             {                                 Return (SECB)                             }                             Method (_STA, 0, NotSerialized)  // _STA: Status                             {                                 Return (0x0F)                             }                             Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status                             {                                 If (OSDW ())                                 {                                     Return (One)                                 }                                 Return (Zero)                             }                         }                     }                 }                 Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method                 {                     If (LNot (Arg2))                     {                         Return (Buffer (One)                         {                              0x03                                        })                     }                     Return (Package (0x02)                     {                         "PCI-Thunderbolt",                         One                     })                 }             }         }     }  
      Thanks to @nmano we now also have an additional SSDT, i.e SSDT-TB3-L02-BR1X.aml, which fixes further TB ACPI dependencies and which should be implemented in /EFI/Clover/ACPI/patches. This SSDT will permanently load the TB NHI0 and XHC USB PCI drivers, even in case that no TB devices are connected. Apparently it also resolves some TB sleep/wake issues.   SSDT-TB3-L02-BR1X.aml can be substituted by a simple Clover DSDT patch to be included in the config plist:   Comment:  BR1A BR1X THB patch ©N.Mano Find: 42523141 48303030 60865C2F 045F5342 5F504349 30425231 41483030 3160865C 2F045F53 425F5043 49304252 31414830 30326086 5C2F045F 53425F50 43493042 52314148 30303360 865C2F04 5F53425F 50434930 42523141 48303034 60865C2F 045F5342 5F504349 30425231 41483030 3560865C 2F045F53 425F5043 49304252 31414830 30366086 5C Replace: 42523158 55505342 60865C2F 055F5342 5F504349 30425231 58555053 42445342 3060865C 2F055F53 425F5043 49304252 31585550 53424453 42316086 5C2F055F 53425F50 43493042 52315855 50534244 53423260 865C2F05 5F53425F 50434930 42523158 55505342 44534233 60865C2F 055F5342 5F504349 30425231 58555053 42445342 3460862A 51  
      Note that both TB-SSDTs are mainboard and slot-dependend! With the TBEX 3 or Alpine Ridge in a PCIe slot different from PCIe Slot-4, one needs to adopt both SSDT and DSDT patch in concordance with IOREG. All Gigabyte users with the TBEX 3 or Alpine Ridge in PCIe Slot-4 can use SSDT-X299-TB3-iMacPro-Gigabyte.aml and SSDT-TB3-L02-PR2X.aml.zip instead.      E.10) System Overview CPU Cosmetics 
      As our Skylake-X CPU at present will not be properly recognised by OS X, Apple's System Overview ("About This Mac") reveals incomplete or simply wrong CPU details. Many times CPU's like the i9-7980XE are implemented as "unknown"...   I recently discovered on InsanelyMac a sophisticated fix of pure cosmetic nature developed by Shaneee (also thanks to fabiosun for pointing me to this direction), which allows to implement those CPU details you want to be implemented. For the sake of simplicity, I summarise the necessary steps once more below. Note that the following example is only valid for systems with English as main system language. If your system language is German, French, Spanish, Chinese etc., substitute "English.lproj" in the individual commands by the "lproj" of your System language! Thanks to @PedroJSkywalker for this latter important advice!   1.) Open a terminal and use the following commands: cp /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings ~/Desktop/ sudo mv /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings-Backup   2.) Open "AppleSystemInfo.strings" on your Desktop with TextWrangler and change <key>UnknownCPUKind</key> <string>Unknown</string>  
      to what ever you want. In my case I choose:
      <key>UnknownCPUKind</key> <string>4,5 GHz 18-core 36-thread Skylake-X i9-7980XE</string>   Save  "AppleSystemInfo.strings"     3.) Run the following terminal commands: sudo codesign -f -s - ~/Desktop/AppleSystemInfo.strings sudo cp ~/Desktop/AppleSystemInfo.strings /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/   and reboot your system.   4.) Open your config.plist with Clover Configurator and in Section "CPU" set "Type" to "Unknown". Save the config.plist and reboot.   5.) Apple's System Overview now will reveal the following details:     As fall back option enter the following terminal commands:
      sudo rm /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings sudo mv /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings-Backup /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.string  
      and reboot.
       
      E.11) ASUS Boot Splash Screen Cosmetics
      Based on the ideas and instructions of @Matthew82 from InsanelyMac, I achieved an iMacPro ASUS Boot Splash Screen
       
       
      by means of the following procedure:   1.) Installation of the BREW distribution (if not already performed in Section B.1):   a.) Open a terminal and change to "bash" shell.   bash  
      b.) Now enter the following "bash" terminal command and follow the standard BREW installation instructions:
      /usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)"  
      2.) After the successful installation of the BREW distribution, we have to implement the QT5 distribution, again by using a "bash" terminal shell. If not already performed in Section B1.), just enter the following "bash" terminal commands:
      brew install qt5 brew link qt5 --force  
      3.) After successfully implementing BREW and QT5, we can now download the most actual CodeRush UEFIPatch distribution from Github to our home directory with the following terminal command:
      git clone https://github.com/LongSoft/UEFITool   4.) Now compile the UEFI Tool distribution with the following terminal commands:   cd /UEFITools/ qmake uefitool.pro make   5.) Download and unzip iMacPro.raw to your Desktop.   6.) Now launch by UEFITool by clicking on the newly compiled UEFITool.app in the UEFITools Folder in your home directory.   a.) Select "File" -> "Open image file" and load your patched or unpatched BIOS Firmware distribution.   Select "Search.." in the UEFITool "Edit" Menu and perform a "GUID" search of "7BB28B99-61BB-11D5-9A5D-0090273FC14D" with "Header only"...    
      You will receive a message "GUID pattern "7BB28B99-61BB-11D5-9A5D-0090273FC14D" found as .... in 7BB28B99-....". Double click on that message and search for the "Raw section" accompanying the "7BB28B99-...." entry, which indeed is the Boot Image, which you can easily verify by extracting the raw section body (right-click on "Raw section" and select "Extract body") to your Desktop and by subsequently opening the extracted raw-file directly with Apple's "Preview.app" (right-click an the raw file and select "Open with.." -> Preview.app).   b.) To exchange the default original ASUS Boot Logo image file stored in "Raw Section" by the iMacPro.raw image file that you previously downloaded to your Desktop,  right-click again on "Raw section", select this time "Replace body"  and select the iMacPro.raw image file on your Desktop.     Note that the actual image dimension of iMacPro.raw (2131pix x 1457pix) was adopted for its use on my 38" LG 38UC99. For monitors with reduce screen resolution, iMacPro.raw might have to be adopted to an image dimension that suites your particular screen resolution, before its upload to "Raw section". If the Boot Logo image dimension is too big for your Monitor's screen resolution, you might just end up with a black screen during the BIOS initialisation at boot.   To do so, select in the Preview.app Menu -> "Tools" -> "Adjust Size". Change the image dimension and save the modified image with "File" -> "Export". In the "Export menu" press "Save", after selecting "JPEG" under "Format" , after choosing "Desktop" as the place to store the image, and after entering the new file name, which has to end with ".jpg".   Double-check by right-clicking on the resulting jpg image file and selecting "Get Info" that its file size does no exceed 200KB by far. If the latter would be the case, you would not be able to save the modified BIOS Firware file subsequently.   Finally just rename your new "XXXX.jpg" file to "XXXX.raw....   I guess, that by following the procedure detailed above, it is obvious that iMacPro.raw also can be substituted by any other image of your personal choice. Just be aware that it's background colour should be black (ecstatic reason for a its nice integration within the else black ASUS BIOS Boot Screen)   c.)  After replacing "Raw Section" with iMacPro.raw or the XXX.raw image of your choice, save your modified BIOS Firmware File with the Option "File" -> "Save Image File..."   d.) Copy your modified BIOS Firmware file to a USB3.0 Flash Drive, formatted with FAT32.   e.) Reboot, enter the Mainboard BIOS and save your BIOS settings to the USB Flash Drive   f.) Flash your mainboard BIOS with the modified BIOS Firmware   g.) Renter the Mainboard BIOS and restore your BIOS settings from the USB Flash Drive   h.) Save your restored BIOS settings with (F7) and (F10), reboot and you are done.   Just don't forget to set BIOS Setting "Boot Logo Display" to "Auto", when using this new approach. Any different setting might result in a black screen during BIOS initialisation.    
      E.12) Native Display Brightness Control / Native NightShift Functionality for Monitors with DCC/IC Support
        1.) Native Display Brightness Control    Many of you might miss the ability to control the display brightness with the F1/F2 keys on original Apple Keyboards, or with FN&F1/FN&F2 on non-Apple keyboards.    @bensge wrote a small but genius application to do just that on any Hackintosh System and to show the native OSX brightness system UI.    
      The App works for desktops and monitors that support DDC/CI. You have to connect your monitor to your GPU either via HDMI or DP. Note that you also have to enable DDC/CI support on your monitor to make the program work.   This application automatically adds itself as a Login Item in your User Settings in System Preferences.    
      Please carefully read all instructions on his NativeDiplayBrightness GitHub page before downloading the program.
      git clone https://github.com/Bensge/NativeDisplayBrightness/ cd ~/NativeDisplayBrightness/ xcodebuild   The compiled NativeDisplayBrightness.app can be found in subfolder ~/NativeDisplayBrightness/build/Release   To add the application as a Login Item in your User Settings in System Preferences, just double click on the App.    If you're using an original Apple keyboard, this app won't work with your F1/F2 keys straight away. On non-Apple keyboards it won't work out off the box, even with FN&F1/FN&F2 as it should work  .    In both cases you need to additionally add two KernelToPatch entries in your config.plist in Section "Kernel and Kext Patches" of Clover Configurator: Name* Find* [Hex] Replace* [HEX] Comment com.apple.driver.AppleHIDKeyboard 30783030 30373030 33612c30 78666630 31303032 31 30783030 30373030 33612c30 78303030 37303033 61 by Wern com.apple.driver.AppleHIDKeyboard 30783030 30373030 33622c30 78666630 31303032 30 30783030 30373030 33622c30 78303030 37303033 62 by Wern   2.) Native NightShift Functionality for Monitors with DDC/IC Support   To enable native NightShift functionality on the 38" LG 38UC99, one needs to download and unzip the respective Display Override Profile DisplayProductID-76fc, subsequently properly sign the file, and finally copy the file to /System/Library/Displays/Contents/Resources/Overrides/DisplayVendorID-1e6d/.   The latter to steps can be done by the following terminal commands: cd ~/Downloads sudo codesign -f -s - DisplayProductID-76fc sudo cp DisplayProductID-76fc /System/Library/Displays/Contents/Resources/Overrides/DisplayVendorID-1e6d/ Subsequently you have to reboot and to newly adjust your Screen Resolution under "Display" in System Preferences.
       

       
      And your are done:
       
       
      Note that the attached Display Override Profile, does not allow a LG 38UC99 Monitor Frequency of 75Hz. Only 60Hz are supported.   Many thanks to user @Ramalama for providing this approach to our community. NightShift should also work for the Acer 38" and Dell 38" Monitors. Yet @Ramalama misses the respective EDIDs. Any body with e.g. the Acer XR382CQK should immediately  upload the requested information and contact @Ramalama by posting in this thread! Many thanks in advance!   E.13) Logic-X and Audio Studio Software Functionality
       
      The ASUS BIOS patching, providing full read/write access for the OSX Kernel to the MSR 0xE2 register, apparently also circumvents the Intel SKZ7 bug and yet missing BIOS microcode implementations. The Xnu CPU Power Management (XCPM) is now solely handled by the OSX Kernel, which completely resolves all former Logic-X or other studio audio software implementations. The same states for all other X299 mainboards with factory-default open MSR 0xE2 register implementation.   Nevertheless there is a second extremely important intrinsic LOGIC X configuration setting, which has to be adopted depending on the degree of sophistication of the studio audio hardware (Latency) in use.   In the following description, I will provide the correct audio preference settings for the ASUS Prime X299 with the onboard Realtek ALC S1220A audio chip:   1.) Within Logic X go to "Preferences" -> "Audio"   2.) Under Advanced check "Show Advanced Tools"   3.) Go back to the "Audio" settings and adopt "I/O Buffer Size" from "128" to e.g. "512" or even better "1024" Samples, in case you really use the onboard Realtek ALC S1220A audio chipset. Users of more sophisticated Studio Audio Hardware with better latencies have to adopt the I/O Buffer Size accordingly to their hardware implementation.    
      To check the now flawless functionality and performance of Logic-X, download, unzip and run the attached Logic-X test sample Test Hyperthreading Bug.logicx.zip of @DSM2. attached at the bottom of this originating post/guide. Note that the test sample sound volume output is zero, for avoiding epileptic or panic attacks at audience side... this is just a test sample to check the Logic-X functionality and performance and not a chart breaking audio sample.
       
      Start Intel Power Gadget (IPG) in parallel and play the test sample with Logic-X:
       
       
      You will rapidly notice that everything fully behaves as expected. The Hyperthreading-sample plays flawless at alternated CPU frequencies.
      All credits to @DSM2.
       
      E.14) iStatMenus Hardware Monitoring
       
      Thanks to extended tweet session between @BJango, @gxsolace and myself, it seems that we achieved a major step forward in properly monitoring Skylake-X/X299 Hardware with iStatMenus. iStatMenus now correctly interfaces with the HWSensor and FakeSMC kext distribution provided by @interferenc.
       
      The most actual iStatMenus v6.1 distribution can be assessed at https://bjango.com/mac/istatmenus/   The most actual HWSensor and FakeSMC kext distribution of @interferenc can be assessed at https://github.com/interferenc/HWSensors   To compile the the HWSensor and FakeSMC kexts of @interferenc, perform the individual steps detailed below:   1.) git clone https://github.com/interferenc/HWSensors 2.)
      cp HWSensors ~/Desktop/ 3.)
      cd ~/Desktop/HWSensors 4.) 
      xcodebuild -project Versioning\ And\ Distribution.xcodeproj/ 5.)
      xcodebuild -project HWMonitor.xcodeproj/ 6.)
      xcodebuild -project HWSensors.xcodeproj -alltargets   Subsequently, one finds the all compiled binaries in ~/Desktop/HWSensors/Binaries/.   Note that all compiled kext binaries are once more attached towards the bottom of this originating thread (guide). Just download and unzip HW-Sensors-IF.zip and copy all kexts to /EFI/Clover/kexts/Other/. Note that this pre-compiled binary package already implements a modified GPU Sensor kext of @Kozlek, which should also account for Polaris GPUs.   Many thanks to both @interferenc and @Bjango for their awesome and extensive contributions and brilliant work!   Skylake-X/X299 iStatMenus Hardware Sensor Data:
       
      Skylake-X CPU Thread Utilisation Graphs:

       
      To change from CPU core to thread utilisation monitoring, uncheck "Hide Hyper-Threading cores" in Section "CPU & GPU" of iStatMenus Preferences.

        Temperature unites can be adjusted between Celsius, Fahrenheit and Kelvin in Section "Sensors" of iStatMenus Preferences.       F.) Benchmarking
          F.1) Sylake-X Intel I9-7980XE (4.8GHz) CPU Benchmarking       Geekbench CPU Benchmark:  Multi-Core Sore: 65.348 Single-Core Sore: 5.910   Cinebench Cpu Benchmark: 4.618 CB  
          Compare with recent Geekbench results for the 18-core iMacPro (W2191B):   Geekbench CPU Benchmark:  Multi-Core Sore: 46.406 Single-Core Sore: 5.175
          F.2) Gigabyte AORUS GTX 1080 Ti Waterforce EB 11GB Extreme Edition Benchmarking     Geekbench OpenGl and Metal2 Benchmarks:  OpenGL Sore: 229.965 Metal2 Sore: 242.393  
        G.) Summary and Conclusion:
       
      Already during the first individual macOS High Sierra 10.13 beta releases, Syklake-X/X299 systems reached full functionality together with flawless stability. Now with macOS High Sierra 10.13.5 (17F77), it might be the right moment to follow my build and Desktop Installation Guide to unfold the unbelievable Skylake-X/X299 potential together with macOS High Sierra 10.13 (special iMac Pro build)!   I am quite optimistic that high-end builds based on extremely novel Skylake-X/X299 technology will find manifold application, not only in science and research at universities or research institutions, engineering facilities, or medical labs, etc... Skylake-X processors with up to 18 cores (36 threads) and turbo frequencies up to 4.8 GHz will make X299 to a "relatively cheap" but really serious alternative to the iMac Pro's and Mac Pro's. The principal intention of this desktop guide was to demonstrate, that we are able to build and configure fully functional and relatively "low-cost" high-end systems nowadays, which go far beyond of what Apple is able to offer at present or will be ever able to offer for some reasonable pricing. A Skylake-X/X299-System, that allows the use of all software-packages developed for MacOS, Unix, Linux or even Windows at the same time (e.g. think on Vine, Parallels, or a dual boot system configuration). The flexibility between different mainboards (Asus, Gigabyte, ASRock, MSI, etc.), different Skylake-X processors, and different RAM memory configurations (16-128GB) should make such system affordable for anybody (also home office, audio and video editing/production, etc.) and allow its perfect adaptation for the specific purpose, requirements and available budgets. It might not be necessary to outline, that current Skylake-X/X299 Systems perform absolutely stable on a 24/7/365 basis.   I am a scientist, expert in solar physics, space weather forecast and related telescope/instrument/space-mission development. In the frame of my scientific research, I developed parallelized image reconstruction, spectral line inversion and numerical modeling algorithms/applications, which require tremendous parallelized calculation power, RAM memory and storage capacities to reduce, analyze and interpret extensive and pioneering scientific ground-based or space-born observational data sets. This basically was also the professional motivation for developing my innovative iMacPro macOS High Sierra Hackintosh Build iSPOR-S (the imaging Spectropolarimetric Parallel Organized Reconstruction Server running iSPOR-DP, the Imaging Spectropolarimetric Parallel Organized Reconstruction Data Pipeline software package for the GREGOR Fabry-Pérot Interferometer, located at the 1.5m GREGOR Solar Telescope (Europe's largest solar telescope) on Tenerife, Canary Islands, Spain) and for the entire respective iMac Pro Skylake-X/X299 Desktop User Guide Development, which hopefully will be also of benefit for others.  Anybody interested can find more details on my personal webpage.  
    • By KGP-iMacPro
      Up and running  macOS 10.14 Mojave DP1 (18A293u) on my Broadwell-E/X99 iMac Pro Hackintosh! 
       

       
       

       

       
      Abstract and Introduction: 

      This originating post constitutes an innovative and brand new iMac Pro macOS 10.14 Mojave Build and Desktop Guide for Broadwell-E/EP, Haswell-E/EP and X99, which certainly will grow along the 10.14 Betas not only thanks to your estimated feedback and contributions. It is the logical continuation of my successful iMac Pro Broadwell-E/EP, Haswell-E/EP and X99 Build and Desktop Guide published for macOS High Sierra 10.13 in the other forum. Being an iMac Pro Desktop Guide, it has also large similarities with my Skylake-X/X299 iMac Pro macOS 10.14 Mojave Desktop Guide. However, to avoid jumping back and forth, I will make this guide as consistent as the other, which however implies also some redundancy.    
       
      As everybody already might know, my Broadwell-E/EP, Haswell-E/EP and X99 Desktop Guides base on the ASUS X99-A II. However, also other X99 ASUS mainboard models or X99 mainboards of other brands might be compatible after likely considering and implementing few mandatory modifications. The same states for guide compatibility with all Broadwell-E/EP and Haswell-E/EP CPUs different form the i7-6950X employed here. 
       
      Before starting with all detailed instructions, please find a Table of Content that provides an overview of the individual topics addressed within this guide:   --------------------------------------------------------------------------------------------------------------   Table of Contents:    A.) Hardware Summary    B.) ASUS Mainboard BIOS B.1) ASUS BIOS Firmware Patching B.2) ASUS X99-A II BIOS Configuration   C.) Important General Note/ Advice and Error Prevention     D.) iMac Pro macOS 10.14 Mojave System Setup This chapter includes a general guideline how to perform the initial setup of a Broadwell-E/EP, Haswell-E/EP, X99 iMac Pro with macOS Mojave DP1 (18A293u).    D.1) iMac Pro EFI-Folder Preparation D.2) iMac Pro macOS Mojave DP1 (18A293u) Installer Package Creation D.3) iMac macOS Mojave DP1 (18A293u) USB Flash Drive Installer Creation D.4) iMac Pro macOS Mojave DP1 (18A293u) Clean Install on Broadwell-E/EP, Haswell-E/EP, X99 D.5) Direct iMac Pro conversion of a functional Broadwell-E/EP, Haswell-E/EP, X99 system with a SMBIOS System Definition different from iMac Pro1,1 and a standard macOS build implementation.  D.6) iMac Pro macOS High Sierra Build Update Procedure   E.) Post Installation Process E.1) Xnu CPU Power Management (XCPM) Configuration E.2) Graphics Configuration E.3) Audio Configuration E.4) USB Configuration E.5) M.2/NVMe Configuration E.6) SSD/NVMe TRIM Support E.7) Thunderbolt EX3 PCIe Add-On Implementation E.8) Gbit and 10-Gbit Ethernet Implementations E.8.1) ASUS X99-A II on-board Gbit Ethernet Functionality E.8.2) 10-Gbit LAN Implementations E.8.2.1) ASUS XG-C100C Aquantia AQC107 10-Gbit NIC E.8.2.2) Intel X540-T1 10-Gbit NIC E.8.2.3) Small-Tree P2EI0G-2T 10-Gbit NIC E.8.2.4) NetGear ProSave XS508M 8-port 10-Gbit Switch E.8.2.5) QNAP TS-431X2 Quad-core 4-Bay NAS tower E.8.2.6) 10-GBit Ethernet Optimisation E.9) ASUS X99-A II PCI Device Implementation E.9.1)  ACPI DSDT Replacement Implementation E.9.2) SSDT-ASUS-X99-A-II.aml PCI Device Implementation E.9.2.1) HDEF - onboard Audio Controller PCI Implementation: E.9.2.2) GFX1, HDAU - Nvidia Graphics Card and HDMI/DP Audio PCI implementation E.9.2.3) XGBE - 10GBit NIC Implementation: E.9.2.4) ETH0 - onboard LAN Controller PCI Implementation E.9.2.5) SAT1 - Intel AHCI SATA Controller PCI Implementation E.9.2.6) EVSS - Intel X99 sSata Controller PCI Implementation E.9.2.7)  NVMe Controller PCI Implementation E.9.2.8) - USBX: E.9.2.9) XHCI - onboard Extended Host Controller Interface (XHCI) PCI Implementation E.9.2.10) ASMedia ASM1142 USB 3.1 Controller PCI Implementation E.9.2.11) ARPT - OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI Implementation: E.9.2.12) DTGP Method E.9.2.13) - Debugging Sleep Issues E.9.3) SSDT-X99-TB3-iMacPro-KGP.aml PCI Device Implementation E.10) iMac Pro Boot Splash Screen Cosmetics E.11) iMac Pro Desktop Background cosmetics E.12) iStatMenus Hardware Monitoring   F.) Benchmarking F.1) i7-6950X CPU Benchmarks F.2) Gigabyte AORUS GTX 1080 Ti 11GB Xterme Edition OpenGL and Metal Benchmarks     G.) Summary and Conclusion    --------------------------------------------------------------------------------------------------------------   A.) Hardware Summary
       
      Motherboard: Asus X99-A II
      CPU: I7-6950X (10-core) RAM: 128 KIT (8X16GB) G.Skill TridentZ (F4-3200C14Q2-128GTZSW) System Disk: Samsung 850 EVO 1TB (SSD) / Samsung 960 EVO 1TB (NVMe, M.2) RAID: 3x Western Digital Red Pro 6TB (18TB); Graphics: Gigabyte AORUS GeForce® GTX 1080 Ti Xtreme Edition 11G (GV-N108TAORUS X-11GD) Wifi + Bluetooth: OSXWIFI PC/Hackintosh - Apple Broadcom Bcm9436cd - 802.11 A/B/G/N/AC +Bluetooth 4.0 PCIe Power Supply: Corsair AX860 CPU Cooler: Corsair H80i v2 Webcam: Logitech HD Pro WebCam C930 Monitor: LG 38UC99-W, 38", WQHD, 21:9, 3840x1600 pixel, 75 Hz. Case: Corsair CC600TWM-WHT, Graphite Series 600T, Mid Tower Keyboard: Logitech K811 Mouse: Logitech Ultra-Thin Touch Mouse T631 Blu-Ray/DVD Writer: LG Super Multi Blue BH16 (BH16NS55)   Thunderbolt: ASUS TBEX 3 and Gigabyte Alpine Ridge   10Gbit Ethernet components: - 1x ASUS XG-C100C AQC107 PCIe x4 10GBit LAN Adapter (for testing purposes) - 1x Intel X540-T1 single port 10GBit LAN PCIe Adapter (for testing purposes, now installed in my X99 rig) - 1x Small-Tree P2EI0G-2T 2-Port 10GBit LAN PCIe Adapter (now default configuration) - 1x NetGear ProSave XS508M 8-port 10GBit switch - 1x QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port and 4x 12 TB Seagate IronWolf in RAID 0 configuration.   Let me express my gratitude to @gxsolace at this place for providing me with 1x Intel X540-T1, 1x Small-tree P2EI0G-2T and 4x 12 TB Seagate IronWolf hardware.   B.) Asus Mainboard BIOS   Please find below a detailed instruction for ASUS X99 mainboard BIOS Firmware patching, as well as a summary of my actual Asus X99-A II  BIOS settings.   B.1) Asus Mainboard BIOS Firmware Patching   On a real Mac with native OSX XCPM power management, the MSR 0xE2 register is unlocked and therefore writeable. However, on ASUS mobos this register is usually read only. This is also the case for all ASUS X99 mobos. When the kernel tries to write to this locked register, it causes a kernel panic. This panic can happen very early in the boot process, with the result that your system freezes or reboots during the boot process. We can circumvent the MSR 0xE2 register write with a dedicated KernelToPatch entry in the config.plist, namely "xcpm_core_scope_msrs © Pike R. Alpha" and by enabling the "KernelPM" in the config.plist in Section "Kernel and Kext Patches" of the Clover Configurator. See Section E.1) for further details.   However, thanks to CodeRush's Longsoft UEFIPatch distribution and sophisticated MSR 0xE2 Register patches, we are able to successfully patch any ASUS X99 mainboard BIOS distribution and unlock the MSR 0xE2 register. This makes the "xcpm_core_scope_msrs © Pike R. Alpha" KernelToPatch entry obsolete and allows full native read/write MSR 0xE2 register access by the OSX kernel. The patched ASUS mainboard BIOS firmware finally can be uploaded each specific ASUS X99 mainboard by means of the ASUS EZ BIOS Flashback Procedure.   The individual steps for the ASUS X99 BIOS Patching are detailed below:   1.) Download and unzip the CodeRush's UEFI patch (attached towards the bottom of this guide) to your Desktop.   2.) To patch the latest BIOS for your ASUS mobo, download the most actual BIOS version from the ASUS mobo support page (e.g., follow the subsequent link to obtain the latest BIOS Version for the Asus X99-A II).   3.) Unzip the bios file and copy the CAP file into the UEFIPatch directory on your Desktop.   4.) Open a terminal; type "cd " and drag the "UEFIPatch"-folder on your Desktop into the Terminal window and press "Enter". One can also use the terminal command equivalent: cd ~/Desktop/UEFIPatch_0.3.9_osx/ Note that this step is important to successfully execute the UEFI-Patch procedure! You must be in the UEFIPatch directory on your terminal, in order to successfully execute step 5.) below!
        Once in the UEFIPatch directory on your terminal, drop the "UEFIPatch"-executable into the terminal window; Also drop the most actual BIOS CAP file into the terminal window; Press enter to execute the "UEFIPatch"-procedure. The equivalent terminal command is: ./UEFIPatch X99-A-II-ASUS-1902.CAP by assuming that you want to patch the latest X99-A-II-ASUS-1902.CAP BIOS-files for the ASUS X99-A II. For other mobos, please adapt the adequate BIOS CAP-filename in the command!
        During the patch procedure, you will see something like the following message, which can be simply ignored: parseImageFile: Aptio capsule signature may become invalid after image modifications parseSection: section with unknown type 52h parseFile: non-empty pad-file contents will be destroyed after volume modifications parseSection: section with unknown type 52h parseFile: non-empty pad-file contents will be destroyed after volume modifications patch: replaced 6 bytes at offset F69h 0FBA6C24400F -> 0FBA7424400F Image patched  
      6.) You will now find a ***.CAP.patched BIOS-file in the UEFIPatch folder, which is your patched (MSR 0xE2 unlocked) BIOS file.   7.) Rename the ***.CAP.patched BIOS file to X99A2.CAP, the required filename for the ASUS X99-A II BIOS Flashback procedure. Note that the required filename varies for each ASUS mobo. For details see the ASUS BIOS Flashback filename convention.   8.) Copy the X99A2.CAP (or it's derivative in case you use a different ASUS mobo) to a FAT-formatted USB2.0 storage device.   9.) Shut-down your hack, connect the USB2.0 storage device to the USB-port assigned to the ASUS BIOS Flashback procedure (see the mobo manual for details). Press the BIOS-Flashback button for three seconds until the flashback-led starts to blink, indicating that the BIOS Flashback is in progress. Release the button. The locations of the BIOS-Flashback button and the USB-port assigned to the BIOS-Flashback procedure on the ASUS X99-A II are indicated in the figure below:     10.) Wait until the Flashback-led stops blinking and turns off, indicating that the BIOS Flashback process as been successfully completed. You now successfully installed the most actual patched BIOS, compatible with native OSX/MacOS power management.   11.) Boot your system and apply the BIOS settings described below.   For all ASUS X99A-II users, directly download the most actual patched BIOS firmware 1902 with an iMac Pro Splash Screen Boot Image here: X99A2.CAP.   B.2) Asus X99-A II BIOS Configuration   To overclock your RAM memory in concordance with your RAM specifications, enable the EZ XMP Switch on your ASUS Mainboard and enable posteriorly XMP in the Standard ASUS BIOS Setup mode (F7). Subsequently switch from standard to advanced ASUS BIOS Setup mode by pressing again F7.     Important Note:   "ASUS MultiCore Enhancement": When set to "Auto", MCE allows you to maximise the overclocking performance optimised by the ASUS core ratio settings. When disabled, MCE allows to set to default core ratio settings.   "Sync All Cores": Tremendous increase in CPU performance can be achieved with the CPU Core Ratio set to "Sync All Cores". In case of i9-7980XE stock settings (4.4 Ghz, Sync All Cores), the Geekbench score difference is approx. 51.000 (disabled) compared to 58.000 (enabled)! Note however, that Sync All Cores should be used only in case of the availability of an excellent water cooling system! Otherwise, CPU Core Ratio should be set to "Auto". Further note that with CPU Core Ratio set to "Sync All Cores", one might have to set the AVX Instruction Core Ratio Negative Offset to "3" in case of system freezes or system instabilities.   VT-d Note: For compatibility with VM or parallels, VT-d can be also ENABLED... Verify however, in this case that in your config.plist the boot flag "dart=0" is checked under Arguments in the "Boot" Section of Clover Configurator!    Above 4G Decoding Note: I always assumed that the latter BIOS functionality would be mandatory for successfully operating the ThunderboltEX 3 PCie adaptor. This is definitely not the case. Thus in contrary to the BIOS Settings Table above I now rather recommend to DISABLE the latter BIOS functionality (Above 4G Decoding: off), as it also seems to affect the system sleep/wake functionality when enabled.    CPU SVID Support: In addition to the BIOS settings mentioned above one should also Enable CPU SVID support in BIOS Section AI Tweaker, which is fundamental for the proper Intel Power Gadget (IPG) CPU power consumption display.      C.) Important General Note/Advice and Error Prevention   
      Please note the following important General Note / Advice and Error Prevention, when setting up your X99 System by implementing the latest macOS Mojave distribution.
       
      1.) The /EFI/Clover/drivers64UEFI/-directory of EFI-X99-10.14-DP1-Release-iMacPro1,1-160618 contains by default AptioMemoryFix.efi thanks to @vit9696. Note that with Clover_v2.4k_r4392, AptioMemoryFix.efi has become an official Customization Option of Clover and can now be selected and therefore also just easily implemented in the frame of the Clover Boot Loader Installation.
       
      For native NVRAM implementation, Clover's RC Scripts have to be omitted during the clover boot loader installation. If already previously installed, remove Clover's RC Scripts from the /etc directory of your macOS USB Flash Drive Installer or System Disk:
      sudo rm -rf /etc/rc.boot.d sudo rm -rf /etc/rc.shutdown.d  
      Also the "slide" boot flag needs to be disabled.
       
      2.a.) Most ATI GPUs, e.g. RX Vega 64, RX Vega Frontier, RX 580, RX 560 are now natively implemented.  Remaining HDMI/DP port errors, hot plug errors and flaws with multi-monitor or 5K display configurations can be fixed by means of VegaGraphicsFixup.kext, kindly provided by @jyavenard. Important comment for all Vega users with 4K monitors though:  when connecting e.g. the Vega Frontier with e.g. the LG 38UC99-W (WUHD, 3840 pix x 1600 pix) via one of the Display Ports (DPs), the screen resolution is fine under both Windows 10 and macOS High Sierra but is totally at odd during boot (VGA like boot screen resolution). @DSM2 reported similar issues with his true 4K display and with both the ASUS Prime X299 Deluxe and the Gigabyte Designare EX. Thus the VEGA DP 4K boot screen resolution issue is neither related with the fact that the LG 38UC99-W is a ultra-wide (3840x1600) and not a true UHD (3840x2160) monitor nor related to any likely apparent issue with the ASUS Prime X299 Deluxe firmware. It is definitely a Vega firmware problem in combination with 4K displays, as the DP 4K boot screen resolution issue is totally absent with my Nvidia GPU and the problem also does not only affect the ASUS Splash Screen but also spreads over the entire boot process until the login screen is reached (Windows and macOS). Splash Screen, Apple logo or verbose boot messages are not stretched but rather have VGA like resolution. Any fix of the AMD vBIOS would be highly appreciated. It is more than disappointing to witness such issues with 1000$ GPUs... Fortunately, the 4K boot screen issue is restricted to the Vega DP ports and likely due to the fact that the LG 38UC99-W only supports DP 1.2. Solution: Connect your Vega and your 4K display via the HDMI port and everything will work as expected.
       
      b.) Also Nvidia Kepler Graphics Cards are natively implemented. 
       
      c.) All Users with Nvidia Maxwell and Pascal Graphics Cards Users still have to wait for the official release of 10.14 Web Drivers. Over the last weeks, I was actively requesting Web Driver development for macOS 10.14 Betas from Nvidia. I really hope that Nvidia will not leave us again without Web Driver support until the official release of Mojave by September 2018. In the meanwhile, we have to live with e.g. patched Web Driver xxx.35.106 for macOS High Sierra 10.13.5 after a simple patching procedure detailed in Section E.2), although the latter Web Driver is not really suited for 10.14 and just works with strong limitations. 
       
      For further details and error prevention see Section E.2).
       
      3.) The /EFI/Clover/drivers64UEFI/-directory of all former EFI-Folder distributions contained a patched version of the actual apfs.efi. The actual apfs.efi can be obtained by following the respective guideline detailed below:
       
      Right-click with your mouse on the "Install macOS High Sierra.app" and select "Show Package Contents" -> click with the mouse on "Contents" and subsequently on "Shared Support" -> double-click with the mouse on "BaseSystem.dmg" for mounting.   Go to "usr" -> "standalone" -> "i386". Drop the apfs.efi to your Desktop.   To patch the apfs.efi for non-verbose boot, follow THIS LINK. Credits to @PMheart and @ermac.   Note however, that the entire apsf.efi approach detailed above recently has become totally obsolete. Thanks to the ApfsSupportPkg developed by @acidenthera & Co. and thanks to it's recent implementation to Clover (thanks to @Slice, @Philip Petev & Co.) in form of ApsfDriverLoader.efi, there is no further need of the former apsf.efi in the /EFI/Clover/drivers64UEFI/ directory.       The actual Clover distribution package including the ApsfDriverLoader.efi can by build by means of the Build_Clover.command available on Gitub. Since Version 4.8.8, the latter script also can be used with 10.14 and Xcode 10 + Xcode 10 Command Line Tools thanks to @vector sigma. By adding  export PATH="/usr/local/bin:/usr/bin:/bin:/usr/sbin:/sbin" && buildclover to the script,     the latter also can be used in case of Brew, QT5, UEFITool or MacPorts implementations like Latex, X11, gcc, etc. not yet fully compatible with 10.14 Mojave. Again thanks to @vector sigma for also providing/enabling this trick/possibility .    4.) To avoid CPU thread TSC desynchronisation errors during boot and wake from S3, likely induced by yet erroneous CPU BIOS microcode implementations, we need to use TSCAdjustReset.kext provided by @interferenc in the /EFI/CLOVER/kexts/Other/ directory of both USB Flash Drive and System Disk in the latter case.   To access TSCAdjustRest.kext, download primarily its source distribution from Github with the following terminal command: git clone https://github.com/interferenc/TSCAdjustReset Subsequently copy the TSCAdjustRest source distribution to your Desktop using the following terminal command:
      mv /TSCAdjustReset ~/Desktop Now change in the terminal to the TSCAdjustReset source distribution on your Desktop with the following terminal command:
      cd ~/Desktop/TSCAdjustReset/ Now compile the source distribution with Xcode by using the following terminal command:
      xcodebuild After successful compilation, you will find the TSCAdjustRest.kext in ~/Desktop/TSCAdjustReset/build/Release/
        Please note that the TSCAdjustRest.kext by default is configured for a 8-core CPU (16 threads) like the i7-7820X. To adopt the kext for Skylake-X processers with more or less cores than 8 cores, apply the following approach:   a.) Right-click with the mouse on the TSCAdjustRest.kext file and select "Show Packet Contents".   b.) Double-click with the mouse on /contents/ . After a right-click on the "Info.plist" file, select "Open with /Other". Select the TextEdit.app and edit the "Info.plist" file.   c.) Use the "find"-function of TextEdit.app and search for the term "IOCPUNumber"   d.) Note that the adequate IOCPUNumber for your particular CPU is the number of its threads -1, by always keeping in mind that the number of it's threads is always 2x the number of it's cores.   Thus, in case of the 10 core i7-6950X, the IOCPUNumber is 19 (20 threads - 1). <key>IOCPUNumber</key> <integer>19</integer>   and following the same methodology, the correct IOCPUNumber for the 6-core i7-6800K is 11 (12 threads -1) <key>IOCPUNumber</key> <integer>11</integer>   e.) After adopting the IOCPUNumber for your particular Broadwell-E/EP, Haswell-E/EP processor, save the info.plist file and copy the modified VoodooTSCSync.kext to the /EFI/CLOVER/kexts/Other/ - directories of both USB Flash Drive Installer and System Disk!  
      5.) Like under macOS 10.13 High Sierra also with macOS 10.14 Mojave, Apple forces all users to use the new Apple file system APFS in case of a Clean Install.     In case that you want to remain with the HFS+ file system, use @Brumbear's Unsolid.kext in the /EFI/Clover/kexts/Other/ directory.   Note that there is no way to convert an APFS disk back to HFS+ without the loss of all data, but one can easily reformat an APFS formatted disk to HFS+ under OSX by using either Apple's Disk Utility App or "diskutil" commands. All you need to do is to previously unmount the APFS volume before erasing it with a journaled HFS+ file system and a GRUB Partition Table (GTP). If you want to maintain the disk's content, perform a backup before erasing the disk with a HFS+ format.   The application of Apple's Disk utility is straight forward. The  "diskutil" equivalent is detailed below:   In the Terminal app, type: diskutil list In the output which you can read by scrolling back, you will find all internal disks named /dev/disk0, /dev/disk1, depending upon how many physical disks are present in your system.
        Make a note of the disk identifier for the disk you intend to format (you can eliminate risk by removing all disks but the intended target).   In the Terminal app, type: diskutil unmount /dev/diskX where diskX is a place holder for the disk to be unmounted.
        Now delete the APFS container of diskX: diskutil apfs deleteContainer /dev/diskX Subsequently, you can erase the entire disk with HFS+ and a GPT by typing the following terminal command:
      diskutil partitionDisk /dev/diskX 1 GPT jhfs+ "iMacPro" R where /dev/diskX is again a place holder for disk to be erased and iMacPro would be the label for the single partition created. The remaining 1 GPT jhfs+ and R arguments tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and using the entire disk, respectively.
        Alternatively one can also use the following terminal command: diskutil partitionDisk /dev/diskX GPT JHFS+ iMacPro 0b where /dev/diskX is again a place holder for disk to be erased and iMacPro is again the label for the disk partition created. The GPT HFFS+ and 0b arguments again tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and covering the entire disk, respectively.
        In the Terminal app, type now: diskutil mount /dev/diskX where diskX is again a place holder for the disk to be remounted.
        Note, that by means of the "diskutil approach", brand new unformatted or not compatibly formatted system NVMe, SSD and HDD system drives can be also directly formatted within the macOS Clean Install procedure. When presented with the initial install screen where you are presented options to Restore From Backup or Install, select Terminal from the Utilities menu bar item;   The "diskutil" terminal approach is also able to convert a HFS+ macOS Mojave System Disk to APFS. To do so enter the following terminal command: diskutil apfs convert /dev/diskX where diskX is again a place holder for the HFS+ disk to be converted to APFS. The same procedure again can also be directly performed by means of Apple's Disk Utility.
        Important recommendation: If you opt for an APFS System Disk implementation, try to also implement all other disks of your system with APFS file format. On systems with APFS disks and non-APFS disks, the boot duration will increase, as apsf.efi will perform a fsck check of non-AFPS disks (like HFS+ or Fat32) during boot. However, dual boot APFS Systems with an NTFS Windows System Disk are not effected by the apsf.efi issue, as OSX does not know how to properly deal with NTFS.  
      9.) For the proper function of Lilu.kext and Lilu plugins like AppleALC.kext, NvidiaGraphicsFixup.kext, Whatevergreen.kext etc. one also needs to add boot flag "-lilubetaall" to the config.plist during the 10.14 Mojave Betas.
       
      10.) In order to successfully boot your X99 macOS 10.14 Mojave System system, carefully verify that your config.plist contains in Section "KextsToPatch" of Section "Kernel and Kext Patches" of Clover Configurator the 10.14 IOPCIFamily Kext Patch kindly provided by @PMHeart.           D.) iMac macOS 10.14 Mojave System Setup   Below, one finds a detailed description for the Installation/Update of/to macOS Mojave 10.14 DP1 (18A293u). This also includes the EFI-Folder Preparation (D.1), the macOS Mojave 10.14 DP1 (18A293u) Installer Package creation (D.2), the macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer Creation (D.3) and the macOS Mojave 10.14 DP1 (18A293u) Clean Install. One also finds instructions for a direct iMac Pro conversion of a functional Broadwell-E/EP, Haswell-E/EP X99 system with a SMBIOS System Definition different from iMacPro1,1 and standard macOS build implementation (D.5) of any former macOS distribution. D.6 finally provides details to the future iMac Pro macOS Mojave Update Procedure.   D.1) iMac Pro EFI-Folder Preparation    In order to successfully boot a macOS USB Flash Drive Installer or System Disk on a Hackintosh system, both drives must be equipped with an EFI-Folder in their EFI partitions. In this Section we will prepare a fully equipped EFI-Folder with SMBIOS iMacPro1,1 System definition.   1.) Download and unzip EFI-X99-10.14-DP1-Release-iMacPro1,1-160618  and copy the therein contained EFI-Folder to your Desktop.   2.) Open the config.plist in /EFI/Clover/ with the latest version of Clover Configurator (>/= v.4.60.0), proceed to the "SMBIOS" Section and complete the SMBIOS iMacPro1,1 Serial Number, Board Serial Number and SMUUID entries. These details are mandatory to successfully run iMessage and FaceTime on your iMac Pro System. Note that all other iMacPro1,1 SMBIOS Details  are already implemented in the config.plist of EFI-X99-10.14-DP1-Release-iMacPro1,1-160618.   Press several times the "Generate New" Button next to serial number text field.   Open a terminal, enter repeatedly the command "uuidgen", and copy the output value to the SMUUID field in the "SMBIOS" Section of the Clover Configurator.   Depending on your system configuration (Broadwell-E/EP or Haswell-E/EP) change or adopt the following settings if necessary     "FakeCPUID" in "Kernel and Kext Patches" Section of Clover Configurator:   Broadwell-E/EP FakeCPUID: "0x040674"    Haswell-E/EP standard FakeCPUID: "0x0306F2"     All Broadwell-E/EP and Haswell-E/EP users have to enable the Broadwell-E performance Kernel patch for macOS Mojave 10.14 of @PMheart in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator, to overcome persistent OC and performance flaw issues.   a.) Broadwell-E performance Kernel patch Find: C1E30848 63D389D0 48C1EA20 B9990100 000F3048 FF057348 73004883 C4085B5D C30F1F40 00 Replace: B800FF00 004863D3 89D048C1 EA20B999 0100000F 3048FF05 73487300 4883C408 5B5DC390 90   To successfully boot my Broadwell-E X99 System and to obtain full XCPM-performance I also need to include the following Kernel patches:   b.) xcpm_pkg_scope_msrs © Pike R. Alpha (kindly provided by @PMHeart) Find: BE070000 0031D2E8 91FCFFFF Replace: BE070000 0031D290 90909090   c.) _xcpm_SMT_scope_msrs 2 © Pike R. Alpha (kindly provided by @PMHeart) Find: BE0B0000 0031D2E8 66FCFFFF Replace: BE0B0000 0031D290 90909090   Enable "PluginType" in your config.plist under SSDT/Generate Options/ in Section ACPI of Clover Configurator for a fully working XCPM implementation. Note that by this, Pike Alpha's former ssdt.aml XCPM implementation becomes totally obsolete.     Aslo verify once more in concordance with Error Protection C.9) and C.10) that your config.plist contains boot flag "-lilubetaall" and the 10.14 IOPCIFamily kext patch!     Finally save the modified config.plist.   3.) Copy the appropriate TSCAdjustRest.kext, which you modified in error prevention C.4), to the /EFI/CLOVER/kexts/Other/ directory of the EFI-Folder.   You know have a fully equipped EFI-Folder for subsequent implementations as detailed below.   D.2) iMac Pro macOS Mojave 10.14 DP1 (18A293u) Installer Package Creation    To derive the macOS Mojave 10.14 DP1 (18A293u) Full-Package Installer just download and execute macOSDeveloperBetaAccessUtility.dmg and complete the subsequent steps you are asked for.    D.3) iMac Pro macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer Creation    Follow the individual steps detailed below to successfully create a bootable iMac Pro macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer.   1.) Format a USB Flash Drive of your choice (source, named USB) with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on your iMac Pro macOS USB Flash Drive Installer.   2.) With the macOS Mojave 10.14 DP1 (18A293u) Installer Package in your /Application Folder,  connect your USB Flash Drive (named USB) and run the following terminal command: sudo /Applications/Install\ macOS\ 10.14\ Beta.app/Contents/Resources/createinstallmedia --volume /Volumes/USB --nointeraction Alternatively, one can create the iMac Pro macOS USB Flash Drive Installer also by means of the Install Disk Creator.app.
        3.) If your macOS USB Flash Drive Installer is not bootable you can additionally perform the following terminal commands: cd /Volumes/YOUR_USB_VOLUME mkdir .IABootFiles cd .IABootFiles cp /Volumes/YOUR_USB_VOLUME/System/Library/CoreServices/boot.efi . "YOUR_USB_VOLUME" is a place holder in the above commands for the name of your real USB Flash Drive.
        With the terminal command: ls boot.efi you can subsequently verify that boot.efi is there where it should be.
        4.) For successfully booting your iMac Pro macOS USB Flash Drive Installer, the latter must however also contain a valid EFI- Folder with an SMBIOS iMacPro1,1 system definition. Thus, copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition of your macOS USB Flash Drive Installer.   You now have a fully functional and bootable macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer.     D.4) iMac Pro macOS Mojave 10.14 DP1 (18A293u) Clean Install on Broadwell-E/EP, Haswell-E/EP, X99   Follow the individual steps detailed below to successfully setup macOS Mojave 10.14 DP1 (18A293u)  on a virgin system drive of your choice (NVMe, SSD or HDD).   1.) In order to perform a clean install of macOS Mojave 10.14 DP1 (18A293u), prepare a virgin NVMe, SDD or HDD destination drive for the iMac Pro macOS installation by formatting the drive with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on the drive.   2.) Copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition.   3.) Now connect the Destination Drive to your Hackintosh System and boot the latter with the plugged macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer, your created in Section D.2)   4.) While booting your system, press the F8 button to enter the BIOS boot menu. Select to boot from your macOS USB Flash Drive Installer.   5.) Subsequently, click on the USB Flash Drive Installer Icon in the clover boot menu to boot the respective macOS Installer partition on your macOS USB Flash Drive Installer   6.) After successful boot, pass the individual steps of the macOS 10.14 Mojave installation menu and finally select the destination drive of your macOS 10.14 Mojave  Installation, which should be logically the system disk you successfully configured above. In the next step, the Installer will create a macOS Mojave 10.14 Installer Partition on the system disk and subsequently reboot your system.   7.) During system reboot, just press again the F8 button to enter the BIOS boot menu. Select again to boot from your USB Flash Drive. In contrary to 6.), click this time on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS Mojave 10.14 Installer Partition on your system disk.   8.) After successful boot, you will enter now the macOS Mojave 10.14 Installer Screen with a progress bar starting at about 34 minutes.   9.) After another reboot, press again the F8 button to enter the BIOS boot menu. Select to boot with your System Disk EFI-folder. Click on the "MacOS Mojave" icon on the clover boot screen to boot the new macOS Mojave  partition of your system disk.   10.) After successful boot you have to perform the iCloud registration to have your first iMac Pro macOS Mojave 10.14 DP1 (18A293u) build.    Proceed with Section D.6) - iMac Pro macOS High Sierra Build Updates (if necessary) or E.) - Post Installation Process.     D.5) Direct iMac Pro conversions of a functional Broadwell-E/EP, Haswell-E/EP, X99 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation    1.) Replace the EFI-Folder of your System Disk by the EFI-Folder you created in Section D.1)   2.) Copy /System/Library/CoreServices/PlatformSupport.plist to your Desktop, add BoardID "Mac-7BA5B2D9E42DDD94" under SupportedBoardIDs by means of Xcode as suggested by user Griven from the German Hackintosh-Forum and copy back the modified PlatformSupport.plist to System/Library/CoreServices/.   3.) If not already in your /Applications folder after performing Section D.2), copy the iMac Pro macOS Installer Package ("Install macOS 10.14 Beta.app") to your /Applications folder.   4.) Double click on the "Install High Sierra.app" in the /Applications Folder to start the macOS Mojave 10.14 DP1 (18A293u) installation.    5.) After reboot, click on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS Mojave 10.14 Installer Partition on your system disk.   6.) After successful boot, you will enter now the macOS Mojave 10.14 Installer Screen with a progress bar starting at 43 minutes.   7.) After another reboot, click on the "MacOS High Sierra" icon in the clover boot screen to boot the updated macOS Mojave 10.14 on your system disk.   8.) After successful boot you have to register at iCloud at the end of the macOS installation, and you will now have your first iMac Pro macOS Mojave 10.14 DP1 (18A293u) build.   Proceed with Section D.6) - iMac Pro macOS High Sierra Build Updates (if necessary) or Section E.) - Post Installation Process.   D.6) iMac Pro macOS 10.14 Mojave  Update Procedure   If you already used my 10.13 iMacPro X99 guide to setup a 10.13 iMac Pro macOS build, you simply have to update your EFI-Folder and directly perform the update to macOS 10.14 Mojave from System Disk by else following steps 4.) to 8.) of D.5) above. This way you also will also be able to perform any future update of macOS 10.14 Mojave.   Let me conclude with a general recommendation:  In case of macOS beta builds one should clone the macOS System Drive with Carbon Copy Cloner (CCC) to a test drive and to update to the Betas on the latter.    
      E.) Post Installation Process   E.1) XNU CPU Power Management (XCPM) Configuration   The EFI folder of EFI-X99-10.14-DP1-Release-iMacPro1,1-160618, attached towards the end of this post, already contains a fully functional XCPM configuration for the i7-6950X Broadwell-E CPU, which just needs to be adopted for other CPU configurations (Broadwell-E/EP different from i7-6950X, Haswell-E/EP).   Before adapting the XCPM configuration, verify the following BIOS settings:   Advanced\CPU Configuration\CPU Power Management Configuration\ Enhanced Intel SpeedStep Technology (EIST): Disabled Turbo mode: Enabled CPU C-State: Enabled Enhanced C1 State: Enabled CPU C3 Report: Enabled CPU C6 Report: Enabled Package C State Limit: C6(non Retention) state  
      Subsequently, follow the individual steps below.   1.) Open the config.plist of your 10.14 system disk and revise the  "Kernel and Kext Patches" Section.     Verify "FakeCPUID" in "Kernel and Kext Patches" Section of Clover Configurator:   Broadwell-E/EP FakeCPUID: "0x040674"       Haswell-E/EP standard FakeCPUID: "0x0306F2"    All Broadwell-E/EP and Haswell-E/EP users have to enable the Broadwell-E performance Kernel patch for macOS Mojave 10.14 of @PMheart in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator, to overcome persistent OC and performance flaw issues.   a.) Broadwell-E performance Kernel patch Find: C1E30848 63D389D0 48C1EA20 B9990100 000F3048 FF057348 73004883 C4085B5D C30F1F40 00 Replace: B800FF00 004863D3 89D048C1 EA20B999 0100000F 3048FF05 73487300 4883C408 5B5DC390 90   To successfully boot my Broadwell-E X99 System and to obtain full XCPM-performance I also need to include the following Kernel patches:   b.) xcpm_pkg_scope_msrs © Pike R. Alpha (kindly provided by @PMHeart) Find: BE070000 0031D2E8 91FCFFFF Replace: BE070000 0031D290 90909090   c.) _xcpm_SMT_scope_msrs 2 © Pike R. Alpha (kindly provided by @PMHeart) Find: BE0B0000 0031D2E8 66FCFFFF Replace: BE0B0000 0031D290 90909090   Enable "PluginType" in your config.plist under SSDT/Generate Options/ in Section ACPI of Clover Configurator for a fully working XCPM implementation. Note that by this, Pike Alpha's former ssdt.aml XCPM implementation becomes totally obsolete.   All other former XCPM kernel patches have become obsolete also with 10.14   There is also no need for injecting any additional frequency vector.   2.) Reboot after applying any changes.   To verify your XCPM configuration, perform the following steps:   1.) Verify with the terminal command "sysctl machdep.xcpm.mode" if the XCPM mode is active. If so, "sysctl machdep.xcpm.mode" should return "1".   2.) a.) Verify that in the IORegistryExplorer you have now under CP00@0 the following entry: Property:         Type:         Value: plugin-type       Number        0x1  
      b.) Verify with the terminal command kextstat|grep -y x86plat  
      that the "X86PlatformPlugin.kext" is now loaded. If the command returns something like 112    1 0xffffff7f822bc000 0x17000    0x17000    com.apple.driver.X86PlatformPlugin (1.0.0) FD88AF70-3E2C-3935-99E4-C48669EC274B <111 19 18 13 11 7 6 5 4 3 1>  146    1 0xffffff7f822d3000 0x7000     0x7000     com.apple.driver.X86PlatformShim (1.0.0) DCEA94A4-3547-3129-A888-E9D5C77B275E <112 111 13 7 4 3> you are fine.
        c.) Verify with the terminal command [code]kextstat|grep -y appleintelcpu[/code] that you got now rid of the Apple Intel CPU power management. If the result is empty you are fine.
        3.) To verify that the Frequency-Vectors are loaded, use the following terminal command: sysctl -n machdep.xcpm.vectors_loaded_count  
      If everything is ok, the command returns "1".   4.) To obtain further information on your XCPM Power Management configuration, download Piker Alpha’s AppleIntelInfo.kext from Github. To compile the source code, you need to primarily install Xcode (Appstore) and Xcode Command Line Tools! This guideline might be helpful for the  successfully installation of the latter.   Now enter the following terminal commands: cd ~/Downloads/AppleIntelInfo-master xcodebuild cd build/Release chmod -R 755 AppleIntelInfo.kext sudo chown -R root:wheel AppleIntelInfo.kext  
      Load the AppleIntelInfo.kext with "kextload" and "cat" the info-results with the following terminal commands: sudo kextload AppleIntelInfo.kext sudo cat /tmp/AppleIntelInfo.dat  
      The cat command should reveal something like the following result: AppleIntelInfo.kext v2.5 Copyright © 2012-2017 Pike R. Alpha. All rights reserved. Settings: ------------------------------------------ logMSRs..................................: 1 logIGPU..................................: 0 logCStates...............................: 1 logIPGStyle..............................: 1 InitialTSC...............................: 0x11d3a1760ecb2 (10453 MHz) MWAIT C-States...........................: 8480 Processor Brandstring....................: Intel(R) Core(TM) i7-6950X CPU @ 3.00GHz Processor Signature..................... : 0x406F1 ------------------------------------------  - Family............................... : 6  - Stepping............................. : 1  - Model................................ : 0x4F (79) Model Specific Registers (MSRs) ------------------------------------------ MSR_CORE_THREAD_COUNT............(0x35)  : 0x0 ------------------------------------------  - Core Count........................... : 10  - Thread Count......................... : 20 MSR_PLATFORM_INFO................(0xCE)  : 0x20080C3BF3811E00 ------------------------------------------  - Maximum Non-Turbo Ratio.............. : 0x1E (3000 MHz)  - Ratio Limit for Turbo Mode........... : 1 (programmable)  - TDP Limit for Turbo Mode............. : 1 (programmable)  - Low Power Mode Support............... : 1 (LPM supported)  - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)  - Maximum Efficiency Ratio............. : 12  - Minimum Operating Ratio.............. : 8 MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x1E000005 ------------------------------------------  - I/O MWAIT Redirection Enable......... : 0 (not enabled)  - CFG Lock............................. : 0 (MSR not locked)  - C3 State Auto Demotion............... : 1 (enabled)  - C1 State Auto Demotion............... : 1 (enabled)  - C3 State Undemotion.................. : 1 (enabled)  - C1 State Undemotion.................. : 1 (enabled)  - Package C-State Auto Demotion........ : 0 (disabled/unsupported)  - Package C-State Undemotion........... : 0 (disabled/unsupported) MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x10414 ------------------------------------------  - LVL_2 Base Address................... : 0x414  - C-state Range........................ : 1 (C-States not included, I/O MWAIT redirection not enabled) IA32_MPERF.......................(0xE7)  : 0xACF485063 IA32_APERF.......................(0xE8)  : 0xB96AC7BB7 MSR_0x150........................(0x150) : 0x0 MSR_FLEX_RATIO...................(0x194) : 0xE0000 ------------------------------------------ MSR_IA32_PERF_STATUS.............(0x198) : 0x204900001E00 ------------------------------------------  - Current Performance State Value...... : 0x1E00 (3000 MHz) MSR_IA32_PERF_CONTROL............(0x199) : 0x2A00 ------------------------------------------  - Target performance State Value....... : 0x2A00 (4200 MHz)  - Intel Dynamic Acceleration........... : 0 (IDA engaged) IA32_CLOCK_MODULATION............(0x19A) : 0x0 IA32_THERM_INTERRUPT.............(0x19B) : 0x0 IA32_THERM_STATUS................(0x19C) : 0x883D0000 ------------------------------------------  - Thermal Status....................... : 0  - Thermal Log.......................... : 0  - PROCHOT # or FORCEPR# event.......... : 0  - PROCHOT # or FORCEPR# log............ : 0  - Critical Temperature Status.......... : 0  - Critical Temperature log............. : 0  - Thermal Threshold #1 Status.......... : 0  - Thermal Threshold #1 log............. : 0  - Thermal Threshold #2 Status.......... : 0  - Thermal Threshold #2 log............. : 0  - Power Limitation Status.............. : 0  - Power Limitation log................. : 0  - Current Limit Status................. : 0  - Current Limit log.................... : 0  - Cross Domain Limit Status............ : 0  - Cross Domain Limit log............... : 0  - Digital Readout...................... : 61  - Resolution in Degrees Celsius........ : 1  - Reading Valid........................ : 1 (valid) MSR_THERM2_CTL...................(0x19D) : 0x0 IA32_MISC_ENABLES................(0x1A0) : 0x850089 ------------------------------------------  - Fast-Strings......................... : 1 (enabled)  - FOPCODE compatibility mode Enable.... : 0  - Automatic Thermal Control Circuit.... : 1 (enabled)  - Split-lock Disable................... : 0  - Performance Monitoring............... : 1 (available)  - Bus Lock On Cache Line Splits Disable : 0  - Hardware prefetch Disable............ : 0  - Processor Event Based Sampling....... : 0 (PEBS supported)  - GV1/2 legacy Enable.................. : 0  - Enhanced Intel SpeedStep Technology.. : 1 (enabled)  - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)  - Adjacent sector prefetch Disable..... : 0  - CFG Lock............................. : 0 (MSR not locked)  - xTPR Message Disable................. : 1 (disabled) MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x640A00 ------------------------------------------  - Turbo Attenuation Units.............. : 0  - Temperature Target................... : 100  - TCC Activation Offset................ : 0 MSR_MISC_PWR_MGMT................(0x1AA) : 0x402000 ------------------------------------------  - EIST Hardware Coordination........... : 0 (hardware coordination enabled)  - Energy/Performance Bias support...... : 1  - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)  - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores) MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x2A2A2A2A2A2A2A2A ------------------------------------------  - Maximum Ratio Limit for C01.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C02.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C03.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C04.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C05.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C06.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C07.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C08.......... : 2A (4200 MHz) MSR_TURBO_RATIO_LIMIT1...........(0x1AE) : 0x2222222222222A2A ------------------------------------------  - Maximum Ratio Limit for C09.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C10.......... : 2A (4200 MHz) IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x5 ------------------------------------------  - Power Policy Preference...............: 5 (balanced performance and energy saving) MSR_POWER_CTL....................(0x1FC) : 0x2904005B ------------------------------------------  - Bi-Directional Processor Hot..........: 1 (enabled)  - C1E Enable............................: 1 (enabled) MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03 ------------------------------------------  - Power Units.......................... : 3 (1/8 Watt)  - Energy Status Units.................. : 14 (61 micro-Joules)  - Time Units .......................... : 10 (976.6 micro-Seconds) MSR_PKG_POWER_LIMIT..............(0x610) : 0x7FFF80015FFF8 ------------------------------------------  - Package Power Limit #1............... : 4095 Watt  - Enable Power Limit #1................ : 1 (enabled)  - Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)  - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)  - Package Power Limit #2............... : 4095 Watt  - Enable Power Limit #2................ : 1 (enabled)  - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)  - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)  - Lock................................. : 0 (MSR not locked) MSR_PKG_ENERGY_STATUS............(0x611) : 0xC06AC ------------------------------------------  - Total Energy Consumed................ : 48 Joules (Watt = Joules / seconds) MSR_PKGC3_IRTL...................(0x60a) : 0x0 MSR_PKGC6_IRTL...................(0x60b) : 0x0 MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x298ED1EE0 MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0xD638F0 MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x298ED1EE0 MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0xD638F0 MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x44911A9AC IA32_TSC_DEADLINE................(0x6E0) : 0x11D3A1BDB3826 CPU Ratio Info: ------------------------------------------ Base Clock Frequency (BLCK)............. : 100 MHz Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz) Maximum non-Turbo Ratio/Frequency........: 30 (3000 MHz) Maximum Turbo Ratio/Frequency............: 42 (4200 MHz) P-State ratio * 100 = Frequency in MHz ------------------------------------------ CPU P-States [ (12) 27 30 ] CPU C3-Cores [ 1 2 4 6 8 10 12 14 16 18 ] CPU C6-Cores [ 0 2 4 6 8 10 12 14 16 18 ] CPU P-States [ 12 17 27 (30) ] CPU C3-Cores [ 1 2 3 4 6 7 8 10 11 12 14 15 16 18 19 ] CPU C6-Cores [ 0 2 4 6 8 9 10 12 14 16 17 18 ] CPU P-States [ (12) 17 27 30 31 ] CPU C3-Cores [ 0 1 2 3 4 6 7 8 9 10 11 12 14 15 16 18 19 ] CPU P-States [ (12) 14 17 27 30 31 ] CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 ] CPU C6-Cores [ 0 2 4 6 8 9 10 12 14 15 16 17 18 ] CPU P-States [ (12) 14 17 20 27 30 31 ] CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ] CPU C6-Cores [ 0 1 2 4 6 7 8 9 10 12 14 15 16 17 18 ] CPU P-States [ (12) 14 16 17 20 27 30 31 ] CPU P-States [ (12) 14 16 17 18 20 27 30 31 ] CPU P-States [ (12) 14 16 17 18 20 27 30 31 32 ] CPU P-States [ (12) 14 16 17 18 20 22 27 30 31 32 ] CPU C6-Cores [ 0 1 2 3 4 6 7 8 9 10 12 14 15 16 17 18 ] CPU P-States [ (12) 13 14 16 17 18 20 22 27 30 31 32 ] CPU C6-Cores [ 0 1 2 3 4 6 7 8 9 10 12 13 14 15 16 17 18 19 ] CPU P-States [ (12) 13 14 16 17 18 20 22 23 27 30 31 32 ] CPU P-States [ 12 13 14 (15) 16 17 18 20 22 23 27 30 31 32 ] CPU P-States [ (12) 13 14 15 16 17 18 20 22 23 25 27 30 31 32 ] CPU P-States [ (12) 13 14 15 16 17 18 20 21 22 23 25 27 30 31 32 ] CPU C6-Cores [ 0 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ] CPU P-States [ 12 13 14 15 16 17 18 20 21 22 23 (24) 25 27 30 31 32 ] CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 30 31 32 ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 29 (30) 31 32 ] CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 36 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 36 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 41 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 41 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 38 41 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 38 39 41 (42) ] CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 ] CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 (42) ]  
      To unload the AppleIntelInfo.kext, enter the terminal command: sudo kextunload AppleIntelInfo.kext  
      E.2) Graphics Configuration
       
      Most ATI GPUs, e.g. RX Vega 64, RX Vega Frontier, RX 580, RX 560 are now natively implemented.  Remaining HDMI/DP port errors, hot plug errors and flaws with multi-monitor or 5K display configurations can be fixed by means of VegaGraphicsFixup.kext, kindly provided by @jyavenard. Important comment for all Vega users with 4K monitors though:  when connecting e.g. the Vega Frontier with e.g. the LG 38UC99-W (WUHD, 3840 pix x 1600 pix) via one of the Display Ports (DPs), the screen resolution is fine under both Windows 10 and macOS High Sierra but is totally at odd during boot (VGA like boot screen resolution). @DSM2 reported similar issues with his true 4K display and with both the ASUS Prime X299 Deluxe and the Gigabyte Designare EX. Thus the VEGA DP 4K boot screen resolution issue is neither related with the fact that the LG 38UC99-W is a ultra-wide (3840x1600) and not a true UHD (3840x2160) monitor nor related to any likely apparent issue with the ASUS Prime X299 Deluxe firmware. It is definitely a Vega firmware problem in combination with 4K displays, as the DP 4K boot screen resolution issue is totally absent with my Nvidia GPU and the problem also does not only affect the ASUS Splash Screen but also spreads over the entire boot process until the login screen is reached (Windows and macOS). Splash Screen, Apple logo or verbose boot messages are not stretched but rather have VGA like resolution. Any fix of the AMD vBIOS would be highly appreciated. It is more than disappointing to witness such issues with 1000$ GPUs... Fortunately, the 4K boot screen issue is restricted to the Vega DP ports and likely due to the fact that the LG 38UC99-W only supports DP 1.2. Solution: Connect your Vega and your 4K display via the HDMI port and everything will work as expected.
       
      Also Nvidia Kepler Graphics Cards are natively implemented. 
       
      All Users with Nvidia Maxwell and Pascal Graphics Cards Users still have to wait for the official release of 10.14 Web Drivers. Over the last weeks, I was actively requesting Web Driver development for macOS 10.14 Betas from Nvidia. I really hope that Nvidia will not leave us again without Web Driver support until the official release of Mojave by September 2018. In the meanwhile, we have to live with e.g. patched Web Driver xxx.35.106 for macOS High Sierra 10.13.5 after a simple patching procedure detailed below, although the latter Web Driver is not really suited for 10.14 and just works with strong limitations. 
       
      How to patch an Nvidia WebDriver:   Download the Nvidia WebDriver-Payload Repackager from InsanelyMac. Credits to @Chris111 and @Pavo.    The patch procedure is simple and fully described in the implemented Readme.txt and will reveal a Repackaged-WebDriver.pkg, which can be used for installing the patched Nvidia Web Driver xxx.35.106 under macOS Mojave 10.14 DP1 (18A293u).   Nvidia Web Driver Installation and Black Screen Prevention:   Apparently with SMBIOS iMacPro1,1, the Nvidia Black Screen Prevention has become obsolete. Thanks to @fabiosun for this finding. Thus, NvidiaGraphicsFixup.kext, subverting AppleMobileFileIntegrity banning the driver can be theoretically removed from the /EFI/CLOVER/kexts/Other/ directory of your macOS Flash Drive Installer and 10.13 System Disk. However, the most actual releases of NvidiaGraphicsFixup.kext v.1.2.7 and Lilu.kext v1.2.3 apparently help in fixing the Nvidia HDAU implementation and sporadic black screen issues while wake from sleep. Thus, the latter kext combination might still represent potential workarounds for few likely remaining system issues.      a.) Install the patched Nvidia 10.13 Web Driver Package.   b.) Now perform the following additional steps:   i.) Copy /L/E/NVDAStartupWeb.kext to your Desktop.   ii.) Right-click on NVDAStartupWeb.kext and select show package content.   iii.) Change to "Contents" and edit the "Info.plist" with Xcode.   iv.) Go to IOKitPersonalities -> NVDAStartup -> change "NVDARequiredOS" from "17F77" to "18A293u", the corresponding build number of MacOS Mojave 10.14 DP1.   v.) Save the "Info.plist" file and copy the modified "NVDAStartupWeb.kext" to /L/E/ with root permission.   vi.) Open a terminal and enter the following commands: sudo chmod -R 755 /Library/Extensions/NVDAStartupWeb.kext sudo chown -R root:wheel /Library/Extensions/NVDAStartupWeb.kext sudo touch /System/Library/Extensions && sudo kextcache -u / sudo touch /Library/Extensions && sudo kextcache -u /  
      vii.) Reboot.
        viii.) The patched Web Driver might not be active yet. Therefore, open the Nvidia Driver Manager and select "Nvidia Web Driver".   ix.) Now reboot as requested and you will have a fully functional patched Web Driver for MacOS Mojave 10.14 DP1 (18A293u).  
       
      E.3) Audio Configuration
       
      EFI-X99-10.14-DP1-Release-iMacPro1,1-160618 contains an already fully functional AppleALC audio configuration. The latter consist of:
       
      1.) codeccommander.kext,  AppleALC.kext v1.2.7 and Lilu.kext v1.2.3 in "/EFI/CLOVER/kexts/Other/
       
      2.) Boot flags "-alcbeta", "alcid=5", "alcaaplid=5", and "-lilubetaall" in the config.plist under "Custom Flags" in Section "Boot" of Clover configurator. 
       
       
       
      3.)  ALZA -> HDEF "DSDT patch" in the config.plist in Section "ACPI" of Clover Configurator 
      Comment:                Find:           Replace: ALZA -> HDEF     414c5a41        48444546 Note that in Section 9.2), we will implement this ACPI replacement directly in the system-SSDT. By then, the DSDT patch detailed above needs to be removed from the config.plist. 
       
      4.) Audio ID Injection "5" in the config.plist under Audio/Inject in Section "Devices" of Clover Configurator. 
          This audio configuration provides a correct analogue onboard audio chipset system implementation.    The correct digital HDMI/DP HDAU PCI device implementation will be detailed in Section E.9) in line with the HDEF and GPU PCI device implementation.   Thanks to @nmano for helping me with the initial AppleALC audio setup for 10.14 Mojave.   
      E.4) USB Configuration    With AppleIntelPCHPMC, Apple should properly implement all external and internal XHC USB 3.0 (USB 3.1 Gen 1 Type-A) and USB 2.0 (USB 2.0 Gen 1 Type-A) ports.  All external and internal USB 3.1 (USB 3.1 Gen 2 Type-A and Type-C) ports are natively implemented on different controllers than XHC.   All ASUS A99-A II users, not content with the XHC USB implementation,  can download, unzip and use my board-specific XHC USB Kext KGP-ASUS-X99-A-II-iMacPro-XHCI.kext.zip in /EFI/Clover/kexts/Other/. All users of mainboards different from the ASUS X99-A II, can create their own board specific XHC USB kext by following my XHC USB Kext Creation guide line in the other forum.    Note that in addition one needs to implement the XHC USB port limit patch in the config.plist under "KextsToPatch"  in Section "Kernel and Kext Patches" of Clover Configurator, as else not all available XHC USB ports will be implemented. Name*          Find*[Hex]             Replace* [Hex]         Comment com.apple.driver.usb.AppleUSBXHCI   83FB0F0F 83090500 00   83FB0F90 90909090 90   USB Port Limit Patch ©PMHeart Many thanks to @PMheart from InsanelyMac for providing the respective 10.14 XHC USB port limit patch detailed above.
       
       
      E.5) M.2/NVMe Configuration
       
      In contrary to macOS Sierra 10.12, and like already in case of macOS High Sierra 10.13, also macOS 10.14 Mojave provides native support of non-4Kn NVMe SSDs, like my Samsung EVO 960 M.2/NVMe. All patches applied under macOS Sierra 10.12 are obsolete. The native support of non-4Kn NVMe SSDs enables the unique opportunity to directly perform a clean-install of macOS High Sierra 10.13 on M.2 NVMEs like the Samsung EVO 960.   The only current drawback consists in the external drive implementation of NVMEs. This minor issue should be easily solved by adding the actual External NVME Icon KextToPatch entry to the config.plist by means of the Clover Configurator. [code] Name*            Find* [HEX]           Replace* [HEX]        Comment IONVMeFamily     4885c074 07808b20     4885c090 90808b20     External NVME Icon Patch[/code] Not however that within the actual 10.14 Mojave distribution, this approach does not seem to work anymore, despite the KextToPatch entry detailed above. If you still have your NVMe implemented in form of an external drive you have to perform the following workaround, detailed below.
        1.) Disable the not working External NVME Icon KextToPatch entry.   2.) Open the IORegistryExplorer, in the upright search field type nvme and take not of values in the left column, i.e. indicated as v.1, v.2 and v.3 and marked by red rectangles in the figure below. As you can see by following these entries, your nvme device shows up in PCI0@0 > BR1B@1,1 > H000@0     3.) Download and unzip the SSDT-NVMe-extern-icon-patch.aml.zip, and open the SSDT-NVMe-extern-icon-patch.aml with MaciASL-DSDT.app, both attached towards the end of this guide. For deviating system configurations, replace the values highlighted in blue color in the figure below with those of your IOReg, marked by red rectangles and indicated by v.1, v.2 and v.3 in the figure of my IOReg above.     4.) Save and copy the modified SSDT-NVMe-extern-icon-patch.aml to the /EFI/CLOVER/ACPI/patched/ folder of your system drive.   5.) Reboot   Now your NVMe drive should correctly show up as internal.  
       
      E.6) SSDT/NVMe TRIM Support 
        Macs only enable TRIM for Apple-provided solid-state drives they come with. If you upgrade a Mac with an aftermarket SSD/NVMe, the Mac won’t use TRIM with it. The same applies for SSDs/NVMes used by a Hackintosh. When an operating system uses TRIM with a solid-state drive, it sends a signal to the SSD/NVMe every time you delete a file. The SSD/NVMe knows that the file is deleted and it can erase the file’s data from its flash storage. With flash memory, it’s faster to write to empty memory — to write to full memory, the memory must first be erased and then written to. This causes your SSD/NVMe to slow down over time unless TRIM is enabled. TRIM ensures the physical NAND memory locations containing deleted files are erased before you need to write to them. The SSD/NVMe can then manage its available storage more intelligently.   Note that the config.plist in the EFI-folder of EFI-X99-10.14-DP1-Release-iMacPro1,1-160618 attached towards the end of this guide, contains an SSD/NVMe "TRIM Enabler" KextsToPatch entry, which can be found in the " Kernel and Kext Patches" Section of the Clover Configurator.     Name*                   Find*[HEX]                  Replace*[HEX]               Comment IOAHCIBlockStorage      4150504c 45205353 4400      00000000 00000000 0000      Trim Enabler  
      With this KextToPatch entry, SSD/NVMe TRIM should be  fully enabled on your 10.13 System. See your Apple's System Report.  
      E.7) Thunderbolt EX 3 PCIe Add-On Implementation 
       
       
      For the successful implementation of the Thunderbolt EX3 PCIe Add-On Adapter, a fully working Dual Boot System with an UEFI Windows Implementation is unfortunately absolutely mandatory. You will not be able to configure your Thunderbolt EX3 PCIe Add-On Adapter in the mainboard BIOS, until the Adapter has been successfully recognised and initialised by the UEFI Windows System. Fortunately legal and official License Keys for the actual Windows 10 Pro distribution can be purchased with a little bit of temporal effort on Google for an actual price of 20 $ or even below! Thus, the installation of a dual boot system with Windows will require some additional temporal user effort but will not noticeably further affect the users's budget.   Please note that I especially emphasize the term UEFI, when speaking about the parallel Windows implementation. Don't use or perform a Legacy Implementation of Windows! In order to properly implement your Windows partition later-on in the Clover Bootloader and to comply with the actual Mainbaord-BIOS settings requirements, it is absolutely mandatory to run or perform an UEFI Windows implementation!   So if not already implemented, how to achieve a fully working UEFI Windows Implementation and Dual boot System with Windows?   1.) Important Note! For the implementation of the UEFI Windows Distribution disconnect all usually plugged macOSDrives from your rig! The Windows installer will implement a Windows Boot Loader! If you have any macOS Drive connected during installation, the latter Windows Boot Loader might overwrite and destroy your current Clover Boot Loader. This is the last thing you want! Thus for the windows installation just connect the destination drive for the installation and the Windows USB Flash Drive Installer your will create in the subsequent step below!   2.) This Tutorial explains in all necessary detail how to download an actual Windows 10 Creator distribution,  and how tosubsequently create a bootable USB Flash Drive Installer for a subsequent UEFI Windows 10 installation by means RUFUS! Don't put emphasis on alternative optional methods and always take care that you just follow the instructions for a successful subsequent UEFI Windows Installation!   3.) This Tutorial explains in all necessary detail how to properly perform the actual Windows 10 Pro Creator UEFIInstallation, subsequent to the a bootable Windows USB Flash Drive Installer realisation detailed in 2.) above.   4.) This Tutorial explains in all necessary detail, how to migrate/clone/backup your Windows 10 UEFI System Disk afterinstallation for future maintenance and safety.   5.) After successfully performing the UEFI Windows 10 Pro Creator Implementation, you can reconnect your macOS driveto your rig. The newly created UEFI Windows 10 Pro Creator Partition will automatically appear as a further boot option in both BIOS Boot Option Menu (F8) and Clover Boot Menu! No additional or further actions or measurements have to be taken!   6.) Once your Windows 10 Pro Creator Partition is fully operational, install all mainboard drivers and programs implemented on the DVD attached to your mainboard.    7.) Now switch of your rig and start with the installation of the Thunderbolt EX3 PCIe Add-On Adapter   a.) I recommend to install the adapter in third PCIe Slot from the bottom which is PCIEX_3   b.) For full TB hot plug functionality skip or remove the THB_C cable between the TBEX 3 and the respective mainboard connector.   8.) Reboot into windows and install the ASUS ThunderboltEX 3 DVD.   9.) Reboot and enter the Mainboard BIOS (F2)   Go to /Advanced/ Thunderbolt(TM) Configuration/ and apply the following BIOS Settings detailed below:     10.) Shut down your rig, connect the Thunderbolt Device with the Thunderbolt EX3 Adaptor and boot   11.) You are done!  Your Thunderbolt EX3 PCIe Adapter and connected devices should be now fully implemented and functional.   12.) We will add TB XHC USB and TB Hot Plug functionality by means of the SSDT-TB3-iMacPro-KGP.aml.zip implemented and described in Section E.9.3) of this guide.   E.8) Gigabit and 10-Gbit Ethernet Implementations    Section E.8.1) and and E.8.2.) below, describe in all necessary detail how to gain full Gbit and 10-Gbit LAN functionality on X99 systems.  
      E.8.1) ASUS X99-A onboard Gbit functionality   
       
      The Intel I218-V2 Gigabit on-board LAN controller of the ASUS X99-A II is implemented by means of IntelMausiEthernet.kext (already part of my EFI-Folder distributions).
       
      E.8.2) 10-Gbit Lan Implementations  
       
      E.8.2.1) ASUS XG-C100C Aquantia AQC 10-Gbit NIC   
       
      Starting with 10.13.2, there is native support for Aquantia based 10GBit network cards, which are implemented by means of a Apple Vanilla kext called "AppleEthernetAquantiaAqtion.kext", which is further part of "IONetworkingFamily.kext/Contents/PlugIns/" placed in  /System/Library/Extensions/ (credits to @mikeboss). First success with the ASUS XG-C100C under MacOS 10.13.3 has been reported by @d5aqoep. @Mieze finally came up with a AppleEthernetAquantiaAqtion KextPatch for the use of the ASUS XG-C100C also under 10.13.4 and and later macOS versions.   For further information and discussion see  . 
      How to successfully implement the ASUS XG-C100C AQC107 PCIe x4 10GBit Ethernet Adapter:   1.) A temporal macOS High Sierra 10.13.3 (17D2047 in case of the iMac Pro) installation is absolutely mandatory at first place. Only within the latter macOS High Sierra build, the ASUS XG-C100C will receive the proper AQC107 Apple firmware to be recognised and fully implemented by OSX. The firmware update will be performed during system boot. Several boot intents might be necessary until the firmware update finally succeeds. Only subsequently, the ASUS XG-C100C will be natively implemented in macOS High Sierra 10.13.3 and fully functional.   2.) To finally use the ASUS XG-C100C with macOS builds >10.13.4, one has to implement the following AppleEthernetAquantiaAqtion KextPatch provided by [USER=389154]@Mieze[/USER]:     Name*                            Find*[HEX]         Replace*[HEX]      Comment AppleEthernetAquantiaAqtion      0F84C003 0000      90909090 9090      Aquantia patch ©Mieze     3.) The proper XGBE ASUS XG-C100C PCI SSDT implementation is detailed in Section E.9.2)   4.) Note that after the firmware update under macOS High Sierra 10.13.3, the ASUS XG-C100C will refuse the official Windows Lan drivers provided by ASUS and will only work with Apple's customised Aquantia64.zip boot camp drivers attached below.   E.8.2.2) Intel X540-T1 10-Gbit NIC      Thanks to some Ubuntu EEPROM modding, I also achieved the successful implementation of the Intel X540-T1 single port 10GB LAN PCIe Adapter by means of the Small-Tree 10GB macOS 10.13 driver.   Important additional notes to the EEPROM modding guideline linked above can be assessed in Section E.8.2.2) of my iMac Pro Skylake-XX299 macOS 10.14 Mojave Build and Desktop guide.   The proper Intel X540-T1 PCI SSDT implementation is detailed in Section E.9.2)   E.8.2.3) Small-Tree P2EI0G-2T 10-GBit NIC     
      The Small-Tree P2EI0G-2T 2-Port 10GB LAN PCIe Adapter constitutes now the actual base line in my iMac Pro X299 10Gbit LAN configuration. It works OoB with the Small-Tree 10GB macOS 10.13 driver.   The proper Small-Tree P2EI0G-2T PCI SSDT implementation is detailed in Section E.9.2)   E.8.2.4) NetGear ProSave XS508M 8-port 10-Gbit Switch     
      As already mentioned above, the NetGear ProSave XS508M 8-port 10GBit switch constitutes the turntable of my 10-GBit Ethernet Network. It further connects with a QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port.
       
      E.8.2.5) QNAP TS-431X2 Quad-core 4-Bay NAS
       
      The QNAP TS-431X2 Quad-core 4-Bay NAS tower finally harbours 4x 12 TB Seagate IronWolf drives in RAID 0 configuration (as I rather opt for read/write speed than redundancy).
       
      E.8.2.5) 10-Gbit Ethernet Optimization
       
      1.) Use SMB 3.0 instead of AFS for your Ethernet communication. 2.) Enable Jumbo Frames on your NAS and macOS network settings. 3.) The service order in your macOS network settings should have your 10-Gbit NIC at first position. 4.) You can turn off the SMB packet signing of the client and server in a secure network.   Incoming SMB   Enter the following terminal commands: sudo -s
 echo "[default]" >> /etc/nsmb.conf 
echo "signing_required=no" >> /etc/nsmb.conf 
exit  
      Outgoing SMB:   Enter the following terminal commands: smbutil statshares -a sudo defaults write /Library/Preferences/SystemConfiguration/com.apple.smb.server SigningRequired 0  
       
      E.9) ASUS X99-A II PCI Device Implementation
       
      In order to properly implement all PCI device drivers on his/her system and build, one needs adequate ACPI DSDT Replacements and a sophisticated SSDT. Both requirements have been originally successfully implemented for the ASUS Prime X299 Deluxe by our gorgeous @apfelnico with partial contributions of @TheOfficialGypsy. Many thanks for the extensive efforts and extremely fruitful and brilliant work! Subsequently, I adopted the ACPI DSDT Replacement Patches and SSDT in concordance with SMBIOS iMacPro1,1 for both the ASUS Prime X299 Deluxe and the ASUS X99-A II. The actual ASUS X99-A II ACPI DSDT Replacements are part of the config.plist contained in EFI-X99-10.14-DP1-Release-iMacPro1,1-160618. The SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml for the ASUS X99-A II, further developed with @apfelnico and @nmano, are attached at the bottom of this originating post/guide.   Note that the ACPI DSDT Replacements, SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml can be build and PCIe slot population dependend and have to be verified and likely adopted or modified for all mainboards different from the ASUS X99-A II and builds or PCIe slot populations different from the one that constitutes the baseline of this guide.   For the ASUS X99-A II I will use in the following the PCIe Slot nomenclature depicted below:  

       
      The verification and likely adaptation/modification can be performed by the help of IORegistryExplorer v1.2.
       
      Important Note: It is strongly recommend to perform a stepwise PCI Device implementation by means of a minimalistic starter SSDT-X99-iMacPro.aml, which just contains the Definition Block and Device Implementation for one single specific device. Once this PCI device has been successfully implemented, other PCI Device definitions can be added to the SSDT-X99-iMacPro.aml. In case that subsequently the implementation of a specific PCI Device would be erroneous and fail, also all other already successfully implemented PCI devices would disappear from Section "PCI" of Apple's System report and the entire "PCI" Device implementation would fail. Thus a stepwise PCI device implementation/adaptation is highly recommended and sometimes deemed necessary!
       
      Also keep always in mind to modify/adopt the ACPI replacements in your config.plist in parallel when ever necessary!   Note once more that the ACPI DSDT Replacements, SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml detailed below require SMBIOS iMacPro1,1.   E.9.1) ACPI DSDT Replacement Implementation  
      Note once more that all required ACPI DSDT Replacements are already implemented in the config.plist in the /EFI/CLOVER/ directory of the EFI-Folder contained in EFI-X99-10.14-DP1-Release-iMacPro1,1-160618 or are directly part of the SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml. In the config.plist, the ACPI DSDT Replacements are disabled by default, thus we will now open the config.plist in the /EFI/CLOVER/ directory of your 10.13 System Disk EFI-Folder with Clover Configurator and stepwise adopt (if necessary) and enable the different required DSDT replacement patches in Clover Configurator Section "ACPI" under "DSDT patches", by also discussing their respective function and impact.   a.) OSI -> XOSI and EC0_ -> EC__ or H_EC  -> EC__ are DSDT replacement patches to achieve consistency with a real Mac variable naming.   i.) The XOSI functionality is required as explained by @RehabMan. Thus please enable the OSI -> XOSI DSDT Replacement patch.   ii.) On the ASUS X99-A II and ASUS X99 Deluxe II we have EC0 and H_EC controllers, which have to be renamed to 'EC' for proper USB power management. Thus enable both EC0_ -> EC__  and H_EC  -> EC__ DSDT Replacement Patches. Comment:             Find*[Hex]      Replace [Hex] OSI -> XOSI          5f4f5349        584f5349 EC0_ -> EC__         4543305f        45435f5f H_EC  -> EC__        485f4543        45435f5f  
      b.) The HEC1 -> IMEI and IDER->MEID DSDT Replacement patches are Intel Management Engine Interface related and are vital as MacOS requires the variable names "IMEI" and "MEID" to load the 'AppleIntelMEIDriver'. The latter functionality solves the 'iTunes/Apple Store Content Access Problem' which is discussed here. Please enable now both DSDT Replacement patches independent from your mainboard. Comment:             Find*[Hex]       Replace [Hex] HECI -> IMEI         48454331         494d4549 IDER->MEID           49444552         4d454944  
      c.) The LPC0 -> LPCB DSDT Replacement Patch is AppleLPC and SMBus related and is applied for consistency with the variable naming on a real Mac.   Please enable now this DSDT replacement patch independent from your mainboard. Comment:             Find*[Hex]         Replace [Hex] LPC0 -> LPCB         4c504330           4c504342  
      d.) FPU_->MATH, TMR_->TIMR, PIC_->IPIC are all DSDT Replacement Patches for consistency with the variable naming on a real Mac. The variables are however functionless on either X99 systems or real Macs.   Please enable now all three DSDT Replacement Patches independent from your mainboard. Comment:             Find*[Hex]        Replace [Hex] FPU_ -> MATH         4650555f          4d415448 TMR_ -> TIMR         544d525f          54494d52 PIC_ -> IPIC         5049435f          49504943  
      e.) The DSM -> XDSM DSDT replacement patch will be vital for loading the SSDT-ASUS-X99-A-II.aml, as all DSM methods used in the original DSDT do have a not compatible structure totally different from the real Mac environment. Without any fix, all DSM methods would be simply ignored. Note that one single device can have only one DSM method, which can assign additional properties to the respective device. Thus please enable the latter DSDT replacement patch completely independent from your mainboard! Comment:             Find*[Hex]         Replace [Hex] _DSM -> XDSM         5f44534d            5844534d  
      f.) The 48 CPxx -> PRxx replacements are i7-6950X specific and result in a proper CPU core reordering as well as in a iMac Pro specific CPU core variable naming.   All i7-6950X users can now enable all 48 CPxx -> PRxx replacements. All users of CPUs different from the i7-6950X have to adopt/modify the 48 CPxx -> PRxx replacements in concordance with their original IOREG CPU core values. Comment:             Find*[Hex]        Replace [Hex] CP00 -> PR00         43503030          50523030 CP01 -> PR01         43503031          50523031 CP02 -> PR02         43503032          50523032 CP03 -> PR03         43503033          50523033 CP04 -> PR04         43503034          50523034 CP05 -> PR05         43503035          50523035 CP06 -> PR06         43503036          50523036 CP07 -> PR07         43503037          50523037 CP08 -> PR08         43503038          50523038 CP09 -> PR09         43503039          50523039 CP0A -> PR10         43503041          50523130 CP0B -> PR11         43503042          50523131 CP0C -> PR12         43503043          50523132 CP0D -> PR13         43503044          50523133 CP0E -> PR14         43503045          50523134 CP0F -> PR15         43503046          50523135 CP10 -> PR16         43503130          50523136 CP11 -> PR17         43503131          50523137 CP12 -> PR18         43503132          50523138 CP13 -> PR19         43503133          50523139 CP14 -> PR20         43503134          50523230 CP15 -> PR21         43503135          50523231 CP16 -> PR22         43503136          50523232 CP17 -> PR23         43503137          50523233 CP18 -> PR24         43503138          50523234 CP19 -> PR25         43503139          50523235 CP1A -> PR26         43503141          50523236 CP1B -> PR27         43503142          50523237 CP1C -> PR28         43503143          50523238 CP1D -> PR29         43503144          50523239 CP1E -> PR30         43503145          50523330 CP1F -> PR31         43503146          50523331 CP20 -> PR32         43503230          50523332 CP21 -> PR33         43503231          50523333 CP22 -> PR34         43503232          50523334 CP23 -> PR35         43503233          50523335 CP24 -> PR36         43503234          50523336 CP25 -> PR37         43503235          50523337 CP26 -> PR38         43503236          50523338 CP27 -> PR39         43503237          50523339 CP28 -> PR40         43503238          50523430 CP29 -> PR41         43503239          50523431 CP2A -> PR42         43503241          50523432 CP2B -> PR43         43503242          50523433 CP2C -> PR44         43503243          50523434 CP2D -> PR45         43503244          50523435 CP2E -> PR46         43503245          50523436 CP2F -> PR47         43503246          50523437  
      Resulting CPU Core Implementation  

       
      E.9.2) SSDT-ASUS-X99-A-II.aml PCI Device Implementation 
       

       
      For the proper PCI device driver implementation (detailed in the Figure above), which is mostly directly related with the PCI device functionality, we now have to revise and likely adopt or modify the attached SSDT-X99-iMacPro.aml to our specific build, system configuration and PCIe slot population with the help of the IORegistryExplorer.   Note that for each device, the SSDT-ASUS-X99-A-II.aml contains a DefinitionBlock entry and the underlying PCI device implementation. In case of necessary modifications/adaptations, don't forget to also modify/adapt the respective DefinitionBlock entries in concordance with your IOREG entries. The entire SSDT structure is module like. Each module can be independently added, changed or removed in dependence of your specific build, needs and requirements. A stepwise implementation of the individual PCI devices is recommended!   E.9.2.1) HDEF - onboard Audio Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0, DeviceObj)    // (from opcode) External (_SB_.PCI0.ALZA, DeviceObj)    // (from opcode)  
      PCI Device Implementation:   Scope (\_SB.PCI0) { Scope (ALZA) { Name (_STA, Zero) // _STA: Status } Device (HDEF) { Name (_ADR, 0x001B0000) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x16) { "alc-layout-id", Buffer (0x04) { 0x05, 0x00, 0x00, 0x00 }, "MaximumBootBeepVolume", Buffer (One) { 0xEF }, "MaximumBootBeepVolumeAlt", Buffer (One) { 0xF1 }, "multiEQDevicePresence", Buffer (0x04) { 0x0C, 0x00, 0x01, 0x00 }, "AAPL,slot-name", Buffer (0x09) { "Built In" }, "model", Buffer (0x17) { "ASUS X99-A II HD Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-1" }, "built-in", Buffer (0x05) { "0x00" }, "device_type", Buffer (0x14) { "HD Audio Controller" }, "name", Buffer (0x22) { "Realtek ALC 1150 Audio Controller" }, "PinConfigurations", Buffer (Zero) {} }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } }  
        The HDEF PCI device implementation is valid for the ASUS X99-A II and likely for all other mainboards with the Realtek ALC 1150 Audio Controller chipset. It is a build in device and does not have any slot specific dependency. Note the ALZA -> HDEF ACPI Replacement within the SSDT! Thanks to @nmano for providing the correct alc-layout-id for macOS 10.14 Mojave.    E.9.2.2) GFX0, HDAU - Nvidia Graphics Card and HDMI/DP Audio PCI implementation 
       
      DefintionBlock entry:
      External (_SB_.PCI0.BR3A, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.H001, DeviceObj)    // (from opcode)  
        PCI Device Implementation: Scope (_SB.PCI0.BR3C)     {         Device (GFX0)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x14)                     {                         "built-in",                         Buffer (One)                         {                              0x00                                           },                         "device-id",                         Buffer (0x04)                         {                              0x06, 0x1B, 0x00, 0x00                         },                         "hda-gfx",                         Buffer (0x0A)                         {                             "onboard-2"                         },                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-1"                         },                         "@0,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@1,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@2,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@3,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@4,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@5,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }         Device (HDAU)         {             Name (_ADR, One)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0C)                     {                         "built-in",                         Buffer (One)                         {                              0x00                                           },                         "device-id",                         Buffer (0x04)                         {                              0xEF, 0x10, 0x00, 0x00                         },                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-1"                         },                         "device_type",                         Buffer (0x16)                         {                             "Multimedia Controller"                         },                         "name",                         Buffer (0x1D)                         {                             "NVIDIA High Definition Audio"                         },                         "hda-gfx",                         Buffer (0x0A)                         {                             "onboard-2"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }     Name (_SB.PCI0.BR3C.H000._STA, Zero)  // _STA: Status     Name (_SB.PCI0.BR3C.H001._STA, Zero)  // _STA: Status     Name (_SB.PCI0.BR3C.D07C._STA, Zero)  // _STA: Status  
      The actual GFX0 and HDAU PCI device implementation is valid for SMBIOS iMacPro1,1 (GFX0) and any Nvidia Graphics Card implemented in PCIe Slot 1.   It is a build and PCIe slot population dependent device implementation. Nvidia Graphics Card users with more than one graphics card, or with an Nvidia graphics card in a PCIe slot different from PCIe Slot 0, will have to adopt the respective PCI0, BR3A, H000, H001, D07C, GFX1 device path entries following their respective IOREG entries. Note the H000 -> H001, H001 ->D07C and D07C -> GFX0 ACPI replacements within the SSDT!   Also note that with 10.13.4, Apple changed the com.apple.driver.AppleHDAController implementation. To make the NVIDIA HDAU PCI device driver work for e.g. a GeForce GTX 1080, one needs to add the following KextToPatch entry in Section "Kernel and kext Patches" of Clover Configurator, as already implemented in the config.plist contained in EFI-X99-10.14-DP1-Release-iMacPro1,1-160618: Name*                                 Find* [HEX]         Replace* [HEX]        Comment com.apple.driver.AppleHDAController   DE100B0E            DE10EF10              FredWst DP/HDMI patch  
      Credits to @FreedWst and thanks to @fabiosun for pointing me to this solution. The KextToPatch entry might defer for Nvidia GPUs different from the Geforce GTX 1080.   Users of NvidiaGraphicsfixup.kext v1.2.6 and above might be able to drop this KextToPatch entry, as the latter kext already properly implements the Nvidia HDAU PCI driver.   Below one finds an example of @apfelnico for a GFX and HDAU PCI implementation of 1x Radeon Vega Frontier in PCIe Slot 1:   DefintionBlock entry: External (_SB_.PCI0.BR3A, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H001, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.BR3A) { Scope (H000) { Name (_STA, Zero) // _STA: Status } Scope (H001) { Name (_STA, Zero) // _STA: Status } Scope (D07C) { Name (_STA, Zero) // _STA: Status } Device (PEGP) { Name (_ADR, Zero) // _ADR: Address Device (EGP0) { Name (_ADR, Zero) // _ADR: Address Device (GFX0) { Name (_ADR, Zero) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x18) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "model", Buffer (0x16) { "Vega Frontier Edition" }, "name", Buffer (0x08) { "ATY_GPU" }, "@0,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@1,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@2,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@3,connector-type", Buffer (0x04) { 0x00, 0x08, 0x00, 0x00 }, "@0,name", Buffer (0x0D) { "ATY,Kamarang" }, "@1,name", Buffer (0x0D) { "ATY,Kamarang" }, "@2,name", Buffer (0x0D) { "ATY,Kamarang" }, "@3,name", Buffer (0x0D) { "ATY,Kamarang" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (HDAU) { Name (_ADR, One) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0A) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "name", Buffer (0x1F) { "Vega Frontier Edition HD-Audio" }, "model", Buffer (0x1F) { "Vega Frontier Edition HD-Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } } } }  
      as well as one example of @apfelnico for the GFX and HDAU PCI implementation of 1x Radeon Vega 64 in PCIe Slot 1, pimped to 1442 Mhz:
       
      DefintionBlock entry: External (_SB_.PCI0.BR3A, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H001, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.BR3A) { Scope (H000) { Name (_STA, Zero) // _STA: Status } Scope (H001) { Name (_STA, Zero) // _STA: Status } Scope (D07C) { Name (_STA, Zero) // _STA: Status } Device (PEGP) { Name (_ADR, Zero) // _ADR: Address Device (EGP0) { Name (_ADR, Zero) // _ADR: Address Device (GFX0) { Name (_ADR, Zero) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x20) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "model", Buffer (0x12) { "Radeon RX Vega 64" }, "name", Buffer (0x08) { "ATY_GPU" }, "@0,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@1,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@2,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@3,connector-type", Buffer (0x04) { 0x00, 0x08, 0x00, 0x00 }, "@0,name", Buffer (0x0D) { "ATY,Kamarang" }, "@1,name", Buffer (0x0D) { "ATY,Kamarang" }, "@2,name", Buffer (0x0D) { "ATY,Kamarang" }, "@3,name", Buffer (0x0D) { "ATY,Kamarang" }, "PP_PhmSoftPowerPlayTable", Buffer (One) { /* 0000 */ 0xB6, 0x02, 0x08, 0x01, 0x00, 0x5C, 0x00, 0xE1, /* 0008 */ 0x06, 0x00, 0x00, 0xEE, 0x2B, 0x00, 0x00, 0x1B, /* 0010 */ 0x00, 0x48, 0x00, 0x00, 0x00, 0x80, 0xA9, 0x03, /* 0018 */ 0x00, 0xF0, 0x49, 0x02, 0x00, 0x8E, 0x00, 0x08, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0028 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, /* 0030 */ 0x5C, 0x00, 0x4F, 0x02, 0x46, 0x02, 0x94, 0x00, /* 0038 */ 0x9E, 0x01, 0xBE, 0x00, 0x28, 0x01, 0x7A, 0x00, /* 0040 */ 0x8C, 0x00, 0xBC, 0x01, 0x00, 0x00, 0x00, 0x00, /* 0048 */ 0x72, 0x02, 0x00, 0x00, 0x90, 0x00, 0xA8, 0x02, /* 0050 */ 0x6D, 0x01, 0x43, 0x01, 0x97, 0x01, 0xF0, 0x49, /* 0058 */ 0x02, 0x00, 0x71, 0x02, 0x02, 0x02, 0x00, 0x00, /* 0060 */ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, /* 0068 */ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x07, 0x00, /* 0070 */ 0x03, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0078 */ 0x00, 0x00, 0x01, 0x08, 0x84, 0x03, 0x84, 0x03, /* 0080 */ 0xB6, 0x03, 0xE8, 0x03, 0x1A, 0x04, 0x4C, 0x04, /* 0088 */ 0x60, 0x04, 0x7E, 0x04, 0x01, 0x01, 0x33, 0x04, /* 0090 */ 0x01, 0x01, 0x84, 0x03, 0x00, 0x08, 0x60, 0xEA, /* 0098 */ 0x00, 0x00, 0x00, 0x40, 0x19, 0x01, 0x00, 0x01, /* 00A0 */ 0x80, 0x38, 0x01, 0x00, 0x02, 0xDC, 0x4A, 0x01, /* 00A8 */ 0x00, 0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0x00, /* 00B0 */ 0x77, 0x01, 0x00, 0x05, 0x90, 0x91, 0x01, 0x00, /* 00B8 */ 0x06, 0x50, 0xBD, 0x01, 0x00, 0x07, 0x01, 0x08, /* 00C0 */ 0xD0, 0x4C, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, /* 00C8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x8D, 0x01, /* 00D0 */ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00D8 */ 0x00, 0x00, 0xDC, 0xC7, 0x01, 0x00, 0x02, 0x00, /* 00E0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, /* 00E8 */ 0xFC, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* 00F0 */ 0x00, 0x00, 0x00, 0x00, 0xD8, 0x1B, 0x02, 0x00, /* 00F8 */ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0100 */ 0x00, 0xF4, 0x40, 0x02, 0x00, 0x05, 0x00, 0x00, /* 0108 */ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1C, 0x64, /* 0110 */ 0x02, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x01, /* 0118 */ 0x00, 0x00, 0x00, 0x68, 0x81, 0x02, 0x00, 0x07, /* 0120 */ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* 0128 */ 0x00, 0x05, 0x60, 0xEA, 0x00, 0x00, 0x00, 0x40, /* 0130 */ 0x19, 0x01, 0x00, 0x00, 0x80, 0x38, 0x01, 0x00, /* 0138 */ 0x00, 0xDC, 0x4A, 0x01, 0x00, 0x00, 0x90, 0x5F, /* 0140 */ 0x01, 0x00, 0x00, 0x00, 0x08, 0x28, 0x6E, 0x00, /* 0148 */ 0x00, 0x00, 0x2C, 0xC9, 0x00, 0x00, 0x01, 0xF8, /* 0150 */ 0x0B, 0x01, 0x00, 0x02, 0x80, 0x38, 0x01, 0x00, /* 0158 */ 0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0xF4, 0x91, /* 0160 */ 0x01, 0x00, 0x05, 0xD0, 0xB0, 0x01, 0x00, 0x06, /* 0168 */ 0x38, 0xC1, 0x01, 0x00, 0x07, 0x00, 0x08, 0x6C, /* 0170 */ 0x39, 0x00, 0x00, 0x00, 0x24, 0x5E, 0x00, 0x00, /* 0178 */ 0x01, 0xFC, 0x85, 0x00, 0x00, 0x02, 0xAC, 0xBC, /* 0180 */ 0x00, 0x00, 0x03, 0x34, 0xD0, 0x00, 0x00, 0x04, /* 0188 */ 0x68, 0x6E, 0x01, 0x00, 0x05, 0x08, 0x97, 0x01, /* 0190 */ 0x00, 0x06, 0xB0, 0xAD, 0x01, 0x00, 0x07, 0x00, /* 0198 */ 0x01, 0x68, 0x3C, 0x01, 0x00, 0x00, 0x01, 0x04, /* 01A0 */ 0x3C, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, /* 01A8 */ 0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x38, /* 01B0 */ 0x01, 0x00, 0x02, 0x00, 0x00, 0x34, 0x98, 0x01, /* 01B8 */ 0x00, 0x04, 0x00, 0x00, 0x01, 0x08, 0x00, 0x98, /* 01C0 */ 0x85, 0x00, 0x00, 0x40, 0xB5, 0x00, 0x00, 0x60, /* 01C8 */ 0xEA, 0x00, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01, /* 01D0 */ 0x80, 0xBB, 0x00, 0x00, 0x60, 0xEA, 0x00, 0x00, /* 01D8 */ 0x94, 0x0B, 0x01, 0x00, 0x50, 0xC3, 0x00, 0x00, /* 01E0 */ 0x02, 0x00, 0xE1, 0x00, 0x00, 0x94, 0x0B, 0x01, /* 01E8 */ 0x00, 0x40, 0x19, 0x01, 0x00, 0x50, 0xC3, 0x00, /* 01F0 */ 0x00, 0x03, 0x78, 0xFF, 0x00, 0x00, 0x40, 0x19, /* 01F8 */ 0x01, 0x00, 0x88, 0x26, 0x01, 0x00, 0x50, 0xC3, /* 0200 */ 0x00, 0x00, 0x04, 0x40, 0x19, 0x01, 0x00, 0x80, /* 0208 */ 0x38, 0x01, 0x00, 0x80, 0x38, 0x01, 0x00, 0x50, /* 0210 */ 0xC3, 0x00, 0x00, 0x05, 0x80, 0x38, 0x01, 0x00, /* 0218 */ 0xDC, 0x4A, 0x01, 0x00, 0xDC, 0x4A, 0x01, 0x00, /* 0220 */ 0x50, 0xC3, 0x00, 0x00, 0x06, 0x00, 0x77, 0x01, /* 0228 */ 0x00, 0x00, 0x77, 0x01, 0x00, 0x90, 0x5F, 0x01, /* 0230 */ 0x00, 0x50, 0xC3, 0x00, 0x00, 0x07, 0x90, 0x91, /* 0238 */ 0x01, 0x00, 0x90, 0x91, 0x01, 0x00, 0x00, 0x77, /* 0240 */ 0x01, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01, 0x18, /* 0248 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, /* 0250 */ 0x00, 0x00, 0xBC, 0x02, 0x48, 0x26, 0x46, 0x00, /* 0258 */ 0x0A, 0x00, 0x54, 0x03, 0x90, 0x01, 0x90, 0x01, /* 0260 */ 0x90, 0x01, 0x90, 0x01, 0x90, 0x01, 0x90, 0x01, /* 0268 */ 0x90, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, /* 0270 */ 0x04, 0x31, 0x07, 0x90, 0x01, 0x90, 0x01, 0x90, /* 0278 */ 0x01, 0x90, 0x01, 0x00, 0x00, 0x59, 0x00, 0x69, /* 0280 */ 0x00, 0x4A, 0x00, 0x4A, 0x00, 0x5F, 0x00, 0x73, /* 0288 */ 0x00, 0x73, 0x00, 0x64, 0x00, 0x40, 0x00, 0x90, /* 0290 */ 0x92, 0x97, 0x60, 0x96, 0x00, 0x90, 0x55, 0x00, /* 0298 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 02A0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 02A8 */ 0x02, 0x02, 0xD4, 0x30, 0x00, 0x00, 0x02, 0x10, /* 02B0 */ 0x60, 0xEA, 0x00, 0x00, 0x02, 0x10 }, "hda-gfx", Buffer (0x0A) { "onboard-2" }, "PP_DisablePowerContainment", Buffer (One) { 0x01 }, "PP_FuzzyFanControl", Buffer (One) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (HDAU) { Name (_ADR, One) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0A) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "name", Buffer (0x14) { "Radeon RX HD-Audio" }, "model", Buffer (0x14) { "Radeon RX HD-Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } } }  
       
        E.9.2.3) XGBE - 10GBit NIC Implementation:   DefintionBlock entry: External (_SB_.PCI0.BR3A, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj)    // (from opcode)  
      ASUS XG-C100C AQC107 PCI Device Implementation: Scope (\_SB.PCI0.BR3A)     {         Scope (H000)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D07C)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                     })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                         },                         "name",                         Buffer (0x33)                         {                             "ASUS XG-C100C Aquantia AQC107 10-Gigabit Ethernet"                         },                         "model",                         Buffer (0x11)                         {                             "Apple AQC107-AFW"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x87, 0x01, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0xB1, 0x07, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x6B, 0x10, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        Intel X540-T1 PCI Device Implementation: Scope (\_SB.PCI0.BR3A)     {         Scope (H000)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D07C)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                        })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                            },                         "name",                         Buffer (0x22)                         {                             "Intel X540-T1 10-Gigabit Ethernet"                         },                         "model",                         Buffer (0x22)                         {                             "Intel X540-T1 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        Small-Tree P2EI0G-2T PCI Device Implementation: Scope (\_SB.PCI0.BR3A)     {         Scope (H000)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D07C)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                        })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                            },                         "name",                         Buffer (0x30)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 1"                         },                         "model",                         Buffer (0x29)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }         Device (XGBF)         {             Name (_ADR, One)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                        })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                            },                         "name",                         Buffer (0x30)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 2"                         },                         "model",                         Buffer (0x29)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The 10-Gigabit NIC XGBE PCI implementation is mainly of cosmetic nature and valid for the NIC in Slot-6. For each PCIe Adapter and for different slot populations the XGBE PCI device implementation needs to be adopted/modified (see details above). This also states for the respective ACPI path entries "PCI0", "BR3A" and respective H000 -> D07C and D07C -> XGBE ACPI Replacements (in compliance with the iMac Pro 10GB ACPI variable nomenclature), directly performed within the SSDT-299-iMacPro.aml. Those not employing any 10-GBit NIC in their system, can simply remove the corresponding SSDT PCI device implementation.   E.9.2.4) ETH0 - onboard LAN Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0, DeviceObj)    // (from opcode) External (_SB_.PCI0.GLAN, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0)     {         Scope (GLAN)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ETH0)         {             Name (_ADR, 0x00190000)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                            },                         "name",                         Buffer (0x2A)                         {                             "Intel i218-V PCI Express Gigabit Ethernet"                         },                         "model",                         Buffer (0x21)                         {                             "Intel i218-V Ethernet Controller"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0xC4, 0x85, 0x00, 0x00                          },                         "device-id",                         Buffer (0x04)                         {                              0xA1, 0x15, 0x00, 0x00                          },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x43, 0x10, 0x00, 0x00                          }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      Note that the ETH0 Intel i218-V Ethernet onboard LAN controller PCI implementation is of pure cosmetic nature and valid for the ASUS X99-A II or X99 mainboards with the same LAN Controller configuration. Owners of different X99 mainboards have to verify and adopt/modify the ACPI path and the PCI device implementations by means of their IOREG entries. Note the GLAN -> ETH0 ACPI replacement directly performed within the SSDT.   E.9.2.5) SAT1 - Intel AHCI SATA Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.SAT1, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.SAT1) { Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0C) { "AAPL,slot-name", Buffer (0x09) { "Built In" }, "built-in", Buffer (One) { 0x00 }, "name", Buffer (0x1B) { "Intel SATA AHCI Controller" }, "model", Buffer (0x27) { "Intel X99-A II Chipset SATA Controller" }, "device_type", Buffer (0x15) { "AHCI SATA Controller" }, "device-id", Buffer (0x04) { 0x02, 0x8D, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } }  
      The SAT1 onboard Intel AHCI SATA controller PCI device implementation is valid for the ASUS X99-A II and for all other X99 mainboards with the same AHCI SATA controller chipset.   E.9.2.6) EVSS - Intel X99 sSata Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.EVSS, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (_SB.PCI0.EVSS) { Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0E) { "AAPL,slot-name", Buffer (0x09) { "Built In" }, "built-in", Buffer (0x05) { "0x00" }, "name", Buffer (0x1B) { "Intel X99 sSata Controller" }, "model", Buffer (0x28) { "Intel X99-A II Chipset sSATA Controller" }, "compatible", Buffer (0x0D) { "pci8086,8d62" }, "device_type", Buffer (0x10) { "AHCI Controller" }, "device-id", Buffer (0x04) { 0x62, 0x8D, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, Zero }) }  
      The EVSS onboard Intel X99 sSATA controller PCI device implementation is valid for the ASUS X99-A II and for all other X99 mainboards with the same X99 sSATA controller chipset. Verify and adopt/modify if necessary device path "PCI0.SAT1" and PCI device implementations by means of IOREG.   E.9.2.7)  NVMe Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.BR1B, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR1B.D075, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR1B.D081, DeviceObj)    // (from opcode)  
        PCI Device Implementation: Scope (_SB.PCI0.BR1B)     {         Scope (D075)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D081)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ANS2)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0C)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                             },                         "device-id",                         Buffer (0x04)                         {                              0x04, 0xA8, 0x00, 0x00                           },                         "device_type",                         Buffer (0x17)                         {                             "MVM Express Controller"                         },                         "name",                         Buffer (0x16)                         {                             "Apple NVMe Controller"                         },                         "model",                         Buffer (0x13)                         {                             "Apple NVMe AP1024M"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }  
      The current ANS2 Apple NVMe Controller PCI implementation is of purely cosmetic nature and is valid for the ASUS X99-A II. Note  ACPI Replacements D075 -> D081 and D081 -> ANS2 directly within the SSDT, in concordance with the respective SMBIOS iMacPro1,1 variable naming!   E.9.2.8) - USBX:   PCI Device Implementation: Device (_SB.USBX)     {         Name (_ADR, Zero)  // _ADR: Address         Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method         {             If (LNot (Arg2))             {                 Return (Buffer (One)                 {                      0x03                                     })             }             Return (Package (0x08)             {                 "kUSBSleepPortCurrentLimit",                 0x0834,                 "kUSBSleepPowerSupply",                 0x13EC,                 "kUSBWakePortCurrentLimit",                 0x0834,                 "kUSBWakePowerSupply",                 0x13EC             })         }     }  
      When using the XHCI device name for USB (see the XHCI PCI Device Implementation below), one observes a bunch of USB Power Errors when booting the system. The USBX PCI device implementation fixes this errors.
          E.9.2.9) XHCI - onboard Extended Host Controller Interface (XHCI) PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.XHCI, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.XHCI) { Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x1B) { "AAPL,slot-name", Buffer (0x09) { "Built In" }, "built-in", Buffer (One) { 0x00 }, "device-id", Buffer (0x04) { 0x31, 0x8D, 0x00, 0x00 }, "name", Buffer (0x34) { "Intel XHC USB Controller" }, "model", Buffer (0x2F) { "Intel X99-A II Chipset XHC USB Host Controller" }, "AAPL,current-available", 0x0834, "AAPL,current-extra", 0x0A8C, "AAPL,current-in-sleep", 0x0A8C, "AAPL,max-port-current-in-sleep", 0x0834, "AAPL,device-internal", Zero, "AAPL,clock-id", Buffer (One) { 0x01 }, "AAPL,root-hub-depth", 0x1A, "AAPL,XHC-clock-id", One, Buffer (One) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } }  
      The XHCI USB3.0 PCI device implementation is valid for the ASUS X99_A II and for all other X99 mainboards with the same XHCI controller chipset. Verify and adopt/modify if necessary device path "PCI0.XHCI" and PCI device implementations by means of IOREG.     E.9.2.10) ASMedia ASM1142 USB 3.1 Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.RP05, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP05.D07D, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP05.D082, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (_SB.PCI0.RP05)     {         Scope (D07D)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D082)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XHC3)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                         })                 }                 Store (Package (0x0A)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                             },                         "device-id",                         Buffer (0x04)                         {                              0x42, 0x12, 0x00, 0x00                           },                         "name",                         Buffer (0x1B)                         {                             "ASMedia USB 3.1 Controller"                         },                         "model",                         Buffer (0x28)                         {                             "ASMedia ASM1142 USB 3.1 Type-A & Type-C"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }  
        The ASMedia ASM1142 USB 3.1 onboard Intel AHCI SATA controller PCI device implementation is valid for the ASUS X99-A II and for all other X99 mainboards with the same XHC USB3.1 controller ASMedia ASM1142 chipset configuration. Note the D07D -> D082 and D082 -> XHC3 ACPI replacements directly within the SSDT!   E.9.2.11) ARPT - OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0.RP07, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP07.ARPT, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (_SB.PCI0.RP07)     {         Device (ARPT)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (0x04)                     {                          0x03                                         })                 }                 Store (Package (0x0C)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-5"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                             },                         "device_type",                         Buffer (0x13)                         {                             "AirPort Controller"                         },                         "model",                         Buffer (0x4A)                         {                             "OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 Controller"                         },                         "compatible",                         Buffer (0x0D)                         {                             "pci14e4,43a0"                         },                         "name",                         Buffer (0x10)                         {                             "AirPort Extreme"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }  
        The ARPT OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI device implementation is of pure cosmetic nature and only valid for users of the latter WIFI/Bluetooth PCIe Adapter in PCIe Slot 5. Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 5 have to adapt/modify the respective device path. Users of the Asus X99-A II onboard Bluetooth chipset controller or with a completely different WIFI/Bluetooth configuration have to adopt the entire Airport PCI implementation by means of IOREG.   E.9.2.12) DTGP Method: Method (DTGP, 5, NotSerialized)     {         If (LEqual (Arg0, ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))         {             If (LEqual (Arg1, One))             {                 If (LEqual (Arg2, Zero))                 {                     Store (Buffer (One)                         {                              0x03                         }, Arg4)                     Return (One)                 }                 If (LEqual (Arg2, One))                 {                     Return (One)                 }             }         }         Store (Buffer (One)             {                  0x00             }, Arg4)         Return (Zero)     }  
      The DTG Method Implementation is required for SSDT functionality and has not to be modified or adopted in any case.     E.9.2.13) - Debugging Sleep Issues   For debugging sleep issues as proposed by Pike Alpha, one can add SSDT-SLEEP.aml to /EFI/CLOVER/ACPI/patched and follow Pike's comment and advices provided at https://pikeralpha.wordpress.com/2017/01/12/debugging-sleep-issues/     E.9.3) SSDT-X99-TB3-iMacPro-KGP.aml PCI Device Implementation    
      The current Thunderbolt PCI device implementation SSDT-X99-TB3-iMacPro-KGP.aml has been kept as close as possible to the SSDT-9.aml of @TheOffcialGypsy's iMac Pro dumb. It also contains implementations mainly developed by @apfelnico, @nmano, @Mork vom Ork, @Matthew82, @maleorderbridge, @TheRacerMaster.    It is valid for both, the ASUS TBEX 3 and Gigabyte Alpine Ridge and allows for TB and XHC USB sleep/wake functionality with the THB_C cable plugged to the thunderbolt onboard header of the ASUS Prime X299 Deluxe. While XHC USB hot plug seems to work fine within this configuration, TB hot plug seems to require the removal of the THB_C cable. Thank's to @crismac2013 and @LeleTuratti for their findings!   >>> https://youtu.be/Jakp5dCoFvY <<<   Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 4 have to adapt/modify the respective BR2A,BR2X, H000, D07F and UPSB ACPI Replacements, directly performed within the SSDT.   DefintionBlock entry: External (_SB_.PCI0, DeviceObj) // (from opcode) External (_SB_.PCI0.BR2A, DeviceObj) // (from opcode) External (_SB_.PCI0.BR2A.H000, DeviceObj) // (from opcode) External (_SB_.PWRB, DeviceObj) // (from opcode) External (AG12, UnknownObj) // (from opcode) External (AG22, UnknownObj) // (from opcode) External (BR2A, DeviceObj) // (from opcode) External (BR2A.H000, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode) External (IO80, UnknownObj) // (from opcode) External (PG12, UnknownObj) // (from opcode) External (PG22, UnknownObj) // (from opcode) External (PICM, UnknownObj) // (from opcode) External (PWRB, DeviceObj) // (from opcode)  
      PCI Device Implementation: OperationRegion (GNVS, SystemMemory, 0x4FEE6918, 0x0403) Field (GNVS, AnyAcc, Lock, Preserve) { OSYS, 16 } Method (OSDW, 0, NotSerialized) { If (LEqual (OSYS, 0x2710)) { Return (One) } Else { Return (Zero) } } Method (PINI, 0, NotSerialized) { Store (0x07DC, OSYS) If (XOSI ("Darwin")) { Store (0x2710, OSYS) } ElseIf (XOSI ("Linux")) { Store (0x03E8, OSYS) } ElseIf (XOSI ("Windows 2009")) { Store (0x07D9, OSYS) } ElseIf (XOSI ("Windows 2012")) { Store (0x07DC, OSYS) } Else { Store (0x07DC, OSYS) } } Method (XOSI, 1, NotSerialized) { Store (Package (0x0E) { "Darwin", "Linux", "Windows", "Windows 2001", "Windows 2001 SP2", "Windows 2001.1", "Windows 2001.1 SP1", "Windows 2006", "Windows 2006 SP1", "Windows 2006.1", "Windows 2009", "Windows 2012", "Windows 2013", "Windows 2015" }, Local0) Return (LNotEqual (Ones, Match (Local0, MEQ, Arg0, MTR, Zero, Zero))) } Scope (\_SB.PCI0) { Scope (BR2A) { Name (_STA, Zero) // _STA: Status } Device (BR2X) { Name (_ADR, 0x00020000) // _ADR: Address OperationRegion (MCTL, SystemMemory, 0xE0000188, 0x04) Field (MCTL, ByteAcc, NoLock, Preserve) { , 3, HGPE, 1, , 7, , 8, , 8 } Method (_INI, 0, NotSerialized) // _INI: Initialize { Store (One, HGPE) } Name (_HPP, Package (0x04) // _HPP: Hot Plug Parameters { 0x08, 0x40, One, Zero }) Name (SHPC, 0x40) Name (SPDS, 0x40) Name (MRLS, Zero) Name (CCOM, 0x10) Name (SPDC, 0x08) Name (MRLC, 0x04) Name (SPFD, 0x02) Name (SABP, One) Name (SPOF, 0x10) Name (SPON, 0x0F) Name (ALMK, 0x1C) Name (ALON, One) Name (ALBL, 0x02) Name (ALOF, 0x03) Name (PLMK, 0x13) Name (PLON, 0x04) Name (PLBL, 0x08) Name (PLOF, 0x0C) Name (HPEV, 0x0F) OperationRegion (PPA4, PCI_Config, Zero, 0x0100) Field (PPA4, ByteAcc, NoLock, Preserve) { Offset (0xA0), , 4, LDIS, 1, Offset (0xA2), Offset (0xA4), ATBP, 1, , 1, MRSP, 1, ATIP, 1, PWIP, 1, HPSR, 1, HPCP, 1, , 12, PSNM, 13, ABIE, 1, PFIE, 1, MSIE, 1, PDIE, 1, CCIE, 1, HPIE, 1, SCTL, 5, Offset (0xAA), SSTS, 7, Offset (0xAB), Offset (0xB0), Offset (0xB2), PMES, 1, PMEP, 1, Offset (0xB4) } Method (ATID, 0, NotSerialized) { Return (And (SCTL, 0x03)) } Method (PWID, 0, NotSerialized) { Return (ShiftRight (And (SCTL, 0x0C), 0x02)) } Method (PWCC, 0, NotSerialized) { Return (ShiftRight (And (SCTL, 0x10), 0x04)) } Method (ABPS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, One, SSTS) } Return (And (SSTS, One)) } Method (PFDS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x02, SSTS) } Return (ShiftRight (And (SSTS, 0x02), One)) } Method (MSCS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x04, SSTS) } Return (ShiftRight (And (SSTS, 0x04), 0x02)) } Method (PDCS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x08, SSTS) } Return (ShiftRight (And (SSTS, 0x08), 0x03)) } Method (CMCS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x10, SSTS) } Return (ShiftRight (And (SSTS, 0x10), 0x04)) } Method (MSSC, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x20, SSTS) } Return (ShiftRight (And (SSTS, 0x20), 0x05)) } Method (PRDS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x40, SSTS) } Return (ShiftRight (And (SSTS, 0x40), 0x06)) } Method (OSHP, 0, NotSerialized) { Store (SSTS, SSTS) Store (Zero, HGPE) } Method (HPCC, 1, NotSerialized) { Store (SCTL, Local0) Store (Zero, Local1) If (LNotEqual (Arg0, Local0)) { Store (Arg0, SCTL) While (LAnd (LNot (CMCS (Zero)), LNotEqual (0x64, Local1))) { Store (0xFB, IO80) Sleep (0x02) Add (Local1, 0x02, Local1) } CMCS (One) } } Method (ATCM, 1, NotSerialized) { Store (SCTL, Local0) And (Local0, ALMK, Local0) If (LEqual (Arg0, One)) { Or (Local0, ALON, Local0) } If (LEqual (Arg0, 0x02)) { Or (Local0, ALBL, Local0) } If (LEqual (Arg0, 0x03)) { Or (Local0, ALOF, Local0) } HPCC (Local0) } Method (PWCM, 1, NotSerialized) { Store (SCTL, Local0) And (Local0, PLMK, Local0) If (LEqual (Arg0, One)) { Or (Local0, PLON, Local0) } If (LEqual (Arg0, 0x02)) { Or (Local0, PLBL, Local0) } If (LEqual (Arg0, 0x03)) { Or (Local0, PLOF, Local0) } HPCC (Local0) } Method (PWSL, 1, NotSerialized) { Store (SCTL, Local0) If (Arg0) { And (Local0, SPON, Local0) } Else { Or (Local0, SPOF, Local0) } HPCC (Local0) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler Name (_T_0, Zero) // _T_x: Emitted by ASL Compiler While (One) { Store (And (Arg0, 0xFF), _T_0) If (LEqual (_T_0, 0x03)) { While (One) { Store (ToInteger (Arg1), _T_1) If (LNotEqual (Match (Package (0x04) { 0x80, 0x81, 0x82, 0x83 }, MEQ, _T_1, MTR, Zero, Zero), Ones)) { If (LNot (PWCC ())) { PWCM (One) Store (One, ABIE) } } Break } } Break } } Method (EJ0L, 1, NotSerialized) { Store (0xFF, IO80) Store (SCTL, Local0) If (LNotEqual (ATID (), One)) { And (Local0, ALMK, Local0) Or (Local0, ALBL, Local0) } HPCC (Local0) Store (SCTL, Local0) Or (Local0, SPOF, Local0) HPCC (Local0) Store (SCTL, Local0) Or (Local0, PLOF, Local0) HPCC (Local0) Store (SCTL, Local0) Or (Local0, ALOF, Local0) HPCC (Local0) } Method (PMEH, 1, NotSerialized) { If (And (HPEV, SSTS)) { If (ABPS (Zero)) { ABPS (One) Sleep (0xC8) } } Return (0xFF) } Method (HPEH, 1, NotSerialized) { If (LNot (HPCP)) { Return (0xFF) } Store (0xFE, IO80) Sleep (0x64) Store (Zero, CCIE) If (And (HPEV, SSTS)) { Store (0xFD, IO80) Sleep (0x0A) Store (PPXH (Zero), Local0) Return (Local0) } Else { Return (0xFF) } Store (0xFC, IO80) Sleep (0x0A) } Method (PPXH, 1, NotSerialized) { Sleep (0xC8) If (ABPS (Zero)) { If (LNot (PRDS (Zero))) { Store (One, LDIS) PWSL (Zero) PWCM (0x03) If (LEqual (MSSC (Zero), MRLS)) { ATCM (0x02) } Else { ATCM (0x03) } ABPS (One) Sleep (0xC8) Return (0xFF) } Store (Zero, ABIE) ABPS (One) Sleep (0xC8) If (PWCC ()) { ATCM (0x02) Sleep (0x0258) Store (0x0258, Local0) ABPS (One) While (LNot (ABPS (Zero))) { Sleep (0xC8) Add (Local0, 0xC8, Local0) If (LEqual (0x1388, Local0)) { Store (One, ABIE) ATCM (0x03) PWCM (0x02) Sleep (0x0258) Store (Zero, LDIS) PWSL (One) Sleep (0x01F4) If (LNot (PFDS (Zero))) { PWCM (One) Store (Zero, Local1) Store (One, ABIE) } Else { PWSL (Zero) PWCM (0x03) ATCM (One) Store (One, LDIS) Store (0x03, Local1) Store (One, ABIE) } ABPS (One) Sleep (0xC8) Return (Local1) } } Return (0xFF) } Else { ATCM (0x02) Sleep (0x0258) Store (0x0258, Local0) ABPS (One) Sleep (0xC8) While (LNot (ABPS (Zero))) { Sleep (0xC8) Add (Local0, 0xC8, Local0) If (LEqual (0x1388, Local0)) { ABPS (One) ATCM (0x03) PWCM (0x02) Sleep (0xC8) Store (One, ABIE) Store (One, LDIS) PWCM (0x03) Return (0x03) } } PWCM (One) ABPS (One) Sleep (0xC8) Store (One, ABIE) Return (0xFF) } } If (PFDS (Zero)) { PFDS (One) PWSL (Zero) PWCM (0x03) ATCM (One) Store (One, LDIS) Return (0x03) } If (PDCS (Zero)) { PDCS (One) If (LNot (PRDS (Zero))) { PWSL (Zero) PWCM (0x03) If (LEqual (MSSC (Zero), MRLS)) { ATCM (0x02) } Else { ATCM (0x03) } Store (One, LDIS) Return (0xFF) } Else { Store (Zero, LDIS) ABPS (One) Sleep (0xC8) Store (One, ABIE) Sleep (0xC8) Return (Local1) } } Return (0xFF) } Method (SNUM, 0, Serialized) { Store (PSNM, Local0) Return (Local0) } Method (_SUN, 0, NotSerialized) // _SUN: Slot User Number { Return (SNUM ()) } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (AG12) } Return (PG12) } Device (UPSB) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (One) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (One) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LNot (Arg2)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x02) { "PCIHotplugCapable", One }) } Device (NHI0) { Name (_ADR, Zero) // _ADR: Address Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Store (Package (0x13) { "AAPL,slot-name", Buffer (0x07) { "Slot-4" }, "built-in", Buffer (One) { 0x00 }, "device_type", Buffer (0x19) { "Thunderbolt 3 Controller" }, "model", Buffer (0x20) { "Intel DSL6540 Thunderbolt 3 NHI" }, "name", Buffer (0x25) { "Intel DSL6540 Thunderbolt Controller" }, "pathcr", Buffer (One) { /* 0000 */ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00, /* 0010 */ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00, /* 0020 */ 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x0E, 0x00, /* 0028 */ 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0030 */ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0038 */ 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x01, 0x00, /* 0040 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0048 */ 0x00, 0x00, 0x07, 0x00, 0x02, 0x00, 0x01, 0x00 }, "ThunderboltDROM", Buffer (One) { /* 0000 */ 0x6D, 0x01, 0xC5, 0x49, 0xD5, 0x3E, 0x21, 0x01, /* 0008 */ 0x00, 0x04, 0xCE, 0x8D, 0x61, 0x01, 0x5E, 0x00, /* 0010 */ 0x01, 0x00, 0x0C, 0x00, 0x01, 0x00, 0x08, 0x81, /* 0018 */ 0x81, 0x02, 0x81, 0x00, 0x00, 0x00, 0x08, 0x82, /* 0020 */ 0x91, 0x01, 0x81, 0x00, 0x00, 0x00, 0x08, 0x83, /* 0028 */ 0x81, 0x04, 0x81, 0x01, 0x00, 0x00, 0x08, 0x84, /* 0030 */ 0x91, 0x03, 0x81, 0x01, 0x00, 0x00, 0x08, 0x85, /* 0038 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x86, /* 0040 */ 0x20, 0x03, 0x87, 0x80, 0x02, 0xC8, 0x05, 0x89, /* 0048 */ 0x50, 0x00, 0x00, 0x05, 0x8A, 0x50, 0x00, 0x00, /* 0050 */ 0x02, 0xCB, 0x0D, 0x01, 0x41, 0x70, 0x70, 0x6C, /* 0058 */ 0x65, 0x20, 0x49, 0x6E, 0x63, 0x2E, 0x00, 0x0C, /* 0060 */ 0x02, 0x4D, 0x61, 0x63, 0x69, 0x6E, 0x74, 0x6F, /* 0068 */ 0x73, 0x68, 0x00 }, "ThunderboltConfig", Buffer (One) { /* 0000 */ 0x01, 0x02, 0xFF, 0xFF, 0x04, 0x00, 0x03, 0x01, /* 0008 */ 0x01, 0x00, 0x04, 0x00, 0x05, 0x01, 0x02, 0x00, /* 0010 */ 0x03, 0x00, 0x03, 0x01, 0x01, 0x00, 0x01, 0x00, /* 0018 */ 0x03, 0x01, 0x02, 0x00, 0x04, 0x00, 0x03, 0x00 }, "power-save", One, Buffer (One) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Return (Zero) } } Device (DSB1) { Name (_ADR, 0x00010000) // _ADR: Address Name (_SUN, 0x04) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB2) { Name (_ADR, 0x00020000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LNot (Arg2)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x02) { "PCIHotplugCapable", Zero }) } Device (XHC5) { Name (_ADR, Zero) // _ADR: Address Name (SDPC, Zero) OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x10) { "AAPL,slot-name", Buffer (0x07) { "Slot-4" }, "built-in", Buffer (One) { 0x00 }, "model", Buffer (0x16) { "Intel DSL6540 USB 3.1" }, "name", Buffer (0x1D) { "Intel DSL6540 XHC Controller" }, "device-id", Buffer (0x04) { 0xB6, 0x15, 0x00, 0x00 }, "USBBusNumber", Zero, "AAPL,XHCI-clock-id", One, "UsbCompanionControllerPresent", One }) } Name (HS, Package (0x01) { "XHC1" }) Name (FS, Package (0x01) { "XHC1" }) Name (LS, Package (0x01) { "XHC1" }) Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake { Return (Package (0x02) { 0x6D, Zero }) } Device (RHUB) { Name (_ADR, Zero) // _ADR: Address Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (SSP1) { Name (_ADR, One) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) Name (HS, Package (0x02) { "XHC1", 0x05 }) Name (FS, Package (0x02) { "XHC1", 0x05 }) Name (LS, Package (0x02) { "XHC1", 0x05 }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x08) { "UsbCPortNumber", 0x03, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8, "UsbCompanionPortPresent", One }) } } Device (SSP2) { Name (_ADR, 0x02) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) Name (HS, Package (0x02) { "XHC1", 0x06 }) Name (FS, Package (0x02) { "XHC1", 0x06 }) Name (LS, Package (0x02) { "XHC1", 0x06 }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x08) { "UsbCPortNumber", 0x04, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8, "UsbCompanionPortPresent", One }) } } Device (HS01) { Name (_ADR, 0x03) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) } Device (HS02) { Name (_ADR, 0x04) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address Name (_SUN, 0x02) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LNot (Arg2)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x02) { "PCI-Thunderbolt", One }) } } } }  
      Thanks to @nmano we now also have an additional SSDT, i.e SSDT-TB3-L02-BR2X.aml, which fixes further TB ACPI dependencies and which should be implemented in /EFI/Clover/ACPI/patches. This SSDT will permanently loads the TB NHI0 and XHC USB PCI drivers, even in case that no TB devices are connected. Apparently it also resolves some TB sleep/wake issues.   SSDT-TB3-L02-BR2X.aml can be substituted by a simple Clover DSDT patch to be included in the config plist:   Comment: BR2A BR2X THB patch ©N.Mano Find: 42523241 48303030 60865C2F 045F5342 5F504349 30425232 41483030 3160865C 2F045F53 425F5043 49304252 32414830 30326086 5C2F045F 53425F50 43493042 52324148 30303360 865C2F04 5F53425F 50434930 42523241 48303034 60865C2F 045F5342 5F504349 30425232 41483030 3560865C 2F045F53 425F5043 49304252 32414830 30366086 5C Replace: 42523258 55505342 60865C2F 055F5342 5F504349 30425232 58555053 42445342 3060865C 2F055F53 425F5043 49304252 32585550 53424453 42316086 5C2F055F 53425F50 43493042 52325855 50534244 53423260 865C2F05 5F53425F 50434930 42523258 55505342 44534233 60865C2F 055F5342 5F504349 30425232 58555053 42445342 3460862A 5C  
        E.10) iMac Pro Boot Splash Screen Cosmetics    Based on the ideas and instructions of @Matthew82, I achieved an iMacPro ASUS Boot Splash Screen     by means of the following procedure:   1.) Installation of the BREW distribution:   a.) Open a terminal and change to "bash" shell. bash  
      b.) Now enter the following "bash" terminal command and follow the standard BREW installation instructions: /usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)"  
      2.) After the successful installation of the BREW distribution, we have to implement the QT5 distribution, again by using a "bash" terminal shell. Enter the following "bash" terminal commands: brew install qt5 brew link qt5 --force  
      3.) After successfully implementing BREW and QT5 and if not already performed in Section B.1), we can now download the most actual CodeRush UEFIPatch distribution from Github to our home directory with the following terminal command: git clone https://github.com/LongSoft/UEFITool  
      4.) Now compile the UEFI Tool distribution with the following terminal commands: cd /UEFITools/ qmake uefitool.pro make  
      5.) Download and unzip iMacPro.raw to your Desktop.   6.) Now launch by UEFITool by clicking on the newly compiled UEFITool.app in the UEFITools Folder in your home directory.   a.) Select "File" -> "Open image file" and load your patched or unpatched BIOS Firmware distribution.   Select "Search.." in the UEFITool "Edit" Menu and perform a "GUID" search of "7BB28B99-61BB-11D5-9A5D-0090273FC14D" with "Header only"...     You will receive a message "GUID pattern "7BB28B99-61BB-11D5-9A5D-0090273FC14D" found as .... in 7BB28B99-....". Double click on that message and search for the "Raw section" accompanying the "7BB28B99-...." entry, which indeed is the Boot Image, which you can easily verify by extracting the raw section body (right-click on "Raw section" and select "Extract body") to your Desktop and by subsequently opening the extracted raw-file directly with Apple's "Preview.app" (right-click an the raw file and select "Open with.." -> Preview.app).   b.) To exchange the default original ASUS Boot Logo image file stored in "Raw Section" by the iMacPro.raw image file that you previously downloaded to your Desktop,  right-click again on "Raw section", select this time "Replace body"  and select the iMacPro.raw image file on your Desktop.     Note that the actual image dimension of iMacPro.raw (2131pix x 1457pix) was adopted for its use on my 38" LG 38UC99. For monitors with reduce screen resolution, iMacPro.raw might have to be adopted to an image dimension that suites your particular screen resolution, before its upload to "Raw section". If the Boot Logo image dimension is too big for your Monitor's screen resolution, you might just end up with a black screen during the BIOS initialisation at boot.   To do so, select in the Preview.app Menu -> "Tools" -> "Adjust Size". Change the image dimension and save the modified image with "File" -> "Export". In the "Export menu" press "Save", after selecting "JPEG" under "Format" , after choosing "Desktop" as the place to store the image, and after entering the new file name, which has to end with ".jpg".   Double-check by right-clicking on the resulting jpg image file and selecting "Get Info" that its file size does no exceed 200KB by far. If the latter would be the case, you would not be able to save the modified BIOS Firware file subsequently.   Finally just rename your new "XXXX.jpg" file to "XXXX.raw....   I guess, that by following the procedure detailed above, it is obvious that iMacPro.raw also can be substituted by any other image of your personal choice. Just be aware that it's background colour should be black (ecstatic reason for a its nice integration within the else black ASUS BIOS Boot Screen)   c.)  After replacing "Raw Section" with iMacPro.raw or the XXX.raw image of your choice, save your modified BIOS Firmware File with the Option "File" -> "Save Image File..."   d.) Copy your modified BIOS Firmware file to a USB3.0 Flash Drive, formatted with FAT32.   e.) Reboot, enter the Mainboard BIOS and save your BIOS settings to the USB Flash Drive   f.) Flash your mainboard BIOS with the modified BIOS Firmware   g.) Renter the Mainboard BIOS and restore your BIOS settings from the USB Flash Drive   h.) Save your restored BIOS settings with (F7) and (F10), reboot and you are done.   Just don't forget to set BIOS Setting "Boot Logo Display" to "Auto", when using this new approach. Any different setting might result in a black screen during BIOS initialisation.     E.11) iMac Pro Desktop Background Cosmetics    It might be nice to equip your iMac Pro X299 also with the adequate iMac Pro Desktop Background.   1.) Download, unzip and copy imac-pro-wallpaper.jpg.zip to your Dektop   2.) Right-click with the mouse on your Desktop and select "Change Desktop Background.."   3.) In the left column click on the "+" and add your Desktop Folder   4.) Select imac-pro-wallpaper.jpg to be your new Desktop Background    E.12) iStatMenus Hardware Monitoring   Thanks to extended tweet session between @BJango, @gxsolace and myself, we achieved a major step forward in properly monitoring Skylake-X/X299 Hardware with iStatMenus. iStatMenus now correctly interfaces with the HWSensor and FakeSMC kext distribution provided by @interferenc. It also can be used for Broadwell-E/EP, Haswell-E/EP, X99 system monitoring, with the tiny drawback that for CPUs with less then 18 cores the CPU numeration seems still erroneous. My distributed EFI-Folder already contains all necessary HWSensor and FakeSMC kexts.    The most actual iStatMenus v6.1 distribution can be assessed at https://bjango.com/mac/istatmenus/   The most actual HWSensor and FakeSMC kext distribution of @interferenc can be separately assessed at https://github.com/interferenc/HWSensors.    To compile the the HWSensor and FakeSMC kexts of @interferenc, perform the individual steps detailed below:   1.) git clone https://github.com/interferenc/HWSensors 2.)
      cp HWSensors ~/Desktop/ 3.)
      cd ~/Desktop/HWSensors 4.)
      xcodebuild -project Versioning\ And\ Distribution.xcodeproj/ 5.)
      xcodebuild -project HWMonitor.xcodeproj/ 6.)
      xcodebuild -project HWSensors.xcodeproj -alltargets  
      Subsequently, one finds the all compiled binaries in ~/Desktop/HWSensors/Binaries/.   Note that all compiled kext binaries are once more attached towards the bottom of this originating thread (guide). Just download and unzip HW-Sensors-IF.zip and copy all kexts to /EFI/Clover/kexts/Other/. Note that this pre-compiled binary package already implements a modified GPU Sensor kext of @Kozlek, which should also account for Polaris GPUs.   Many thanks to both @interferenc and @Bjango for their awesome and extensive contributions and brilliant work!   Broadwell-E/EP, Haswell-E/EP, X99 iStatMenus Hardware Sensor Data:     Broadwell-E/EP, Haswell-E/EP CPU Thread Utilisation Graphs:     To change from CPU core to thread utilisation monitoring, uncheck "Hide Hyper-Threading cores" in Section "CPU & GPU" of iStatMenus Preferences.     Temperature unites can be adjusted between Celsius, Fahrenheit and Kelvin in Section "Sensors" of iStatMenus Preferences.       F.) Benchmarking   F.1) i7-6950X CPU Benchmarks             F.2) Gigabyte AORUS GTX 1080 Ti 11GB Xterme Edition OpenGL and Metal Benchmarks   Yet to be implemented to be implemented once a macOS 10.14 Mojave Web Driver has been released.     G.) Summary and Conclusions   Already under macOS 10.12 Sierra and macOS 10.13 High Sierra, Broadwell-E/EP, Haswell-E/EP, X99 systems reached full functionality together with flawless stability. Now with macOS 10.14 Mojave, it might be another opportunity to follow my iMac Pro Build and Desktop Guide to unfold the unbelievable Broadwell-E/EP, Haswell-E/EP, X99 potential!   High-end builds based on Broadwell-E/EP, Haswell-E/EP, X99 technology have found manifold application, not only in science and research at universities or research institutions, engineering facilities, or medical labs, etc... Broadwell-E/EP, Haswell-E/EP, X99 with up to 22 cores (44 threads) and turbo frequencies up to 4.4 GHz have made X99 to a "relatively cheap" but really serious alternative to real iMac Pro's and Mac Pro's. The principal intention of my desktop guides is to demonstrate, that we are able to build and configure fully functional and relatively "low-cost" high-end systems, which go far beyond of what Apple is able to offer at present or will be ever able to offer for some reasonable pricing. Broadwell-E/EP, Haswell-E/EP, X99 Systems that allow the use of all software-packages developed for MacOS, Unix, Linux or even Windows at the same time (e.g. think on Vine, Parallels, or a dual boot system configuration). The flexibility between different mainboards (Asus, Gigabyte, ASRock, MSI, etc.), different Broadwell-E/EP, Haswell-E/EP processors, and different RAM memory configurations (16-128GB) make such systems affordable for anybody (also home office, audio and video editing/production, etc.) and allows their perfect adaptation for each specific purpose, requirement and available budget. It might not be necessary to outline, that current Broadwell-E/EP, Haswell-E/EP, X99 Systems perform absolutely stable on a 24/7/365 basis.   I am a scientist, expert in solar physics, space weather forecast and related telescope/instrument/space-mission development. In the frame of my scientific research, I developed parallelized image reconstruction, spectral line inversion and numerical modeling algorithms/applications, which require tremendous parallelized calculation power, RAM memory and storage capacities to reduce, analyze and interpret extensive and pioneering scientific ground-based or space-born observational data sets. This basically was also the professional motivation for developing innovative iMac Pro macOS Builds iSPOR-S (imaging Spectropolarimetric Parallel Organized Reconstruction Servers running iSPOR-DP, the Imaging Spectropolarimetric Parallel Organized Reconstruction Data Pipeline software package for the GREGOR Fabry-Pérot Interferometer, located at the 1.5m GREGOR Solar Telescope (Europe's largest solar telescope) on Tenerife, Canary Islands, Spain) as well as for the entire related iMac Desktop Guide Development, which naturally shall also be of benefit for others.  Anybody interested can find more details on my personal webpage.  
       
    • By fusion71au
      Clover r4542 ISO compiled with GCC and minimal config.plist compatible for use in VMWare Workstation.
       
      Tested with unlocked Workstation 14 running OSX 10.9 -->10.14 guest in Windows X64 host.
       
      Installation
      1. Download and unzip "EFI_Clover_r4542 for VMware.zip". Mount Clover-v2.4k-4542-X64.iso by double clicking on it.
      2. Mount your VM's EFI System Partition eg in terminal
      sudo diskutil mount disk0s1   3. Copy EFI folder from step 1 into the EFI partition
      4. Shutdown the VM, add bios.bootDelay = "3000" to your VM's vmx file
      5. Reboot your VM, press <F2> to access the VMware Boot Manager and add CLOVERX64.efi to the boot menu.
       
      Substitute your own unique and valid MLB and ROM variables in the /EFI/CLOVER/config.plist (Rt Variables section) to activate iMessage/Facetime on your VM.
    • By PingoLinkin
      Motherboard: ASUS / X99 Deluxe II
      Chipset: Intel® X99
      Processador: i7-6800 LGA2011 v3
      Memoria: HyperX - DDR4 24000MHz - 32GB(2x16gb)
      Rede: Intel® I218V, 1 x Gigabit LAN; Intel® I211-AT, 1 x Gigabit LAN LAN; Dual Gigabit LAN controllers- 802.3az Energy Efficient Ethernet (EEE) appliance
      Audio: Realtek® ALC1150 com 8 canais
      Video: Geforce GTX 750 Ti 2GB SC DDR5 128 bits PCI-E 3.0 (1x DVI, 1x DisplayPort, 1x HDMI)
      Keyboard: Apple Aluminium
      Mouse: Microsoft
      HD: SAMSUNG SSD 840 EVO 1TB
       
      ///////////////////////////////////////////
       

       
      1 - Preparando PENBOOT:
        1.1 - Baixe a imagem do Sierra e deixe na pasta "Applications";
        1.2 - Formate o PenDrive e altere o nome para: "MyVolume";
        1.3 - Abra o Terminal e digite a seguinte linha de código, dê enter e quando solicitado digite sua senha. Aguarde o término da instalação, geralmente demora em torno de 20min:
      sudo /Applications/Install\ macOS\ Sierra.app/Contents/Resources/createinstallmedia --volume /Volumes/MyVolume --applicationpath /Applications/Install\ macOS\ Sierra.app  
       
      1.4 - Baixe a última versão do Clover EFI bootloader: Download
        1.5 - Abra o Clover, na última etapa, clique em Customize, depois marque a opção "Install for UEFI booting only", como na imagem abaixo:

       
        1.6 - Provavelmente a partição "EFI" estará montada, abra a partição e substitua a pasta "CLOVER" por esta CLOVER Asus X99 Deluxe II - Sierra.zip.
       
      2 - Configurando BIOS
        2.1 - Atualize sua BIOS para a versão mais recente, a minha é: 1902
        2.2 - Reset as configurações de sua BIOS em: Exit/Load Optimized Defaults;
        2.3 - Vá para: Boot/CMS (Compatibility Support Module)/Launch CMS: ENABLED;
        2.4 - Vá para: Boot/Secure Boot/OS Type: Other OS;
       
      3 - Instalando OS
        3.1 - Ligue o computador com o Pendrive espetado, ele automaticamente irá iniciar o Clover, caso isso não aconteça, na tela inicial da ASUS, pressione F8 para escolher o pendrive como boot primário;
        3.2 - Em algum momento futuro, seu clover pode não arrancar corretamente, caso isso aconteça, na tela inicial do CLOVER pressione F11 para limpar o NVRAM, ele irá reiniciar a máquina automaticamente, em seguida voltará a arrancar normalmente;
       
      4 - PÓS-INSTALAÇÃO
        4.1 - Inicie seu MAC temporariamente pelo Pendrive como boot primário;
        4.2 - Instale o clover seguindo as etapas 1.4, 1.5 e 1.6 . Apenas não esqueça de alterar o destino para o HD Interno com a instalação do Sierra.
        4.3 - Feito isso, reinicie seu mac, agora sem o pendrive;
       
      5 - VÍDEO
        5.1 - Na pasta CLOVER que anexei acima, já possui as kexts NvidiaGraphicsFixup.kext e Lilu.kext ;
        5.2 - Baixe e instale o nVidia Web Driver(Download) de acordo com a versão do seu OS;
        5.3 - A minha versão, por exemplo, é: "macOS 10.12.6 (16G1408)";
        5.4 - Veja abaixo onde encontrar sua versão:

       
      Obs.: Existe um bug no vídeo, caso queira utilizar a entrada DVI, é preciso iniciar a máquina já com o cabo plugado, caso contrário ele deixará sua tela preta e não voltará mais ao normal até que reinicie a máquina.
       
        5.5 - INSTALANDO O CUDA:
           1 - A última versão não funcionou, então baixei a penúltima e funcionou perfeitamente. A versão instalada foi: CUDA 387.178 driver for MAC.

       
       
      6 - ÁUDIO
        6.1 - Baixe o Voodoo HDA 2.9.0 Clover (Download)
        6.2 - Siga as etapas das imagens que estão dentro do anexo;
       
       
      Não solucionado:
      Não consigo habilitar a placa ThunderboltEX 3;
       
       
      Valeu.
    • By MaLd0n
      First... If you need DSDT edits for SkyLake, KabyLake or CoffeeLake... -Post your full Clover folder with original tables in Origin folder(Extract with F4 in Clover boot screen) -Run it, post files generated in your desktop RunMe.app  Installation   --Create a bootable copy of macOS Sierra Check out the link http://www.insanelymac.com/forum/files/file/559-flash-drive-maker/   --Create a bootable copy of macOS HighSierra Check out the link http://diskmakerx.com/   --Install Clover in USB stick https://sourceforge.net/projects/cloverefiboot/files/Installer/   --Replace with my Clover folder  CLOVER.zip   --Install Sierra/High Sierra and boot into system!   Post Installation   --Install Clover in HDD/SSD and replace with my folder CLOVER.zip   --Reboot and activate video!   -Nvidia WebDriver Sierra http://www.insanelymac.com/forum/topic/312525-nvidia-web-driver-updates-for-macos-sierra-update-07212017/ -Nvidia WebDriver High Sierra http://www.insanelymac.com/forum/topic/324195-nvidia-web-driver-updates-for-macos-high-sierra-update-10162017/ -Cuda http://www.insanelymac.com/forum/topic/302795-cuda-90214-is-out-update-10162017/   --DSDT My DSDT with patches for Skylake DSDT.MaLd0n ASUS Z170M PLUS.zip   Patches -FIX ERRORS AND WARNINGS -HPET -SATA -SLPB -DMAC -DARWIN -LPC -XHCI -PLUGIN TYPE -HDAS to HDEF -HDEF -RTC -IRQs -SBUS -BUS1 -MCHC -ALS0 -SHUTDOWN -LAN -USBX -PMCR -EC -IMEI -PNLF -HDMI --FakeSMC
      http://www.hwsensors.com/releases   --Audio https://github.com/vit9696/AppleALC   --USB https://bitbucket.org/RehabMan/os-x-usb-inject-all/downloads   --LAN https://github.com/Mieze/IntelMausiEthernet   -Credits and thanks to the old and new people in the community who developed patches, kexts and bootloaders!   Slice, Kabyl, usr-sse2, jadran, Blackosx, dmazar, STLVNUB, pcj, apianti, JrCs, pene, FrodoKenny, skoczy, ycr.ru, Oscar09, xsmile, SoThOr, RehabMan, Download-Fritz, Zenit432, cecekpawon, Intel, Apple, Oracle, Chameleon Team, crazybirdy, Mieze, Mirone, Oldnapalm, netkas, Elconiglio, artut-pt, ErmaC, Pavo, Toleda, Master Chief and family, bcc9, The King, PMheart, Sherlocks, Micky1979, vit9696, vandroiy2013, Voodoo Team, Pike R. Alpha, lvs1974, Austere.J, CVad and many, many, many others!   We're all here to have fun and learn from each other!   ENJOY!
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