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Differences are noted in Audio (item 14) and Network (item 18).
I've made my Gigabyte GA-EX58-UD5 functionally as close to a single processor MacPro4,1 as possible, and in some ways it's better than the Apple hardware that can't be over clocked, has only four memory slots instead of six, has only one analog line out instead of four, and lacks external SATA ports.
My 4 Ghz Geekbench score of 14124 is higher than that of the 2.26 GHz dual processor Apple hardware MacPro4,1.
Using a DSDT.aml can bring you closer to actual Apple hardware functionality;
- No CMOS reset after reboot without ElliottForceLegacyRTC.kext or similar (CMOS reset during wake as of 10.7.0, see item 24 below for a fix)
- Audio without additional kexts (ALC889A audio option A with 10.6.x)
- Sleep using native power management without SleepEnabler.kext
- Lower CPU temperatures using native power management without NullCPUPowerManagement.kext
- Turbo plus one clock ratio
- Shutdown without EvOreboot.kext or similar
- Enable the power button to sleep and wake the computer
Native power management will be seen in kernel.log during boot;
kernel[0]: AppleIntelCPUPowerManagementClient: ready
kernel[0]: AppleIntelCPUPowerManagement: Turbo Ratios 1112
kernel[0]: AppleIntelCPUPowerManagement: initialization complete
What `Turbo Ratios 1112' means is that one core will clock to turbo plus one, when the other three cores aren't being utilized.
For a 2.66 GHz i7 920 or Xeon W3520 the multiplier for turbo is 21, and this will give BCLK times 22.
Page three of Gigabyte's corei7_x58_bios_guide.pdf alludes to this functionality.
Note: There is a bug in 10.6.8 that shows incorrect turbo ratios, but it's fixed as of 10.7.0.
MSR Tools can be used to see the CPU speed fluctuations (32 bit).
Use it with caution, as there is a chance that it will lock up and cause a system hang if force quit.
The following example is with an i7 920 or Xeon W3520 CPU, BCLK frequency changed from 133 to 185, and CPU clock ratio set to the standard 20 with turbo enabled.
x20;
Max Frequency: 3.70 GHz
Actual Frequency: 3.70 GHz (100%)
x21;
Max Frequency: 3.70 GHz
Actual Frequency: 3.89 GHz (105%)
x22;
Max Frequency: 3.70 GHz
Actual Frequency: 4.07 GHz (110%)
The mark-i application can also be used (32 and 64 bit), see post 692;
http://www.insanelym...c=196771&st=691
Speed step;
This will reduce clock speed as low as a x12 multiplier under idle conditions.
Enabling native power management with DSDT modifications will bring lower CPU temperatures, and speed step will go even lower, but only if using the Dynamic Vcore (DVID) feature of the BIOS.
DVID was added in version F9m of the GA-EX58-UD5 BIOS, check the Gigabyte BIOS beta thread for when it was added in the other models.
10.6.0 and 10.6.1:
Use MP41SpeedStepFix.kext.
10.6.0 through 10.6.3:
Save a copy of /System/Library/Extensions/IOPlatformPluginFamily.kext, add the PLimitDict and StepDataDict sections from /System/Library/Extensions/IOPlatformPluginFamily.kext/Contents/PlugIns/ACPI_SMC_PlatformPlugin.kext/Contents/Resources/MacPro3_1.plist to the same location in MacPro4_1.plist, and change the two key values from MacPro3,1 to MacPro4,1.
Watch the OS update it's extensions cache and any helper partitions in system.log and restart.
10.6.3 with Mac Pro Audio Update 1.1, and 10.6.4 through current:
Apple has enabled speed step in an updated MacPro4_1.plist.
To confirm, use ioreg to look at IOService:/AppleACPIPlatformExpert/CPU0@0/AppleACPICPU/ACPI_SMC_PlatformPlugin.
You will see CPUPLimit with a value of 0x0, a different value if it's not activated, or not there at all if not enabled.
Idle temperature comparison:
Idle CPU temperatures at 4.3 GHz (turbo disabled) and 19 C ambient; 42-46 C
Idle CPU temperatures at 4.3 GHz (turbo disabled) with a speed step MacPro4_1.plist, and 19 C ambient; 42-46 C
Idle CPU temperatures at 4.3 GHz (turbo disabled) with a speed step MacPro4_1.plist, DVID, and 19 C ambient; 35-39 C
ECC memory;
If you have a Xeon CPU, you can use error correcting code (ECC) memory, just like the Apple hardware uses.
Gigabyte doesn't list this as supported, but it works fine.
Create a Memtest86+ boot CD and it will show the following with a Xeon CPU and ECC memory;
Chipset : NHM IMC (ECC : Detect / Correct) Scrub+
It will show the following with a Xeon or i7 CPU and non ECC memory;
Chipset : NHM IMC (ECC : Disabled)
Set the following in /System/Library/SystemProfiler/SPMemoryReporter.spreporter/Contents/Resources/English.lproj/Localizable.strings to correct the cosmetic misreporting of ECC as disabled in System Profiler:Hardware:Memory;
"dimm_type" = "Type";"DDR3"="DDR3 ECC";
"ecc_disabled" = "Disabled";"Disabled"="Enabled";
For confirmation that it's working, here's what you'll see in kernel.log if a cosmic ray flips a bit, or if you've over clocked your memory improperly;
Aug 13 18:23:06 mac05 kernel[0]: AppleTyMCEDriver ReadCorrectable : Detected 1 errors on channel 2 dimm 1 package 0
Aug 13 18:23:16 mac05 kernel[0]: AppleTyMCEDriver ReadCorrectable : Detected 1 errors on channel 1 dimm 0 package 0
Aug 13 18:23:19 mac05 kernel[0]: AppleTyMCEDriver ReadCorrectable : Detected 1 errors on channel 1 dimm 0 package 0
Here's what you'll see in System Profiler:Hardware:Memory;
Memory Slots: ECC: Enabled Bank0/1/A0: Size: 2 GB Type: DDR3 ECC Speed: 1640 MHz Status: OK Manufacturer: Kingston Part Number: 9905413-009.A00LF Serial Number: 0x66cceebc Bank2/3/A1: Size: 2 GB Type: DDR3 ECC Speed: 1640 MHz Status: OK Manufacturer: Kingston Part Number: 9905413-009.A00LF Serial Number: 0x6accadbc Bank4/5/A2: Size: 2 GB Type: DDR3 ECC Speed: 1640 MHz Status: OK Manufacturer: Kingston Part Number: 9905413-009.A00LF Serial Number: 0x66cc91bc Bank6/7/A3: Size: 2 GB Type: DDR3 ECC Speed: 1640 MHz Status: ECC Errors ECC Correctable Errors: 2 Manufacturer: Kingston Part Number: 9905413-009.A00LF Serial Number: 0x6acc64bc Bank8/9/A4: Size: 2 GB Type: DDR3 ECC Speed: 1640 MHz Status: ECC Errors ECC Correctable Errors: 1 Manufacturer: Kingston Part Number: 9905413-009.A00LF Serial Number: 0x69ccecbc Bank10/11/A5: Size: 2 GB Type: DDR3 ECC Speed: 1640 MHz Status: OK Manufacturer: Kingston Part Number: 9905413-009.A00LF Serial Number: 0x66cce8bcDSDT modifications;
The easiest way to create a DSDT.aml is to reboot without a DSDT.aml, using fakesmc.kext, NullCPUPowerManagement.kext to not KP, ElliottForceLegacyRTC.kext to not reset the CMOS, and then use the DSDTSE application to extract the dsdt.dsl, edit it and compile it into dsdt.aml.
Another way is to reboot without a DSDT.aml, with the three kexts, and get an unmodified dsdt.dat by running getDSDT.sh.
Run `./iasl -d dsdt.dat', edit dsdt.dsl with vi or similar, then get dsdt.aml from running `./iasl -ta dsdt.dsl'.
Either way, copy dsdt.aml to the bootloader's Extra folder as DSDT.aml.
The compiler changes 0x00 to Zero, 0x01 to One, removes some comments, shortens some hex, etc., so you will see differences when comparing dsdt.dsl and it's dsdt.aml in DSDTSE.
Save the clean dsdt.dsl derived from each BIOS that you use.
If the clean dsdt.dsl derived from the new BIOS is the same, then no modification to your original modified dsdt.dsl is needed.
GA-EX58-UD5 BIOS F9e added support for CPUs with more than four cores, and F9m added DVID.
Both resulted in additional code in the dsdt.dsl derived from them.
Also keep in mind that a BIOS setting could change the derived dsdt.dsl.
However, I've only seen the sleep setting do this so far.
When you derive dsdt.dsl from a BIOS set to S1(POS) sleep you get;
Name (\_S1, Package (0x04)
and
Name (\SS3, Package (0x04)
and
...
When you derive dsdt.dsl from a BIOS set to S3(STR) sleep you get;
Name (\SS1, Package (0x04)
and
Name (\_S3, Package (0x04)
and
...
If you have a GA-EX58-UD5 with an i7 920 or Xeon W3520, i7 930 or Xeon W3530, i7 950 or Xeon W3550, or i7 975 or Xeon W3580, you can use BIOS F9m through F12 and the attached DSDT.aml files (do 6 and 7).
or
If you have a GA-EX58-UD5 and you are using at least C2RC5 trunk revision 192 you can use BIOS F9m through F13U and the attached standard PR scope DSDT.aml files (don't do 6, do 7 and 20).
or
Make your own if have a different GA-EX58 or GA-X58A MB.
Is it possible to use a DSDT.aml created from a dsdt.dsl from a different MB?
No, because there are significant differences in the unmodified dsdt.dsl file from each GA-EX58 model.
GA-X58A-UD7 rev 1.0 and GA-X58A-UD3R rev 1.0 differ only in the address base in `Device (PCI0.EXPL)'.
GA-X58A-UD3R rev 2.0 is significantly different from rev 1.0.
GA-X58A-UD5 rev 2.0 is significantly different from rev 1.0.
GA-X58A-UD3R rev 2.0 is significantly different from GA-X58A-UD5 rev 2.0.
I'm looking for an unmodified dsdt.dsl from the following boards (*);
GA-EX58-EXTREME (bulier - F12)
GA-EX58-UD5 (me)
GA-EX58-UD4P (MowgliBook - various)
GA-EX58-UD4 *
GA-EX58-DS4 *
GA-EX58-UD3R revision 1.7 *
GA-EX58-UD3R revision 1.6 (smc13)
GA-EX58-UD3R revision 1.0 (callumj09 - F9)
GA-EX58-UD3R-SLI *
GA-X58A-UD9 *
GA-X58A-UD7 revision 2.0 *
GA-X58A-UD7 revision 1.0 (semendemon - ?)
GA-X58A-UD5 revision 2.0 (newnekton1 - FA)
GA-X58A-UD5 revision 1.0 (gunnerfan - ?)
GA-X58A-UD3R revision 2.0 (howboutjoe - FA)
GA-X58A-UD3R revision 1.0 (Lyle M - F2c)
The code in the following code boxes may loose their formatting with copy and paste.
The attached DSDT archives have both dsdt.dsl and DSDT.aml files.
Open the dsdt.dsl (or do `./iasl -d DSDT.aml' to get dsdt.dsl), then copy and paste from that.
1A. To fix the Local0 compile error, add quotation marks to the `Scope (\_SI)' section.
The dsdt.dsl won't compile without this modification.
original:
Scope (\_SI)
{
Method (_MSG, 1, NotSerialized)
{
Store (Local0, Local0)
}
Method (_SST, 1, NotSerialized)
{
Store (Local0, Local0)
}
}
modified:
Scope (\_SI)
{
Method (_MSG, 1, NotSerialized)
{
Store ("Local0", Local0)
}
Method (_SST, 1, NotSerialized)
{
Store ("Local0", Local0)
}
}
1B. (added 20110901, thanks to aikidoka25 and JUN Ho) Newer iasl versions will have a compilation error with the `0xFFF00000, // Length' line, change it to `0xFEB00000, // Length'.2. To fix the _WAK compile warning, add to the end of the `Method (\_WAK, 1, NotSerialized)' section.
original:
Notify (\_SB.PCI0.USB0, 0x00) Notify (\_SB.PCI0.USB1, 0x00) Notify (\_SB.PCI0.USB2, 0x00) Notify (\_SB.PCI0.USB3, 0x00) Notify (\_SB.PCI0.USB4, 0x00) Notify (\_SB.PCI0.USB5, 0x00) }modified:
Notify (\_SB.PCI0.USB0, 0x00)
Notify (\_SB.PCI0.USB1, 0x00)
Notify (\_SB.PCI0.USB2, 0x00)
Notify (\_SB.PCI0.USB3, 0x00)
Notify (\_SB.PCI0.USB4, 0x00)
Notify (\_SB.PCI0.USB5, 0x00)
Return (Package (0x02)
{
Zero,
Zero
})
}
3. To solve the CMOS issue that resets the BIOS back to default, in `Device (RTC)' change the the two instances of 0x04 to 0x02.RTC stands for Real Time Clock.
There's a good explanation of why the IO segment's length needs to be reduced at netkas's site.
The ACPI (Advanced Configuration & Power Interface) specifications are at http://www.acpi.info/.
I'd suggest looking at ACPIspec40.pdf, although Gigabyte seems to be 1.0 in DSDT;
* Revision 0x01 **** ACPI 1.0, no 64-bit math support
There's also some good information at http://www.acpica.org/documentation/.
Note: CMOS reset during wake as of 10.7.0, see item 24 below for a fix.
original:
Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (ATT0, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x04, // Length
)
IRQNoFlags ()
{8}
})
Name (ATT1, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x04, // Length
)
})
modified:
Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (ATT0, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x02, // Length
)
IRQNoFlags ()
{8}
})
Name (ATT1, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x02, // Length
)
})
4. To allow layout-id, etc. insertion modifications to DSDT, add the following before the `Method (\_WAK, 1, NotSerialized)' section.
Method (DTGP, 5, NotSerialized)
{
If (LEqual (Arg0, Buffer (0x10)
{
/* 0000 */ 0xC6, 0xB7, 0xB5, 0xA0, 0x18, 0x13, 0x1C, 0x44,
/* 0008 */ 0xB0, 0xC9, 0xFE, 0x69, 0x5E, 0xAF, 0x94, 0x9B
}))
{
If (LEqual (Arg1, One))
{
If (LEqual (Arg2, Zero))
{
Store (Buffer (One)
{
0x03
}, Arg4)
Return (One)
}
If (LEqual (Arg2, One))
{
Return (One)
}
}
}
Store (Buffer (One)
{
0x00
}, Arg4)
Return (Zero)
}
5. The BIOS has capability for up to 16 threads, but only 8 and 12 thread CPUs have been released to date.For CPU0 through CPU7 for the 8 thread CPUs, or CPU0 through CPUB for the 12 thread i7 980 or Xeon W3680, make changes to pass the CStates to OS X.
This is only needed when clocked over a certain point (148x20 or 2.96 GHz for a i7 920 or Xeon W3520 CPU), as the OS doesn't see the CStates available to it, even with all energy saving options enabled in the BIOS's Advanced CPU Features section.
If you convert the hexadecimal you will find that the PStates represent the default clock of your CPU, but it won't down clock your CPU if over clocked, and is what the BIOS makes available to the OS at default or over clock.
If you have a different CPU your specific PStates can be obtained from running getSSDT5.sh to get SSDT-0.dsl, or from using DSDTSE.
Do this after rebooting at default clock with fakesmc.kext, NullCPUPowerManagement.kext to not KP, ElliottForceLegacyRTC.kext to not reset the CMOS, EIST, C1E and C3/C6/C7 States enabled, and no DSDT.aml.
Why do you need to add specific PStates for your CPU when it's the CStates that drop out above a certain point?
It's because when DropSSDT=yes (item 6) is used, you are telling the bootloader to drop both CStates and PStates and instead read them from the DSDT, and if you had only added CStates to the DSDT there would be no PStates.
To confirm, use ioreg to look at IOService:/AppleACPIPlatformExpert/CPU0@0/AppleACPICPU/ACPI_SMC_PlatformPlugin.
You will see the CState's CSTinfo and the PState's PerformanceStateArray.
Note: CSTInfo has been renamed to AICPMVers as of 10.6.8.
Note:
Don't add this section if you are using at least C2RC5 trunk revision 192, as it will make CStates available to the OS (don't do 6, do 7 and 21).
original:
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06) {}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06) {}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06) {}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06) {}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06) {}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06) {}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06) {}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 10 PState i7 920 and Xeon W3520:
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x0060,
0x0000015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},
0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0A)
{
Package (0x06)
{
0x00000A65,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},
Package (0x06)
{
0x00000A64,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},
Package (0x06)
{
0x000009DF,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},
Package (0x06)
{
0x0000095A,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},
Package (0x06)
{
0x000008D5,
0x00014438,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},
Package (0x06)
{
0x00000850,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},
Package (0x06)
{
0x000007CB,
0x0000F618,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},
Package (0x06)
{
0x00000746,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},
Package (0x06)
{
0x000006C1,
0x0000B798,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},
Package (0x06)
{
0x0000063C,
0x0000A7F8,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 11 PState i7 930 and Xeon W3530 (added 20100425):
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x0060,
0x0000015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},
0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0B)
{
Package (0x06)
{
0x00000AEA,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},
Package (0x06)
{
0x00000AE9,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},
Package (0x06)
{
0x00000A64,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},
Package (0x06)
{
0x000009DF,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},
Package (0x06)
{
0x0000095A,
0x00014438,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},
Package (0x06)
{
0x000008D5,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},
Package (0x06)
{
0x00000850,
0x0000F618,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},
Package (0x06)
{
0x000007CB,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},
Package (0x06)
{
0x00000746,
0x0000CB20,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},
Package (0x06)
{
0x000006C1,
0x0000A7F8,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},
Package (0x06)
{
0x0000063C,
0x00009C40,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 13 PState i7 950 and Xeon W3550 (added 20091222):
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x0060,
0x0000015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},
0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0D)
{
Package (0x06)
{
0x00000BF4,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000018,
0x00000018
},
Package (0x06)
{
0x00000BF3,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000017,
0x00000017
},
Package (0x06)
{
0x00000B6E,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},
Package (0x06)
{
0x00000AE9,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},
Package (0x06)
{
0x00000A64,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},
Package (0x06)
{
0x000009DF,
0x00014438,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},
Package (0x06)
{
0x0000095A,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},
Package (0x06)
{
0x000008D5,
0x00010D88,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},
Package (0x06)
{
0x00000850,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},
Package (0x06)
{
0x000007CB,
0x0000CB20,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},
Package (0x06)
{
0x00000746,
0x0000B798,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},
Package (0x06)
{
0x000006C1,
0x00009C40,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},
Package (0x06)
{
0x0000063C,
0x00008CA0,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 15 PState i7 975 and Xeon W3580 (added 20100109):
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x0060,
0x0000015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},
0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0F)
{
Package (0x06)
{
0x00000CFE,
0x000493E0,
0x0000000A,
0x0000000A,
0x0000001A,
0x0000001A
},
Package (0x06)
{
0x00000CFD,
0x000493E0,
0x0000000A,
0x0000000A,
0x00000019,
0x00000019
},
Package (0x06)
{
0x00000C78,
0x0003C4D8,
0x0000000A,
0x0000000A,
0x00000018,
0x00000018
},
Package (0x06)
{
0x00000BF3,
0x00036B00,
0x0000000A,
0x0000000A,
0x00000017,
0x00000017
},
Package (0x06)
{
0x00000B6E,
0x00031510,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},
Package (0x06)
{
0x00000AE9,
0x0002C6F0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},
Package (0x06)
{
0x00000A64,
0x00027CB8,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},
Package (0x06)
{
0x000009DF,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},
Package (0x06)
{
0x0000095A,
0x0001C520,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},
Package (0x06)
{
0x000008D5,
0x00018E70,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},
Package (0x06)
{
0x00000850,
0x00016378,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},
Package (0x06)
{
0x000007CB,
0x00013880,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},
Package (0x06)
{
0x00000746,
0x0000F230,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},
Package (0x06)
{
0x000006C1,
0x0000D6D8,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},
Package (0x06)
{
0x0000063C,
0x0000BB80,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 15 PState i7 980 and Xeon W3680 (added 20100523):Note;
10.6.3: Not fully supported by the OS, start with sasta's post 701;
http://www.insanelym...c=196771&st=700
10.6.4: Supported by the OS, but the bootloader may need modification to prevent fast RTC;
http://www.tonymacx8...de2487086daac8c
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x0060,
0x0000015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},
0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0F)
{
Package (0x06)
{
0x00000CFE,
0x000493E0,
0x0000000A,
0x0000000A,
0x0000001A,
0x0000001A
},
Package (0x06)
{
0x00000CFD,
0x000493E0,
0x0000000A,
0x0000000A,
0x00000019,
0x00000019
},
Package (0x06)
{
0x00000C78,
0x0003C4D8,
0x0000000A,
0x0000000A,
0x00000018,
0x00000018
},
Package (0x06)
{
0x00000BF3,
0x00036B00,
0x0000000A,
0x0000000A,
0x00000017,
0x00000017
},
Package (0x06)
{
0x00000B6E,
0x00031510,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},
Package (0x06)
{
0x00000AE9,
0x0002C6F0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},
Package (0x06)
{
0x00000A64,
0x00027CB8,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},
Package (0x06)
{
0x000009DF,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},
Package (0x06)
{
0x0000095A,
0x0001C520,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},
Package (0x06)
{
0x000008D5,
0x00018E70,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},
Package (0x06)
{
0x00000850,
0x00016378,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},
Package (0x06)
{
0x000007CB,
0x00013880,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},
Package (0x06)
{
0x00000746,
0x0000F230,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},
Package (0x06)
{
0x000006C1,
0x0000D6D8,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},
Package (0x06)
{
0x0000063C,
0x0000BB80,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
6. To make the CPU changes work correctly, add the following to com.apple.Boot.plist (don't add if you're using at least C2RC5 trunk revision 192);<key>DropSSDT</key>
<string>yes</string>
7. Identify your machine as MacPro4,1 in smbios.plist (not needed if you're using at least C2RC5 trunk revision 313).
<key>SMproductname</key>
<string>MacPro4,1</string>
8A. Use OrangeIconFix.kext to fix the orange drives seen in the Finder (not needed as of 10.7.0).
8B. To make the drives show correctly as Intel ICH10 AHCI in System Profiler's Serial-ATA section, add the following to the `Device (IDE1)' section (put above `Device (PRIM)').
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x02)
{
"device-id",
Buffer (0x04)
{
0x22, 0x3A, 0x00, 0x00
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
9. Modify the `Device (PX40)' section so that AppleLPC.kext loads.This is needed for native power management, and for the `Start up automatically after a power failure' option to appear in Energy Saver.
This must be checked or sleep will shut the computer down instead, unless 17 is also done.
The following is seen from running `OSX86 Tools Utility:View PCI Device/Vendor ID' on GA-EX58-UD5.
00:1f.0 ISA bridge [0601]: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller [8086:3a16]
The device-id should be one that's in /System/Library/Extensions/AppleLPC.kext/Contents/Info.plist (<string>pci8086,3a18</string>).
original:
Device (PX40)
{
Name (_ADR, 0x001F0000)
OperationRegion (PREV, PCI_Config, 0x08, 0x01)
Scope (\)
modified:
Device (PX40)
{
Name (_ADR, 0x001F0000)
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x02)
{
"device-id",
Buffer (0x04)
{
0x18, 0x3A, 0x00, 0x00
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
OperationRegion (PREV, PCI_Config, 0x08, 0x01)
Scope (\)
10. Modify the `Device (HPET)' section so that AppleHPET.kext loads.The AppleHPET kext needs to load so that the AppleIntelCPUPowerManagement and AppleIntelCPUPowerManagementClient kexts can load without KP.
original:
Device (HPET)
{
Name (_HID, EisaId ("PNP0103"))
Name (ATT3, ResourceTemplate ()
{
IRQNoFlags ()
{0}
IRQNoFlags ()
{8}
Memory32Fixed (ReadWrite,
0xFED00000, // Address Base
0x00000400, // Address Length
)
})
Name (ATT4, ResourceTemplate ()
{
})
Method (_STA, 0, NotSerialized)
{
If (LGreaterEqual (OSFX, 0x03))
{
If (HPTF)
{
Return (0x0F)
}
Else
{
Return (0x00)
}
}
Else
{
Return (0x00)
}
}
Method (_CRS, 0, NotSerialized)
{
If (LGreaterEqual (OSFX, 0x03))
{
If (HPTF)
{
Return (ATT3)
}
Else
{
Return (ATT4)
}
}
Else
{
Return (ATT4)
}
}
}
modified:
Device (HPET)
{
Name (_HID, EisaId ("PNP0103"))
Name (ATT3, ResourceTemplate ()
{
IRQNoFlags ()
{0}
IRQNoFlags ()
{8}
Memory32Fixed (ReadWrite,
0xFED00000, // Address Base
0x00000400, // Address Length
)
})
Name (ATT4, ResourceTemplate ()
{
})
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Method (_CRS, 0, NotSerialized)
{
Return (ATT3)
}
}
11. Remove the IRQ from the PIC device to solve the audio stuttering problem.original:
Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0020, // Range Minimum
0x0020, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IO (Decode16,
0x00A0, // Range Minimum
0x00A0, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IRQNoFlags ()
{2}
})
}
modified:
Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0020, // Range Minimum
0x0020, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IO (Decode16,
0x00A0, // Range Minimum
0x00A0, // Range Maximum
0x01, // Alignment
0x02, // Length
)
})
}
12. Change HID to CID in the `Device (PWRB)' section to enable the power button to sleep and wake the computer.In BIOS set `ACPI Suspend Type' to `S3(STR)', this is the lower power suspend to RAM state.
Also set `Soft-Off by PWR-BTTN' to `Delay 4 Sec.', so less than four seconds will sleep (S3) or wake, and more than four seconds will shut down (S5).
`Allow power button to put the computer to sleep' must also be checked in Energy Saver.
original:
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
Method (_STA, 0, NotSerialized)
{
Return (0x0B)
}
}
modified:
Device (PWRB)
{
Name (_CID, EisaId ("PNP0C0C"))
Method (_STA, 0, NotSerialized)
{
Return (0x0B)
}
}
13. Modify fakesmc.kext/Contents/Info.plist in two places with MacPro4,1 specific information (1.30f3 and smc-napa changed to 1.39f5 and smc-thurley).original:
<key>REV </key> <data> ATAPAAAD </data> </dict> <key>smc-compatible</key> <string>smc-napa</string>modified:
<key>REV </key> <data> ATkPAAAF </data> </dict> <key>smc-compatible</key> <string>smc-thurley</string>14. Audio options (Griffin Technology iMic USB Audio Device can be used instead).
VoodooHDA for all GA-X58A and GA-EX58 models;
http://forum.voodoop...board,10.0.html
and
http://forum.voodoop...board,13.0.html
and
http://www.projectos...p?showtopic=355
GA-EX58-UD3R, GA-EX58-UD3R-SLI, GA-EX58-UD4 and GA-EX58-DS4 (Realtek ALC888);
10.6.0 through 10.6.2 (post 12):
http://www.insanelym...ic=140941&st=11
10.6.3 through 10.6.7:
A. Use How_to_patch_AppleHDA.zip:
http://www.insanelym...howtopic=140941
or
B. Use already patched AppleHDA (for 10.6.4, post 850):
http://www.insanelym...c=196771&st=849
and
Use HDAEnabler.kext in Extensions.mkext:
http://www.insanelym...howtopic=213808
and
original:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
andoriginal:
Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x03, 0x00, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
10.6.8 through current:?
GA-X58A-UD3R, GA-X58A-UD5, GA-X58A-UD7 and GA-X58A-UD9 (Realtek ALC889);
10.6.0 through 10.6.2 (post 677):
http://www.insanelym...c=140941&st=676
10.6.3 through 10.6.7:
A. Use How_to_patch_AppleHDA.zip:
http://www.insanelym...howtopic=140941
or
B. Use already patched AppleHDA (for 10.6.4, post 850):
http://www.insanelym...c=196771&st=849
and
Use Legacy889HDA.kext in Extensions.mkext (post 815):
http://www.insanelym...c=196771&st=814
and
original:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
andoriginal:
Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x79, 0x03, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
10.6.8 through current:?
GA-EX58-UD4P, GA-EX58-UD5 and GA-EX58-EXTREME (Realtek ALC889A);
A outputs analog 2.0
B outputs analog 2.0 and digital 5.1.
C outputs analog 5.1 and digital 5.1.
D outputs analog 7.1
There are less sound assertion messages in kernel.log with B and C, and none with D (not true anymore as of 10.6.?)
E outputs at least analog 2.0
A. To have 2.0 audio without any additional kext, make modifications to the `Method (_L0D, 0, NotSerialized)' section and the `Device (AZAL)' section.
Analog output is the green jack.
The layout-id 66 in hex is 0x42.
original:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
andoriginal:
Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x42, 0x00, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
orB. Thanks to aschar1 for the 2.0 ALC889a.kext.
For 10.6.0 and 10.6.1 (post 388);
http://www.insanelym...c=140941&st=387
For 10.6.2 through 10.6.7 (post 457);
http://www.insanelym...c=196771&st=456
Updated DSDT modification to reduce the popping noise after wake, and eliminate it at boot (post 548);
http://www.insanelym...c=196771&st=547
To use ALC889a.kext in Extensions.mkext, make modifications to the `Method (_L0D, 0, NotSerialized)' section and the `Device (AZAL)' section.
Analog output is the green jack.
The layout-id 12 in hex is 0x0C.
original:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
andoriginal:
Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x0C, 0x00, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
orC. Thanks to ANARCHiNTOSH for the AppleHDA 5.1 patcher (post 497);
http://www.insanelym...c=196771&st=496
or
D. Thanks to x.di for the 7.1 LegacyHDA.kext that works with 10.7.4 (or earlier) through current when using HDEF layout-id 12 in DSDT (post 511);
http://www.insanelym...c=196771&st=510
Update (post 686);
http://www.insanelym...c=196771&st=685
E. Thanks to aschar1 for a modified AppleHDA.kext that works with 10.6.8 through 10.7.2 (start with post 1226);
http://www.insanelym...=196771&st=1225
Thanks to aikidoka25 for noting that the output changed from green to black in 10.7.2, and for supplying a way to change it back (post 1302);
http://www.insanelym...=196771&st=1301
Thanks to aschar1 for a modified AppleHDA.kext that works with 10.7.3 (post 1345);
http://www.insanelym...=196771&st=1344
Thanks to JamesLittler for a modified AppleHDA.kext that works with 10.7.4 (post 1353);
http://www.insanelym...=196771&st=1352
Thanks to aschar1 for instructions to modify AppleHDA.kext to work with 10.7.4 through current (start with post 1351);
http://www.insanelym...=196771&st=1350
15. Having the driver for Temperature Monitor installed prevents idle sleep.
Setting `Avoid accessing drive sensors if user inactive:' in Temperature Monitor:Preferences:General:Disk Saver to a value greater than the `Computer sleep' value in Energy Saver doesn't change the behavior.
Thanks to kdawg for noting that iStat can be used instead, and that it doesn't prevent idle sleep if `Monitor S.M.A.R.T drive temps' is unchecked in the sensor section.
Various DVD drives prevent idle sleep, the solution may be to either uncheck `Put the hard disk(s) to sleep when possible' in Energy Saver, or to leave a DVD in the drive.
Another solution is to add the PenntNeu-script RIP.app in Accounts:<user>:Login Items.
To make this work I had to change main.scpt, although this has worked for others unmodified.
original:
if idleTime > systemSleepDelay then tell application "System Events" key code 58 end tell tell application "System Events" to sleep end ifmodified:
if idleTime > systemSleepDelay then do shell script "pmset sleepnow" end if16. (added 20091223) Thanks to mm67 for a modification that enables shutdown, so that EvOreboot.kext or similar isn't needed;
http://www.insanelym...c=192518&st=743 (start with post 744)
A kext would still be needed if you want restart functionality, unless you use Duvel300's patched boot, Asere's bootloader, the Chameleon-Mozodojo bootloader, or C2RC5;
http://www.insanelym...c=192518&st=870 (start with post 871)
Add the following before `OperationRegion (\AGPS, SystemIO, 0x0438, 0x04)'.
OperationRegion (PMRS, SystemIO, 0x0430, 0x01)
Field (PMRS, ByteAcc, NoLock, Preserve)
{
, 4,
SLPE, 1
}
andIn `Method (\_PTS, 1, NotSerialized)' change the following.
original:
If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
}
modified:
If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
Store (Zero, SLPE)
Sleep (0x10)
}
17. (added 20100103) Thanks to sr2, AudiSport, mm67, blackosx and [Master Chief|Unsubscribe Me|TheChief] for a modification that doesn't require `Allow power button to put the computer to sleep' to be checked for 9;
http://www.insanelym...c=196771&st=171 (post 172)
and
http://www.insanelym...c=192518&st=609 (start with post 610)
Add the following before `OperationRegion (PREV, PCI_Config, 0x08, 0x01)'.
OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
Field (LPC0, ByteAcc, NoLock, Preserve)
{
AG3E, 1
}
andChange `Method (\_PTS, 1, NotSerialized)'.
original:
Method (\_PTS, 1, NotSerialized)
{
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG1)
OSTP ()
If (LEqual (Arg0, 0x01)) {}
If (LEqual (Arg0, 0x03)) {}
If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
}
If (LEqual (Arg0, 0x04))
{
If (LNot (PICF))
{
Sleep (0x64)
}
}
}
modified (includes 16):
Method (\_PTS, 1, NotSerialized)
{
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG1)
OSTP ()
If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
Store (One, \_SB.PCI0.PX40.AG3E)
Store (Zero, SLPE)
Sleep (0x10)
}
Else
{
Store (Zero, \_SB.PCI0.PX40.AG3E)
}
}
18A. Network hardware for all GA-EX58 and GA-X58A models.
1. Intel Gigabit CT Desktop Adapter - network adapter, Mfg. Part: EXPI9301CT.
It's $40 or less and uses Apple's IONetworkingFamily.kext/Contents/PlugIns/Intel82574L.kext.
Instructions;
http://www.tonymacx8...php?f=19&t=4057
or
2. Apple USB Ethernet Adapter
18B. Network driver options for Realtek RTL8111C models: GA-EX58-UD3R rev. 1.6 and 1.7.
The Realtek RTL8111C is recognized by Apple's IONetworkingFamily.kext/Contents/PlugIns/AppleRTL8169Ethernet.kext, and also as IOBuiltin=Yes.
18C. Network driver options for Realtek RTL8111D models: GA-EX58-UD3R rev. 1.0, GA-EX58-UD3R-SLI, GA-EX58-UD4, GA-EX58-DS4, GA-EX58-UD4P, GA-EX58-UD5, GA-EX58-UD7, GA-X58A-UD3R rev. 1.0, GA-X58A-UD5 rev. 1.0 and GA-X58A-UD7 rev. 1.0.
The Realtek RTL8111D isn't recognized by the kexts supplied with the OS, but any of the following three can be used.
1. RTGMac_v2.0.5 supports 10.6, it updates Apple's IONetworkingFamily.kext/Contents/PlugIns/AppleRTL8169Ethernet.kext;
http://www.realtek.c...3&GetDown=false
or
2. Lnx2Mac has developed a Realtek RTL81xx driver;
http://lnx2mac.blogs...river-goes.html
or
3. Bit Shoveler's RealtekR1000SL.kext is Bonjour and WOL enabled, even though womp won't be seen with pmset, and `Wake for Ethernet network access' won't be seen in Energy Saver (post 631);
http://www.insanelym...ic=29436&st=630
18D. Network driver options for Realtek RTL8111E models: GA-X58A-UD3R rev. 2.0, GA-X58A-UD5 rev. 2.0, GA-X58A-UD7 rev. 2.0 and GA-X58A-UD9.
The Realtek RTL8111E isn't recognized by the kexts supplied with the OS, but either of the following two can be used.
1. RTGMac_v2.0.5 supports 10.6, it updates Apple's IONetworkingFamily.kext/Contents/PlugIns/AppleRTL8169Ethernet.kext;
http://www.realtek.c...3&GetDown=false
or
2. Lnx2Mac has developed a Realtek RTL81xx driver;
http://lnx2mac.blogs...river-goes.html
19. Network IOBuiltin options.
Some applications need en0 to be recognized as IOBuiltin=Yes, and there are at least four ways to fix this.
A. Add the following in org.chameleon.Boot.plist.
<key>EthernetBuiltIn</key>
<string>yes</string>
or
B. Thanks to Rudy Pedraza, modify Bit Shoveler's RealtekR1000SL.cpp source file and compile.
original:
if (pciDev != NULL)
{
pciDev->close(this);
}
modified:
if (pciDev != NULL)
{
pciDev->setProperty("built-in",1);
pciDev->close(this);
}
orC. Add the following within `Device (PEX4)'.
Device (LAN0)
{
Name (_ADR, 0x00)
Name (_PRW, Package (0x02)
{
0x0B,
0x04
})
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"built-in",
Buffer (0x01)
{
0x01
},
"device_type",
Buffer (0x09)
{
"ethernet"
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
orD. Add an ethernet EFI string that contains the built-in key with a value of 1 to com.apple.Boot.plist, see ~pcwiz's topic at http://www.insanelym...owtopic=114349.
However, you will need to run `gfxutil -f pex4' instead of `gfxutil -f ethernet' in Terminal to determine DevicePath.
20. (added 20100426) Video options.
A. Video is most simply enabled in org.chameleon.Boot.plist.
<key>GraphicsEnabler</key>
<string>yes</string>
or
B. Thanks to aschar1 for a modification to instead enable one or more video cards directly in DSDT (start with post 659);
http://www.insanelym...c=196771&st=658
21. (added 20100726) Add the following to org.chameleon.Boot.plist (was com.apple.Boot.plist) if you're using at least C2RC5 trunk revision 192;
<key>GenerateCStates</key>
<string>yes</string>
22. (added 20100830) 10.6.4 through current will severely decrease NVIDIA GPU performance by causing it's three clocks to always run at level 0 low power mode.
Edit the AppleGraphicsPowerManagement.kext/Contents/Info.plist's MacPro4,1 section and change Vendor10deDevice05e2 to Vendor10deDevice05e3.
The 05e3 part is for a GTX 285, see nvclock0.8b5_7-darwin/src/backend/info.c (link below) for others.
This is to allow the GPU to have power management; level 2 high power when stressed, and down clocking to level 0 when not stressed (~10C lower).
The GPU clock will be at level 0 after sleep and wake, but the shader and memory clocks will temporarily be stuck at level 2.
However, if load is applied and then reduced, shader and memory will return to level 0.
The following solutions cause the three clocks to always run at level 2;
Use MacPro3,1 in smbios.plist.
or
Delete AppleGraphicsPowerManagement.kext.
or
Use the AppleGraphicsPowerManagement.kext from 10.6.3.
Temperatures and clock speeds can be seen with nvclock, and for lower temperatures it's recommended to set fanspeed mode to auto with `nvclock -F auto -f', which needs to be set again after sleep and wake;
http://www.projectos...?showtopic=1246
Thanks to jhrfc for automating this so it will start in auto at boot, and switch back to auto after sleep (post 119);
http://www.insanelym...c=228757&st=118
23. (added 20111106) iCloud notes (post 1306);
http://www.insanelym...=196771&st=1305
24. (moved from Configuration section on 20120810) Fix for CMOS reset during wake with 10.7.0 through current, thanks to rayap;
10.7.x (post 340): http://www.insanelym...c=253992&st=339
10.8.x (post 1): http://www.insanelym...pic=276066&st=0
Over clocking;
These are my settings for a 2.66 GHz Xeon W3520 with 6x2GB 1333 MHz memory.
Up to 3.7 GHz all voltages can be left at auto.
`About This Mac' only shows up to 4.3 GHz.
Edit /System/Library/CoreServices/loginwindow.app/Contents/Resources/English.lproj/AboutThisMac.strings if you want it to show over that;
//"ABOUT_BOX_SINGLE_PROCESSOR_FIELD_FORMAT" = "%@";
"ABOUT_BOX_SINGLE_PROCESSOR_FIELD_FORMAT" = "4.4 GHz Quad-Core Intel Xeon";
At 4 GHz maximum Geekbench score is 14124 with memory x8 at maximum stable speed of 1600 MHz:
Advanced CPU Features: CPU Clock Ratio ................................ [20x] Intel(R) Turbo Boost Tech .................. [Enabled] CPU Cores Enabled ............................ [All] CPU Multi Threading .......................... [Enabled] CPU Enhanced Halt (C1E) ................... [Enabled] C3/C6/C7 State Support .................... [Disabled] enabled CPU Thermal Monitor ......................... [Enabled] CPU EIST Function ............................ [Enabled] Bi-Directional PROCHOT ..................... [Enabled] Virtualization Technology ................... [Enabled] Uncore & QPI Features: QPI Link Speed .............................. [x36] (7.2 GHz) Uncore Frequency .......................... (must be 2x System Memory Multiplier) x17 (3200 MHz) Isonchronous Frequency ..................[Enabled] Standard Clock Control: Base Clock (BCLK) Control ................ [Enabled] enabled BCLK Frequency (MHz) ..................... [133] 200 PCI Express Frequency (MHz) ........... [100] C.I.A.2 [Disabled] Advanced Clock Control: CPU Clock Drive ................... [800mV] PCI Express Clock Drive ................... [900mV] CPU Clock Skew ............................. [0ps] IOH Clock Skew ............................. [0ps] Advanced DRAM Features: Performance Enhance ...................... [Turbo] standard Extreme Memory Profile (X.M.P) ......... [Disabled] System Memory Multiplier (SPD) ........ [Auto] x8 (1600 MHz) DRAM Timing Selectable (SPD) .......... [Auto] manual Channel A + B + C Channel A Timing Settings: ##Channel A Standard Timing Control## CAS Latency Time ...................... [Auto] 11 tRCD ....................................... [Auto] 15 tRP ......................................... [Auto] 15 tRAS ....................................... [Auto] 31 Command Rate (CMD) ......................... [Auto] 2 ##Channel A Advanced Timing Control## tRC ........................................ (Should be = tRAS + tRP or above for stability) tRRD ....................................... tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4) tWR ........................................ tWTP ....................................... (tWTP Must = tWR + tWL + 4) tWL ........................................ (tWL Must be CAS Latency -1) tRFC ....................................... tRTP ....................................... tFAW ...................................... Command Rate (CMD) ................ ##Channel A Misc Timing Control## Round Trip Latency ................... Advanced Voltage Control: CPU Load Line Calibration ................. [Disabled] enabled CPU Vcore 1.2375v ................. [Auto] normal Dynamic Vcore (DVID) ............ [Auto] +0.24375 QPI/VTT Voltage 1.2v ............ [Auto] 1.58 CPU PLL 1.800v ....................... [Auto] 1.88 MCH/ICH PCIE 1.500v ........................... [Auto] QPI PLL 1.100v ....................... [Auto] 1.4 IOH Core 1.100v ..................... [Auto] 1.3 ICH I/O 1.500v ....................... [Auto] ICH Core 1.1v ........................ [Auto] DRAM DRAM Voltage 1.500v .............. [Auto] 1.54 DRAM Termination 0.750v [Auto] .77 Ch-A Data VRef. 0.750v [Auto] .77 Ch-B Data VRef. 0.750v [Auto] .77 Ch-C Data VRef. 0.750v [Auto] .77 Ch-A Address VRef. 0.750v [Auto] .77 Ch-B Address VRef. 0.750v [Auto] .77 Ch-C Address VRef. 0.750v [Auto] .77At 4.1 GHz disabled turbo because of KPs, with memory x6 at 1230 MHz;
Advanced CPU Features: CPU Clock Ratio ................................ [20x] Intel(R) Turbo Boost Tech .................. [Enabled] disabled CPU Cores Enabled ............................ [All] CPU Multi Threading .......................... [Enabled] CPU Enhanced Halt (C1E) ................... [Enabled] C3/C6/C7 State Support .................... [Disabled] enabled CPU Thermal Monitor ......................... [Enabled] CPU EIST Function ............................ [Enabled] Bi-Directional PROCHOT ..................... [Enabled] Virtualization Technology ................... [Enabled] Uncore & QPI Features: QPI Link Speed .............................. [x36] (7.38 GHz) Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2665 MHz) Isonchronous Frequency ..................[Enabled] Standard Clock Control: Base Clock (BCLK) Control ................ [Enabled] enabled BCLK Frequency (MHz) ..................... [133] 205 PCI Express Frequency (MHz) ........... [100] C.I.A.2 [Disabled] Advanced Clock Control: CPU Clock Drive ................... [800mV] PCI Express Clock Drive ................... [900mV] CPU Clock Skew ............................. [0ps] IOH Clock Skew ............................. [0ps] Advanced DRAM Features: Performance Enhance ...................... [Turbo] standard Extreme Memory Profile (X.M.P) ......... [Disabled] System Memory Multiplier (SPD) ........ [Auto] x6 (1230 MHz) DRAM Timing Selectable (SPD) .......... [Auto] Channel A + B + C Channel A Timing Settings: ##Channel A Standard Timing Control## CAS Latency Time ...................... [Auto] tRCD ....................................... [Auto] tRP ......................................... [Auto] tRAS ....................................... [Auto] Command Rate (CMD) ......................... [Auto] ##Channel A Advanced Timing Control## tRC ........................................ (Should be = tRAS + tRP or above for stability) tRRD ....................................... tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4) tWR ........................................ tWTP ....................................... (tWTP Must = tWR + tWL + 4) tWL ........................................ (tWL Must be CAS Latency -1) tRFC ....................................... tRTP ....................................... tFAW ...................................... Command Rate (CMD) ................ ##Channel A Misc Timing Control## Round Trip Latency ................... Advanced Voltage Control: CPU Load Line Calibration ................. [Disabled] enabled CPU Vcore 1.2375v ................. [Auto] normal Dynamic Vcore (DVID) ............ [Auto] +0.2125 QPI/VTT Voltage 1.2v ............ [Auto] 1.52 CPU PLL 1.800v ....................... [Auto] 1.88 MCH/ICH PCIE 1.500v ........................... [Auto] QPI PLL 1.100v ....................... [Auto] 1.3 IOH Core 1.100v ..................... [Auto] 1.3 ICH I/O 1.500v ....................... [Auto] ICH Core 1.1v ........................ [Auto] DRAM DRAM Voltage 1.500v .............. [Auto] 1.54 DRAM Termination 0.750v [Auto] Ch-A Data VRef. 0.750v [Auto] Ch-B Data VRef. 0.750v [Auto] Ch-C Data VRef. 0.750v [Auto] Ch-A Address VRef. 0.750v [Auto] Ch-B Address VRef. 0.750v [Auto] Ch-C Address VRef. 0.750v [Auto]At 4.2 GHz with memory x6 at 1260 MHz:
Advanced CPU Features: CPU Clock Ratio ................................ [20x] Intel(R) Turbo Boost Tech .................. [Enabled] disabled CPU Cores Enabled ............................ [All] CPU Multi Threading .......................... [Enabled] CPU Enhanced Halt (C1E) ................... [Enabled] C3/C6/C7 State Support .................... [Disabled] enabled CPU Thermal Monitor ......................... [Enabled] CPU EIST Function ............................ [Enabled] Bi-Directional PROCHOT ..................... [Enabled] Virtualization Technology ................... [Enabled] Uncore & QPI Features: QPI Link Speed .............................. [x36] (7.56 GHz) Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2730 MHz) Isonchronous Frequency ..................[Enabled] Standard Clock Control: Base Clock (BCLK) Control ................ [Enabled] enabled BCLK Frequency (MHz) ..................... [133] 210 PCI Express Frequency (MHz) ........... [100] C.I.A.2 [Disabled] Advanced Clock Control: CPU Clock Drive ................... [800mV] PCI Express Clock Drive ................... [900mV] CPU Clock Skew ............................. [0ps] IOH Clock Skew ............................. [0ps] Advanced DRAM Features: Performance Enhance ...................... [Turbo] standard Extreme Memory Profile (X.M.P) ......... [Disabled] System Memory Multiplier (SPD) ........ [Auto] x6 (1260 MHz) DRAM Timing Selectable (SPD) .......... [Auto] Channel A + B + C Channel A Timing Settings: ##Channel A Standard Timing Control## CAS Latency Time ...................... [Auto] tRCD ....................................... [Auto] tRP ......................................... [Auto] tRAS ....................................... [Auto] Command Rate (CMD) ......................... [Auto] ##Channel A Advanced Timing Control## tRC ........................................ (Should be = tRAS + tRP or above for stability) tRRD ....................................... tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4) tWR ........................................ tWTP ....................................... (tWTP Must = tWR + tWL + 4) tWL ........................................ (tWL Must be CAS Latency -1) tRFC ....................................... tRTP ....................................... tFAW ...................................... Command Rate (CMD) ................ ##Channel A Misc Timing Control## Round Trip Latency ................... Advanced Voltage Control: CPU Load Line Calibration ................. [Disabled] enabled CPU Vcore 1.2375v ................. [Auto] normal Dynamic Vcore (DVID) ............ [Auto] +0.225 QPI/VTT Voltage 1.2v ............ [Auto] 1.52 CPU PLL 1.800v ....................... [Auto] 1.88 MCH/ICH PCIE 1.500v ........................... [Auto] QPI PLL 1.100v ....................... [Auto] 1.3 IOH Core 1.100v ..................... [Auto] 1.3 ICH I/O 1.500v ....................... [Auto] ICH Core 1.1v ........................ [Auto] DRAM DRAM Voltage 1.500v .............. [Auto] 1.54 DRAM Termination 0.750v [Auto] Ch-A Data VRef. 0.750v [Auto] Ch-B Data VRef. 0.750v [Auto] Ch-C Data VRef. 0.750v [Auto] Ch-A Address VRef. 0.750v [Auto] Ch-B Address VRef. 0.750v [Auto] Ch-C Address VRef. 0.750v [Auto]At 4.3 GHz disabled DVID because resume from S3 sleep doesn't work above +0.225, and maximum Geekbench score is 14104 with memory x6 at 1290 MHz:
Advanced CPU Features: CPU Clock Ratio ................................ [20x] Intel(R) Turbo Boost Tech .................. [Enabled] disabled CPU Cores Enabled ............................ [All] CPU Multi Threading .......................... [Enabled] CPU Enhanced Halt (C1E) ................... [Enabled] C3/C6/C7 State Support .................... [Disabled] enabled CPU Thermal Monitor ......................... [Enabled] CPU EIST Function ............................ [Enabled] Bi-Directional PROCHOT ..................... [Enabled] Virtualization Technology ................... [Enabled] Uncore & QPI Features: QPI Link Speed .............................. [x36] (7.74 GHz) Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2795 MHz) Isonchronous Frequency ..................[Enabled] Standard Clock Control: Base Clock (BCLK) Control ................ [Enabled] enabled BCLK Frequency (MHz) ..................... [133] 215 PCI Express Frequency (MHz) ........... [100] C.I.A.2 [Disabled] Advanced Clock Control: CPU Clock Drive ................... [800mV] PCI Express Clock Drive ................... [900mV] CPU Clock Skew ............................. [0ps] IOH Clock Skew ............................. [0ps] Advanced DRAM Features: Performance Enhance ...................... [Turbo] standard Extreme Memory Profile (X.M.P) ......... [Disabled] System Memory Multiplier (SPD) ........ [Auto] x6 (1290 MHz) DRAM Timing Selectable (SPD) .......... [Auto] Channel A + B + C Channel A Timing Settings: ##Channel A Standard Timing Control## CAS Latency Time ...................... [Auto] tRCD ....................................... [Auto] tRP ......................................... [Auto] tRAS ....................................... [Auto] Command Rate (CMD) ......................... [Auto] ##Channel A Advanced Timing Control## tRC ........................................ (Should be = tRAS + tRP or above for stability) tRRD ....................................... tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4) tWR ........................................ tWTP ....................................... (tWTP Must = tWR + tWL + 4) tWL ........................................ (tWL Must be CAS Latency -1) tRFC ....................................... tRTP ....................................... tFAW ...................................... Command Rate (CMD) ................ ##Channel A Misc Timing Control## Round Trip Latency ................... Advanced Voltage Control: CPU Load Line Calibration ................. [Disabled] enabled CPU Vcore 1.2375v ................. [Auto] 1.46875 Dynamic Vcore (DVID) ............ [Auto] +0.00000 QPI/VTT Voltage 1.2v ............ [Auto] 1.56 CPU PLL 1.800v ....................... [Auto] 1.88 MCH/ICH PCIE 1.500v ........................... [Auto] QPI PLL 1.100v ....................... [Auto] 1.38 IOH Core 1.100v ..................... [Auto] 1.3 ICH I/O 1.500v ....................... [Auto] ICH Core 1.1v ........................ [Auto] DRAM DRAM Voltage 1.500v .............. [Auto] 1.54 DRAM Termination 0.750v [Auto] Ch-A Data VRef. 0.750v [Auto] Ch-B Data VRef. 0.750v [Auto] Ch-C Data VRef. 0.750v [Auto] Ch-A Address VRef. 0.750v [Auto] Ch-B Address VRef. 0.750v [Auto] Ch-C Address VRef. 0.750v [Auto]At 4.4 GHz maximum Geekbench score is 14309 with memory x6 at 1320 MHz:
Advanced CPU Features: CPU Clock Ratio ................................ [20x] Intel(R) Turbo Boost Tech .................. [Enabled] disabled CPU Cores Enabled ............................ [All] CPU Multi Threading .......................... [Enabled] CPU Enhanced Halt (C1E) ................... [Enabled] C3/C6/C7 State Support .................... [Disabled] enabled CPU Thermal Monitor ......................... [Enabled] CPU EIST Function ............................ [Enabled] Bi-Directional PROCHOT ..................... [Enabled] Virtualization Technology ................... [Enabled] Uncore & QPI Features: QPI Link Speed .............................. [x36] (7.92 GHz) Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2860 MHz) Isonchronous Frequency ..................[Enabled] Standard Clock Control: Base Clock (BCLK) Control ................ [Enabled] enabled BCLK Frequency (MHz) ..................... [133] 220 PCI Express Frequency (MHz) ........... [100] C.I.A.2 [Disabled] Advanced Clock Control: CPU Clock Drive ................... [800mV] PCI Express Clock Drive ................... [900mV] CPU Clock Skew ............................. [0ps] IOH Clock Skew ............................. [0ps] Advanced DRAM Features: Performance Enhance ...................... [Turbo] standard Extreme Memory Profile (X.M.P) ......... [Disabled] System Memory Multiplier (SPD) ........ [Auto] x6 (1320 MHz) DRAM Timing Selectable (SPD) .......... [Auto] Channel A + B + C Channel A Timing Settings: ##Channel A Standard Timing Control## CAS Latency Time ...................... [Auto] tRCD ....................................... [Auto] tRP ......................................... [Auto] tRAS ....................................... [Auto] Command Rate (CMD) ......................... [Auto] ##Channel A Advanced Timing Control## tRC ........................................ (Should be = tRAS + tRP or above for stability) tRRD ....................................... tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4) tWR ........................................ tWTP ....................................... (tWTP Must = tWR + tWL + 4) tWL ........................................ (tWL Must be CAS Latency -1) tRFC ....................................... tRTP ....................................... tFAW ...................................... Command Rate (CMD) ................ ##Channel A Misc Timing Control## Round Trip Latency ................... Advanced Voltage Control: CPU Load Line Calibration ................. [Disabled] enabled CPU Vcore 1.2375v ................. [Auto] 1.58125 Dynamic Vcore (DVID) ............ [Auto] +0.00000 QPI/VTT Voltage 1.2v ............ [Auto] 1.58 CPU PLL 1.800v ....................... [Auto] 1.88 MCH/ICH PCIE 1.500v ........................... [Auto] QPI PLL 1.100v ....................... [Auto] 1.4 IOH Core 1.100v ..................... [Auto] 1.3 ICH I/O 1.500v ....................... [Auto] ICH Core 1.1v ........................ [Auto] DRAM DRAM Voltage 1.500v .............. [Auto] 1.54 DRAM Termination 0.750v [Auto] Ch-A Data VRef. 0.750v [Auto] Ch-B Data VRef. 0.750v [Auto] Ch-C Data VRef. 0.750v [Auto] Ch-A Address VRef. 0.750v [Auto] Ch-B Address VRef. 0.750v [Auto] Ch-C Address VRef. 0.750v [Auto]
This guide's configuration has been tested on GA-EX58-UD5;
BIOS F9e (added CPU8-F) and F9h with 10.6.0 through 10.6.2 in 32 bit mode using Chameleon-2.0-RC3-r658 and boot_v10.5
BIOS F9h, F9m (added DVID), F9p, F9 and F10 with 10.6.2 in 32 and 64 bit mode using Chameleon-2.0-RC4-r684
BIOS F10 through F12 with 10.6.2 in 64 bit mode using Chameleon-2.0-RC4-r684
BIOS F12 with 10.6.3 and 10.6.4 in 64 bit mode using Chameleon-2.0-RC4-r684
BIOS F12 with 10.6.4 in 64 bit mode using Booter_AsereBLN_v1.1.8
BIOS F12 with 10.6.4 in 64 bit mode using Chameleon-Mozodojo-262
BIOS F12 with 10.6.4 in 64 bit mode using C2RC5 r334 and r352
BIOS F12 with 10.7.0, and F13U with 10.7.1, in 64 bit mode using C2RC5 r1331
BIOS F13U with 10.7.2 through 10.7.4 in 64 bit mode using C2.1 r1650
BIOS F13U with 10.8.x (kernel is now 64 bit only) using C2.1 r2030
There's a Gigabyte bug that can cause a network port to cease functioning.
Shut the machine down, turn off the power supply, press and hold the CMOS button until the light goes out.
Start the machine, press the tab key at the logo screen, then the delete key at the post screen, then in the main menu press the F12 key to select your saved BIOS settings.
Here's how to tell if a kext is both 32 bit (i386) and 64 bit (x86_64);
[mac05:~] me% file RealtekR1000SL/Contents/MacOS/RealtekR1000SL
RealtekR1000SL.kext/Contents/MacOS/RealtekR1000SL: Mach-O universal binary with 2 architectures
RealtekR1000SL.kext/Contents/MacOS/RealtekR1000SL (for architecture x86_64): Mach-O 64-bit kext bundle x86_64
RealtekR1000SL.kext/Contents/MacOS/RealtekR1000SL (for architecture i386): Mach-O object i386
[mac05:~] me%
Configuration with 10.8.x;
Placed FakeSMC.kext in /System/Library/Extensions/.
Placed modified RealtekR1000SL.kext in /System/Library/Extensions/IONetworkingFamily.kext/Contents/PlugIns/ (item 19B).
Placed LegacyHDA.kext in /System/Library/Extensions/ (item 14D from post 511, HDEF layout-id 12 in DSDT, black jack audio out).
Patched /System/Library/Extensions/AppleRTC.kext (item 24).
Modified AppleGraphicsPowerManagement.kext/Contents/Info.plist (item 22).
To disable the automatic wake-for-network-access every two hours, I changed in /System/Library/LaunchDaemons/com.apple.mDNSResponder.plist from this;
<key>ProgramArguments</key> <array> <string>/usr/sbin/mDNSResponder</string> <string>-launchd</string> </array>...to this;
<key>ProgramArguments</key> <array> <string>/usr/sbin/mDNSResponder</string> <string>-launchd</string> <string>-DisableSleepProxyClient</string> </array>...then caused mDNSResponder to reread the file;
# killall -HUP mDNSResponder
Using C2.1 r2030 and DSDT_GA_EX58_UD5_F9m_v5.
Contents of my smbios.plist, SMcputype is for the CPU to appear as Quad-Core Intel Xeon in About This Mac instead of Intel Core i7, and fake value shown for SMserial (item 23);
<!DOCTYPE plist PUBLIC "-//Apple Computer//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd"> <plist version="1.0"> <dict> <key>SMcputype</key> <string>1281</string> <key>SMserial</key> <string>A01234BC5DE</string> <key>SMboardproduct</key> <string>Mac-F221BEC8</string> </dict> </plist>Contents of my org.chameleon.Boot.plist, extensions like FakeSMC.kext moved from /Extra to /System/Library/Extensions/ and UseKernelCache added as of 10.7.0, and `Start up automatically after a power failure' checked in Energy Saver and darkwake=0 added as of 10.7.0 for reliable wakes;
<?xml version="1.0" encoding="UTF-8"?> <!DOCTYPE plist PUBLIC "-//Apple Computer//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd"> <plist version="1.0"> <dict> <key>Kernel</key> <string>mach_kernel</string> <key>Kernel Flags</key> <string>darkwake=0 -v</string> <key>Quiet Boot</key> <string>no</string> <key>Timeout</key> <string>3</string> <key>Wait</key> <string>no</string> <key>GUI</key> <string>no</string> <key>GenerateCStates</key> <string>yes</string> <key>GraphicsEnabler</key> <string>yes</string> <key>UseKernelCache</key> <string>yes</string> </dict> </plist>Links;
digital_dreamer's Retail Snow Leopard Install Guide: http://www.insanelym...howtopic=185097
Gigabyte's corei7_x58_bios_guide.pdf: http://www.gigabyte-..._bios_guide.pdf
Chrysaor's MSR Tools (32 bit only, post 89): http://www.insanelym...ic=181631&st=88
THe KiNG's MP41SpeedStepFix.kext (for 10.6.0 and 10.6.1): http://www.projectos...p?showtopic=532
demong1's MacPro4_1.plist (see warning at bottom): located in the same forum site and topic as MP41SpeedStepFix.kext
David F. Elliott's NullCPUPowerManagement.kext: http://tgwbd.org/dar...extensions.html
David F. Elliott's ElliottForceLegacyRTC.kext: http://stellarola.tu...repare-yourself
EvoSX86 Team's DSDTSE: http://www.osx86.es/?p=610
fassl's getDSDT.sh: http://www.insanelym...howtopic=133683
ab___73's getSSDT5.sh: http://www.insanelym...howtopic=145792
cVad's 32 bit SL compiled iasl: http://www.insanelym...howtopic=189272
THe KiNG's OrangeIconFix.kext: http://www.projectos...p?showtopic=455
netkas's fakesmc.kext: google for the link
KWS's PenntNeu-script: http://www.insanelym...howtopic=182535
VoodooLabs's Chameleon-2.0-RC4-r684: http://chameleon.osx...ge-disk-support
netkas's boot_v10.5: http://netkas.org/?p=271
Asere's Booter_AsereBLN_v1.1.9: google for the link
Chameleon-Mozodojo bootloader:
http://www.insanelym...howtopic=225766
http://www.projectos...?showtopic=1337
http://forge.voodoop...anches/mozodojo
C2RC5 bootloader:
http://forge.voodoop...tree/HEAD/trunk
OSX86 Tools Utility (32 bit only): http://code.google.com/p/osx86tools/
Gigabyte BIOS beta: http://forums.tweakt...test-bios-28441
Gigabyte OC thread: http://www.xtremesys...ad.php?t=209013
Marcel Bresink's Temperature Monitor: http://www.bresink.c...ureMonitor.html
mprime: http://mersenne.org/freesoft/
Geekbench: http://www.primatelabs.ca/geekbench/
Warning: Using demong1's modified MacPro4_1.plist, then applying an Apple Software Update like Bonjour Update 2010-001 can break things so that you have no mouse or keyboard control at the login GUI.
I traced the problem to the use of tabs instead of spaces, this can be seen with running `cat -vet MacPro4_1.plist' in Terminal.
In kernel.log, the `Kext com.apple.driver.ACPI_SMC_PlatformPlugin failed to load' error was seen with Root set for the OSBundleRequired in the Info.plist for ACPI_SMC_PlatformPlugin.kext and IOPlatformPluginFamily.kext, and `virtual bool IOHIDEventSystemUserClient::initWithTask(task*, void*, UInt32): Client task not privileged to open IOHIDSystem for mapping memory' was seen with Safe-Boot (default) set for OSBundleRequired.
10.6.0 through 10.6.3;
Use my instructions at the top of the post to get a working modified MacPro4_1.plist.
10.6.3 with Mac Pro Audio Update 1.1, and 10.6.4 through current;
Apple has enabled speed step in an updated MacPro4_1.plist.
Warning: 10.6.4 through current will severely decrease NVIDIA GPU performance, see item 22 for a fix.
Request;
I neglected to backup my original Gigabyte GV-N285UD-1GH/F1 (nvclock: 62.00.50.00.01, ioreg: pci1458,34c9) BIOS before I flashed with one from EVGA for some tests.
If anyone with this card has some time, would you dump your BIOS with nvflash so that I can restore to my original BIOS?
Thanks in advance.
Windows;
http://www.techpower...%20Windows.html
DOS;
http://www.techpower...sh_5.95.01.html
Attachments (obsolete, see note in item 5);
DSDT.aml and dsdt.dsl for i7 920 and Xeon W3520, derived from GA-EX58-UD5 and BIOS F9m through F12, with fixes (doesn't include 1B, 19C or 20B), and 14B-E HDEF layout-id 12: DSDT_GA_EX58_UD5_F9m_S3_920_W3520_v2.zip
DSDT.aml and dsdt.dsl for i7 950 and Xeon W3550, derived from GA-EX58-UD5 and BIOS F9m through F12, with fixes (doesn't include 1B, 19C or 20B), and 14B-E HDEF layout-id 12: DSDT_GA_EX58_UD5_F9m_S3_950_W3550_v2.zip
DSDT.aml and dsdt.dsl for i7 975 and Xeon W3580, derived from GA-EX58-UD5 and BIOS F9m through F12, with fixes (doesn't include 1B, 19C or 20B), and 14B-E HDEF layout-id 12: DSDT_GA_EX58_UD5_F9m_S3_975_W3580_v2.zip
DSDT.aml and dsdt.dsl for i7 930 and Xeon W3530, derived from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep, fixes (doesn't include 1B, 19C or 20B), and 14B-E HDEF layout-id 12: DSDT_GA_EX58_UD5_F9m_S3_930_W3530_v2.zip
DSDT.aml and dsdt.dsl for any CPU using at least C2RC5 trunk revision 192, derived from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep, fixes (doesn't include 1B, 19C or 20B), and 14D HDEF layout-id 117: DSDT_GA_EX58_UD5_F9m_S3_Chameleon-Mozodojo_v4.zip
Attachments (current);
Unmodified dsdt.dsl from GA-EX58-UD5 and BIOS F9m through F13U, with S3 sleep:
dsdt_ga_ex58_ud5_f9m_s3.dsl.zip
DSDT.aml and dsdt.dsl for any CPU using at least C2RC5 trunk revision 192, derived from GA-EX58-UD5 and BIOS F9m through F13U, with S3 sleep, fixes (doesn't include 1B, 19C or 20B) and 14B-E HDEF layout-id 12: DSDT_GA_EX58_UD5_F9m_v5.zip
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Attached Files
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DSDT_GA_EX58_UD5_F9m_S3_920_W3520_v2.zip 20.23K
1782 downloads
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DSDT_GA_EX58_UD5_F9m_S3_950_W3550_v2.zip 20.32K
294 downloads
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DSDT_GA_EX58_UD5_F9m_S3_975_W3580_v2.zip 20.39K
163 downloads
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dsdt_ga_ex58_ud5_f9m_s3.dsl.zip 11.86K
277 downloads
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DSDT_GA_EX58_UD5_F9m_S3_930_W3530_v2.zip 21.1K
391 downloads
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DSDT_GA_EX58_UD5_F9m_S3_Chameleon_Mozodojo_v4.zip 19.66K
326 downloads
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DSDT_GA_EX58_UD5_F9m_S3_v5.zip 19.49K
217 downloads
. I have hope, like Obama.
