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Patch DSDT for JMB362 in AHCI mode

stradivari1723

By stradivari1723,
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LatinMcG
LatinMcG
Posted
Posted

im sure someone has this dsdt working WOL..

i havent had that issue besides in a older inspiron 530 intel WOL .. wake would kill LAN = reboot. never fixed that

 

the osfl calls do change things barely noticable. i notice cooler cpu with darwin as it loads the power management instead of generic.

 

but ultimately it might be dsdt or driver. or even bios.. i run gigabyte not asus.

but soon im getting a bad bios flash mobo from a friend for 20$ im going to recover bios on it and test osx in it.

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stradivari1723
stradivari1723
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  • Author
Posted

I have run across more than one account of how people with Realtek NICs did not have WOL working until they switched from Realtek drivers to Lnx2mac's beta driver. So it could very well be a driver issue.

Edit: Couple more things... changing OSVR to Darwin does indeed seem to have provided lower CPU temperatures, however I have done no scientific comparisons, but it also seems to me that perhaps my Geekbench scores are higher than previously!? Finally, I may boot into Win 7 and see if WOL is working in Windows. If it is, that would narrow things down, right? If it's not working in Windows, then that would mean it is a BIOS issue?

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LatinMcG
LatinMcG
Posted
Posted

yes if in cant WOL id say bios might be at fault (most likely its intel driver). read bios fixes for that board. one does mention WOL.

 

i edited the osvr post with Darwin on spots for freeBSD

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stradivari1723
stradivari1723
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WOL works fine in Win 7. :-\

Further thought... could it be because we have to use SleepEnabler.kext and "pmVersion=23" boot argument in order to have sleep working? Would it work if we had vanilla sleep? Or does the sleepenabler kext need to be edited to keep power supplied to the NIC when initiating sleep? Or is that not even relevant??

I'm about to give up... :-(

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Camilo_ML
Camilo_ML
Posted
Posted 

			Device (RP03)
		{
			Name (_ADR, 0x001C0002)
			OperationRegion (P3CS, PCI_Config, 0x40, 0xA0)
			Field (P3CS, AnyAcc, NoLock, WriteAsZeros)
			{
						Offset (0x20), 
						Offset (0x22), 
				PSP3,   1, 
						Offset (0x9C), 
					,   30, 
				HPS3,   1, 
				PMS3,   1
			}

			Device (ETH0)
			{
				Name (_ADR, 0x00)
				Name (_PRW, Package (0x02)
				{
					0x09, 
					0x03
				})
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"location", 
							Buffer (0x02)
							{
								"1"
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
			}

			Method (_PRT, 0, NotSerialized)
			{
				If (\GPIC)
				{
					Return (Package (0x04)
					{
						Package (0x04)
						{
							0xFFFF, 
							0x00, 
							0x00, 
							0x12
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x01, 
							0x00, 
							0x13
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x02, 
							0x00, 
							0x10
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x03, 
							0x00, 
							0x11
						}
					})
				}
				Else
				{
					Return (Package (0x04)
					{
						Package (0x04)
						{
							0xFFFF, 
							0x00, 
							\_SB.PCI0.LPCB.LNKC, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x01, 
							\_SB.PCI0.LPCB.LNKD, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x02, 
							\_SB.PCI0.LPCB.LNKA, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x03, 
							\_SB.PCI0.LPCB.LNKB, 
							0x00
						}
					})
				}
			}
		}

 

This is from an original macpro4,1, maybe it helps

 

rgrds

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stradivari1723
stradivari1723
Posted
  • Author
Posted
i have no clue of what sleepenbler does. as i never use it.

 

I think it sets the power states correctly for sleep on Asus P8P67. Without the kext, choosing sleep results in display off, drives spun down, but fans still running.

 

			Device (RP03)
		{
			Name (_ADR, 0x001C0002)
			OperationRegion (P3CS, PCI_Config, 0x40, 0xA0)
			Field (P3CS, AnyAcc, NoLock, WriteAsZeros)
			{
						Offset (0x20), 
						Offset (0x22), 
				PSP3,   1, 
						Offset (0x9C), 
					,   30, 
				HPS3,   1, 
				PMS3,   1
			}

			Device (ETH0)
			{
				Name (_ADR, 0x00)
				Name (_PRW, Package (0x02)
				{
					0x09, 
					0x03
				})
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"location", 
							Buffer (0x02)
							{
								"1"
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
			}

			Method (_PRT, 0, NotSerialized)
			{
				If (\GPIC)
				{
					Return (Package (0x04)
					{
						Package (0x04)
						{
							0xFFFF, 
							0x00, 
							0x00, 
							0x12
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x01, 
							0x00, 
							0x13
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x02, 
							0x00, 
							0x10
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x03, 
							0x00, 
							0x11
						}
					})
				}
				Else
				{
					Return (Package (0x04)
					{
						Package (0x04)
						{
							0xFFFF, 
							0x00, 
							\_SB.PCI0.LPCB.LNKC, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x01, 
							\_SB.PCI0.LPCB.LNKD, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x02, 
							\_SB.PCI0.LPCB.LNKA, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x03, 
							\_SB.PCI0.LPCB.LNKB, 
							0x00
						}
					})
				}
			}
		}

 

This is from an original macpro4,1, maybe it helps

 

rgrds

 

Interesting. Mac Pro 4,1 has an Intel NIC, right? (dual port, Gigabit)

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stradivari1723
stradivari1723
Posted
  • Author
Posted

I tried replacing the GBE entry with the ETH0 entry below, but no go. :-( Thanks, though.

 

			Device (RP03)
		{
			Name (_ADR, 0x001C0002)
			OperationRegion (P3CS, PCI_Config, 0x40, 0xA0)
			Field (P3CS, AnyAcc, NoLock, WriteAsZeros)
			{
						Offset (0x20), 
						Offset (0x22), 
				PSP3,   1, 
						Offset (0x9C), 
					,   30, 
				HPS3,   1, 
				PMS3,   1
			}

			Device (ETH0)
			{
				Name (_ADR, 0x00)
				Name (_PRW, Package (0x02)
				{
					0x09, 
					0x03
				})
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"location", 
							Buffer (0x02)
							{
								"1"
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
			}

			Method (_PRT, 0, NotSerialized)
			{
				If (\GPIC)
				{
					Return (Package (0x04)
					{
						Package (0x04)
						{
							0xFFFF, 
							0x00, 
							0x00, 
							0x12
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x01, 
							0x00, 
							0x13
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x02, 
							0x00, 
							0x10
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x03, 
							0x00, 
							0x11
						}
					})
				}
				Else
				{
					Return (Package (0x04)
					{
						Package (0x04)
						{
							0xFFFF, 
							0x00, 
							\_SB.PCI0.LPCB.LNKC, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x01, 
							\_SB.PCI0.LPCB.LNKD, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x02, 
							\_SB.PCI0.LPCB.LNKA, 
							0x00
						}, 

						Package (0x04)
						{
							0xFFFF, 
							0x03, 
							\_SB.PCI0.LPCB.LNKB, 
							0x00
						}
					})
				}
			}
		}

 

This is from an original macpro4,1, maybe it helps

 

rgrds

 

 

I found this info on the Intel site, for the NIC that is onboard my MOBO. Does any of this info help??

 

7.4.1.1
b.	Flexible Filter Value Table MSBs – FFVT_H (filters 23) c.	Flexible Filter Value Table - FFVT_45 (filters 45) d.	Flexible Filter Value Table - FFVT_67 (filters 67) e.	Flexible TCO Filter Value/Mask Table LSBs – FTFT_L f.	Flexible TCO Filter Value/Mask Table MSBs – FTFT_H
4. Configure the 82579’s wake up registers per ACPI/APM wake up needs.
5. Clear the Slave Access Enable bit (bit 2) in the Receive Control register (page 800, register 0) to enable the flex filters.
6. Set the Host_WU_Active bit (bit 4) in the Port General Configuration register (page 769, register 17) to activate the 82579’s wake up functionality.
Once wake up is enabled, the 82579 stops responding to SMBus commands.
Host wake up:
1. When a WoL packet/event is detected, the 82579 sends an in-band message to the integrated LAN controller indicating Host wake up.
2. In case of host wake up, the integrated LAN controller wakes the host. 3. Host should issue a LCD reset to the 82579 before clearing the Host_WU_Active bit. 4. Host reads the Wake Up Status register (WUS); wake up status from the 82579).
When a wake up packet is identified, the wake up in-band message is sent and the host should clear the Host_WU_Active bit (bit 4) in the Port General Configuration register (page 769, register 17).
While in wake up active mode new wake up packets received will not overwrite the packet in the FIFO. The 82579 re-transmits the wake up in-band message after 50 ms if no change in the Host_WU_Active bits occurred.
Host Wake Up
The 82579 supports two types of wake up mechanisms: • Advanced Power Management (APM) wake up • ACPI Power Management wake up
Advanced Power Management Wake Up
Advanced Power Management Wakeup or APM Wakeup was previously known as Wake on LAN (WoL). The basic premise is to receive a broadcast or unicast packet with an explicit data pattern, and then to assert a signal to wake up the system or issue an in- band PM_PME message (if configured to).
At power up, if the 82579’s wake up functionality is enabled, the APM Enable bits from the NVM are written to the 82579 by the integrated LAN controller to the APM Enable (APME) bits of the Wakeup Control (WUC) register. These bits control the enabling of APM wake up.
When APM wake up is enabled, the 82579 checks all incoming packets for Magic Packets. See Section 7.4.1.3.1.4 for a definition of Magic Packets.
39
Device Functionality—Intel® 82579 Gigabit Ethernet
7.4.1.1.1
7.4.1.2
To enable APM wake up, programmers should write a 1b to bit 10 in register 26 on page 0 PHY address 01, and then the station address to registers 27, 28, 29 at page 0 PHY address 01. The order is mandatory since registers RAL0[31:0] and RAH0[15:0] are updated with a corresponding value from registers 27, 28, 29, if the APM WoL Enable bit is set in register 26. The Address Valid bit (bit 31 in RAH0) is automatically set with a write to register 29, if the APM WoL Enable bit is set in register 26. The APM Enable bit (bit 0 in the WUC) is automatically set with a write to register 29, if the APM WoL Enable bit is set in register 26.
Once the 82579 receives a matching magic packet, it: • Sets the Magic Packet Received bit in the WUS register. • Initiates the integrated LAN controller wake up event through an in-band message.
APM wake up is supported in all power states and only disabled if a subsequent NVM read results in the APM Wake Up bit being cleared or software explicitly writes a 0b to the APM Wake Up (APM) bit of the WUC register.

 

To enable APM wake up, programmers should write a 1b to bit 10 in register 26 on page 0 PHY address 01, and then the station address to registers 27, 28, 29 at page 0 PHY address 01

 

Can this be done in DSDT, or is this different than PCI registers? How would I do this?

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  • 1 year later...
Riley Freeman
Riley Freeman
Posted
Posted

I got it to finally work by replacing the ENTIRE JMB entry with this simplified bit that The King posted in that other thread:

 

				Device (JMB0)
			{
				Name (_ADR, Zero)
				OperationRegion (BAR0, PCI_Config, 0x40, 0x04)
				Field (BAR0, WordAcc, NoLock, Preserve)
				{
					M1,	 8,
					M2,	 8,
					M3,	 8
				}

				Method (_DSM, 4, NotSerialized)
				{
					Store (0xB3, M1)
					Store (0xA1, M2)
					Store (0xC2, M3)
					Store (Package (0x02)
						{
							"name",
							Buffer (0x16)
							{
								"J-Micron JMB36x eSATA"
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
			}

 

I've used this code to get the JMB362 working on my P8Z68 board. However it lists two eSATA ports while I only have one port on my board (even though it's apparently a dual-port chipset).

 

Is it possible to disable the second port via a DSDT hack? This is what I have in IORegExp. Only PRT0 is needed.

 

Another issue here is I can't get the drive to wake from sleep. I've added the PINI method, but it's possible I'm calling it in the wrong place. I have _WAK and WAK entries and adding PINI() to either of these has no effect. I have to manually wake the drive by launching Disk Utility. I've attached my DSDT, hopefully someone can help.

DSDT.aml.zip

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