34 replies to this topic

[stradivari1723]

Hi, all.

First post. Huzzah.

Anyhoo... I've got an Asus P8P67 Pro. There's an issue with the onboard eSATA ports (Jmicron JMB362 powered), whereby the Asus BIOS/UEFI only allows "enabled" or "disabled" for that particular controller, and unfortunately "enabled" really means "legacy IDE". There is no BIOS option to start it in true AHCI mode.

I have been successful using the controller in Snow Leopard by getting Apple's AHCI driver to attach itself to the controller even though it is in legacy IDE mode, and then switching the controller to AHCI mode by brute force, by setting the PCI registers with setpci.

Once done, the eSATA ports work like a charm, including hot-swapping and all AHCI eSATA goodness.

What I'd like to do now is get this change done in DSDT, and I need some help if you've got the time! :-)

Here is the relevant code from my stock clean DSDT:

				Device (JMB0)
				{
					Name (_ADR, 0x00020000)
					OperationRegion (CF40, PCI_Config, 0x40, 0x04)
					Field (CF40, ByteAcc, NoLock, Preserve)
					{
						CHE0,   1, 
						MULT,   1, 
							,   1, 
						CAB0,   1, 
						CHE1,   1, 
								Offset (0x01), 
						AHEN,   1, 
							,   3, 
						PRT0,   1, 
						AHM0,   1, 
						PRT1,   1, 
						AHM1,   1, 
						CF42,   6, 
						SWAP,   1, 
						PATA,   1, 
							,   6, 
						WTEN,   1, 
								Offset (0x04)
					}

					Name (PIOT, Package (0x05)
					{
						0x0258, 
						0x0186, 
						0x014A, 
						0xB4, 
						0x78
					})
					Name (UDMA, Package (0x07)
					{
						0x78, 
						0x50, 
						0x3C, 
						0x28, 
						0x1E, 
						0x14, 
						0x0F
					})
					Name (MDMA, Package (0x03)
					{
						0x01E0, 
						0x96, 
						0x78
					})
					Name (IDEB, Buffer (0x14) {})
					CreateDWordField (IDEB, Zero, GTM0)
					CreateDWordField (IDEB, 0x04, GTM1)
					CreateDWordField (IDEB, 0x08, GTM2)
					CreateDWordField (IDEB, 0x0C, GTM3)
					CreateDWordField (IDEB, 0x10, GTM4)
					Name (PIO0, 0x04)
					Name (DMA0, 0x06)
					Name (MDA0, 0x02)
					Name (PIO1, 0x04)
					Name (DMA1, 0x06)
					Name (MDA1, 0x02)
					Name (PIO2, 0x04)
					Name (DMA2, 0x06)
					Name (MDA2, 0x02)
					Name (PIO3, 0x04)
					Name (DMA3, 0x06)
					Name (MDA3, 0x02)
					Name (FLGP, 0x1F)
					Name (FLGS, 0x1F)
					Device (IDE0)
					{
						Name (_ADR, Zero)
						Method (_GTM, 0, NotSerialized)
						{
							Store (DerefOf (Index (PIOT, PIO0)), Local0)
							Store (DerefOf (Index (PIOT, PIO1)), Local2)
							Store (0x1A, Local4)
							If (LAnd (FLGP, One))
							{
								If (LNot (MULT))
								{
									If (LAnd (CAB0, SWAP))
									{
										Store (0x02, DMA0)
									}
								}

								Store (DerefOf (Index (UDMA, DMA0)), Local1)
								Or (Local4, One, Local4)
							}
							Else
							{
								Store (DerefOf (Index (MDMA, MDA0)), Local1)
							}

							If (LAnd (FLGP, 0x04))
							{
								If (LAnd (CAB0, SWAP))
								{
									Store (0x02, DMA1)
								}

								Store (DerefOf (Index (UDMA, DMA1)), Local3)
								Or (Local4, 0x04, Local4)
							}
							Else
							{
								Store (DerefOf (Index (MDMA, MDA1)), Local3)
							}

							Store (Local0, GTM0)
							Store (Local1, GTM1)
							Store (Local2, GTM2)
							Store (Local3, GTM3)
							Store (Local4, GTM4)
							Return (IDEB)
						}

						Method (_STM, 3, NotSerialized)
						{
							Store (Arg0, IDEB)
							Store (GTM0, Local0)
							Store (GTM1, Local1)
							Store (GTM2, Local2)
							Store (GTM3, Local3)
							Store (GTM4, Local4)
							Store (Local4, FLGP)
							If (LAnd (LNotEqual (Local0, 0xFFFFFFFF), LNotEqual (Local0, Zero)))
							{
								Store (Match (PIOT, MEQ, Local0, MTR, Zero, Zero), PIO0)
							}

							If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), LNotEqual (Local1, Zero)))
							{
								If (LAnd (FLGP, One))
								{
									Store (Match (UDMA, MEQ, Local1, MTR, Zero, Zero), DMA0)
								}
								Else
								{
									Store (Match (MDMA, MEQ, Local1, MTR, Zero, Zero), MDA0)
								}
							}

							If (LAnd (LNotEqual (Local2, 0xFFFFFFFF), LNotEqual (Local2, Zero)))
							{
								Store (Match (PIOT, MEQ, Local2, MTR, Zero, Zero), PIO1)
							}

							If (LAnd (LNotEqual (Local3, 0xFFFFFFFF), LNotEqual (Local3, Zero)))
							{
								If (LAnd (FLGP, 0x04))
								{
									Store (Match (UDMA, MEQ, Local3, MTR, Zero, Zero), DMA1)
								}
								Else
								{
									Store (Match (MDMA, MEQ, Local3, MTR, Zero, Zero), MDA1)
								}
							}
						}

						Device (DRV0)
						{
							Name (_ADR, Zero)
							Method (_GTF, 0, NotSerialized)
							{
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
									}, Local0)
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
									}, Local1)
								CreateByteField (Local0, One, PIOM)
								CreateByteField (Local1, One, DMAM)
								Store (PIO0, PIOM)
								Or (PIOM, 0x08, PIOM)
								If (LAnd (FLGP, One))
								{
									Store (DMA0, DMAM)
									Or (DMAM, 0x40, DMAM)
								}
								Else
								{
									Store (MDA0, DMAM)
									Or (DMAM, 0x20, DMAM)
								}

								Concatenate (Local0, Local1, Local2)
								Return (Local2)
							}
						}

						Device (DRV1)
						{
							Name (_ADR, One)
							Method (_GTF, 0, NotSerialized)
							{
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF
									}, Local0)
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF
									}, Local1)
								CreateByteField (Local0, One, PIOM)
								CreateByteField (Local1, One, DMAM)
								Store (PIO1, PIOM)
								Or (PIOM, 0x08, PIOM)
								If (LAnd (FLGP, 0x04))
								{
									Store (DMA1, DMAM)
									Or (DMAM, 0x40, DMAM)
								}
								Else
								{
									Store (MDA1, DMAM)
									Or (DMAM, 0x20, DMAM)
								}

								Concatenate (Local0, Local1, Local2)
								Return (Local2)
							}
						}
					}

					Device (IDE1)
					{
						Name (_ADR, One)
						Method (_GTM, 0, NotSerialized)
						{
							Store (DerefOf (Index (PIOT, PIO2)), Local0)
							Store (DerefOf (Index (PIOT, PIO3)), Local2)
							Store (0x1A, Local4)
							If (LAnd (FLGS, One))
							{
								If (LNot (MULT))
								{
									If (LAnd (CAB0, LNot (SWAP)))
									{
										Store (0x02, DMA2)
									}
								}

								Store (DerefOf (Index (UDMA, DMA2)), Local1)
								Or (Local4, One, Local4)
							}
							Else
							{
								Store (DerefOf (Index (MDMA, MDA2)), Local1)
							}

							If (LAnd (FLGS, 0x04))
							{
								If (LAnd (CAB0, LNot (SWAP)))
								{
									Store (0x02, DMA3)
								}

								Store (DerefOf (Index (UDMA, DMA3)), Local3)
								Or (Local4, 0x04, Local4)
							}
							Else
							{
								Store (DerefOf (Index (MDMA, MDA3)), Local3)
							}

							Store (Local0, GTM0)
							Store (Local1, GTM1)
							Store (Local2, GTM2)
							Store (Local3, GTM3)
							Store (Local4, GTM4)
							Return (IDEB)
						}

						Method (_STM, 3, NotSerialized)
						{
							Store (Arg0, IDEB)
							Store (GTM0, Local0)
							Store (GTM1, Local1)
							Store (GTM2, Local2)
							Store (GTM3, Local3)
							Store (GTM4, Local4)
							Store (Local4, FLGS)
							If (LAnd (LNotEqual (Local0, 0xFFFFFFFF), LNotEqual (Local0, Zero)))
							{
								Store (Match (PIOT, MEQ, Local0, MTR, Zero, Zero), PIO2)
							}

							If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), LNotEqual (Local1, Zero)))
							{
								If (LAnd (FLGS, One))
								{
									Store (Match (UDMA, MEQ, Local1, MTR, Zero, Zero), DMA2)
								}
								Else
								{
									Store (Match (MDMA, MEQ, Local1, MTR, Zero, Zero), MDA2)
								}
							}

							If (LAnd (LNotEqual (Local2, 0xFFFFFFFF), LNotEqual (Local2, Zero)))
							{
								Store (Match (PIOT, MEQ, Local2, MTR, Zero, Zero), PIO3)
							}

							If (LAnd (LNotEqual (Local3, 0xFFFFFFFF), LNotEqual (Local3, Zero)))
							{
								If (LAnd (FLGS, 0x04))
								{
									Store (Match (UDMA, MEQ, Local3, MTR, Zero, Zero), DMA3)
								}
								Else
								{
									Store (Match (MDMA, MEQ, Local3, MTR, Zero, Zero), MDA3)
								}
							}
						}

						Device (DRV0)
						{
							Name (_ADR, Zero)
							Method (_GTF, 0, NotSerialized)
							{
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
									}, Local0)
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
									}, Local1)
								CreateByteField (Local0, One, PIOM)
								CreateByteField (Local1, One, DMAM)
								Store (PIO2, PIOM)
								Or (PIOM, 0x08, PIOM)
								If (LAnd (FLGS, One))
								{
									Store (DMA2, DMAM)
									Or (DMAM, 0x40, DMAM)
								}
								Else
								{
									Store (MDA2, DMAM)
									Or (DMAM, 0x20, DMAM)
								}

								Concatenate (Local0, Local1, Local2)
								Return (Local2)
							}
						}

						Device (DRV1)
						{
							Name (_ADR, One)
							Method (_GTF, 0, NotSerialized)
							{
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF
									}, Local0)
								Store (Buffer (0x07)
									{
										0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF
									}, Local1)
								CreateByteField (Local0, One, PIOM)
								CreateByteField (Local1, One, DMAM)
								Store (PIO3, PIOM)
								Or (PIOM, 0x08, PIOM)
								If (LAnd (FLGS, 0x04))
								{
									Store (DMA3, DMAM)
									Or (DMAM, 0x40, DMAM)
								}
								Else
								{
									Store (MDA3, DMAM)
									Or (DMAM, 0x20, DMAM)
								}

								Concatenate (Local0, Local1, Local2)
								Return (Local2)
							}
						}
					}
				}

There is another identical JMB1 entry, with a slightly different address at the header.

The setpci command once booted up is setpci -s 05:0.0 40.b=b3 41.b=a1 42.b=c2

What should I replace or append/insert into the DSDT code?

[LatinMcG]

try adding the register changes on dsdt with  PINI method (google it)
"Apple We Want Your Id!, Some "Max Factor" cosmetic stuff"

the king has a way to change registers on pci init.

[stradivari1723]

LatinMcGyver75, on May 21 2011, 02:21 AM, said:

try adding the register changes on dsdt with  PINI method (google it)
"Apple We Want Your Id!, Some "Max Factor" cosmetic stuff"

the king has a way to change registers on pci init.

I googled all sorts of keywords, "PINI DSDT", "pci init DSDT", etc. and couldn't find anything that looked helpful.

I did find this thread involving The King: http://www.insanelym...hp/t186558.html

I fiddled around with trying to incorporate this spot of code into the JMB entries:

			Device (\_SB.PCI0.PEX0.JMB0)
			{
				Name (_ADR, 0x00)
				OperationRegion (BAR0, PCI_Config, 0x40, 0x04)
				Field (BAR0, WordAcc, NoLock, Preserve)
				{
				Offset (0x00),
				M1, 8,
				Offset (0x01),
				M2, 8,
				Offset (0x02),
				M3, 8
				}

				Method (_DSM, 4, NotSerialized)
				{
				Store (0xb3, M1)
				Store (0xa1, M2)
				Store (0xc2, M3)
				Return (0x00)
				}

But to no avail. I'm simply lacking enough of a foundation in this kind of thing to know what exactly to change, what to modify and adapt for my entry.

Can anybody help me by showing me where to put this bit of code (I understand that it sets the registers to the same value as the setpci command arguments I first posted?) into my DSDT? I'm also not sure of the function of the name, operationregion, and field lines. Do they need to be changed to match what is already in the JMB0 entry in my DSDT? Or do they specify where to write the values. I really need some help! :-)

[stradivari1723]

Seriously?? No one?? :-(

[LatinMcG]

actualy.. yes that is the one u need to follow. but adapt to your device id and pex#

more reading.
www.projectosx.com/forum/index.php?showtopic=852&pid=4351&mode=threaded&start=

also function Disable Register is what u looking for. except u want to enable it on the jmb0

try adding

				Device (JMB0)
				{
					Name (_ADR, 0x00020000)
					 OperationRegion (BAR0, PCI_Config, 0x40, 0x04)
					Field (BAR0, WordAcc, NoLock, Preserve)
					{
							Offset (0x00),
						M1, 8,
							Offset (0x01),
						M2, 8,
							Offset (0x02),
						M3, 8
					}

					Method (_DSM, 4, NotSerialized)
					{
						Store (0xb3, M1)
						Store (0xa1, M2)
						Store (0xc2, M3)
						Store (Package (0x02)
							{
								"name", 
								Buffer (0x16)
								{
									"J-Micron JMB362 eSATA"
								}
							}, Local0)
						DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
						Return (Local0)
					}
					OperationRegion (CF40, PCI_Config, 0x40, 0x04)
					Field (CF40, ByteAcc, NoLock, Preserve)
					{
						CHE0,   1, 
						MULT,   1, 
							,   1, 
						CAB0,   1, 
						CHE1,   1, 
								Offset (0x01), 
						AHEN,   1, 
							,   3, 
						PRT0,   1, 
						AHM0,   1, 
						PRT1,   1, 
						AHM1,   1, 
						CF42,   6, 
						SWAP,   1, 
						PATA,   1, 
							,   6, 
						WTEN,   1, 
								Offset (0x04)
					}
  Method (_INI, 0, NotSerialized)
					{
					}
					Name (PIOT, Package (0x05)
					{
						0x0258, 
						0x0186, 
						0x014A, 
						0xB4, 
						0x78
					})
					Name (UDMA, Package (0x07)
					{
						0x78, 
						0x50, 
						0x3C, 
						0x28, 
						0x1E, 
						0x14, 
						0x0F
					})
					Name (MDMA, Package (0x03)
					{
						0x01E0, 
						0x96, 
						0x78
					})
STOP u went too far!
rest of your dsdt example continues..

[stradivari1723]

LatinMcGyver75, on May 22 2011, 04:01 PM, said:

actualy.. yes that is the one u need to follow. but adapt to your device id and pex#

more reading.
www.projectosx.com/forum/index.php?showtopic=852&pid=4351&mode=threaded&start=

also function Disable Register is what u looking for. except u want to enable it on the jmb0

try adding

				Device (JMB0)
				{
					Name (_ADR, 0x00020000)
					 OperationRegion (BAR0, PCI_Config, 0x40, 0x04)
					Field (BAR0, WordAcc, NoLock, Preserve)
					{
							Offset (0x00),
						M1, 8,
							Offset (0x01),
						M2, 8,
							Offset (0x02),
						M3, 8
					}

					Method (_DSM, 4, NotSerialized)
					{
						Store (0xb3, M1)
						Store (0xa1, M2)
						Store (0xc2, M3)
						Store (Package (0x02)
							{
								"name", 
								Buffer (0x16)
								{
									"J-Micron JMB362 eSATA"
								}
							}, Local0)
						DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
						Return (Local0)
					}
					OperationRegion (CF40, PCI_Config, 0x40, 0x04)
					Field (CF40, ByteAcc, NoLock, Preserve)
					{
						CHE0,   1, 
						MULT,   1, 
							,   1, 
						CAB0,   1, 
						CHE1,   1, 
								Offset (0x01), 
						AHEN,   1, 
							,   3, 
						PRT0,   1, 
						AHM0,   1, 
						PRT1,   1, 
						AHM1,   1, 
						CF42,   6, 
						SWAP,   1, 
						PATA,   1, 
							,   6, 
						WTEN,   1, 
								Offset (0x04)
					}
  Method (_INI, 0, NotSerialized)
					{
					}
					Name (PIOT, Package (0x05)
					{
						0x0258, 
						0x0186, 
						0x014A, 
						0xB4, 
						0x78
					})
					Name (UDMA, Package (0x07)
					{
						0x78, 
						0x50, 
						0x3C, 
						0x28, 
						0x1E, 
						0x14, 
						0x0F
					})
					Name (MDMA, Package (0x03)
					{
						0x01E0, 
						0x96, 
						0x78
					})
STOP u went too far!
rest of your dsdt example continues..

I tried that, but it did not work.

HOWEVER!

I got it to finally work by replacing the ENTIRE JMB entry with this simplified bit that The King posted in that other thread:

				Device (JMB0)
				{
					Name (_ADR, Zero)
					OperationRegion (BAR0, PCI_Config, 0x40, 0x04)
					Field (BAR0, WordAcc, NoLock, Preserve)
					{
						M1,	 8, 
						M2,	 8, 
						M3,	 8
					}

					Method (_DSM, 4, NotSerialized)
					{
						Store (0xB3, M1)
						Store (0xA1, M2)
						Store (0xC2, M3)
						Store (Package (0x02)
							{
								"name", 
								Buffer (0x16)
								{
									"J-Micron JMB36x eSATA"
								}
							}, Local0)
						DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
						Return (Local0)
					}
				}

This worked perfectly, although there is still a second "ghost" IDE entry when I run lspci. However, I don't care because first and foremost now there is an AHCI Sata entry, and that is the one getting picked up by the Apple AHCI driver, and it works perfectly. Any idea why there would still be an IDE entry?

And... thanks for your help! :-)

[LatinMcG]

nice job.
ghost entry hmm..can be disabled with the ide timing fix also from king. on the ide section (ioregexplorer). or it might be in bios ? do u have any ide devices at all ? can it be disabled in bios ? removed from dsdt ?

[stradivari1723]

LatinMcGyver75, on May 25 2011, 05:31 AM, said:

nice job.
ghost entry hmm..can be disabled with the ide timing fix also from king. on the ide section (ioregexplorer). or it might be in bios ? do u have any ide devices at all ? can it be disabled in bios ? removed from dsdt ?

I disabled it in DSDT by writing zeros to the same registers on the JMB1 entry.

However, there is now a secondary problem. Everything works great, but if you're using sleep, it somehow gets reset to IDE upon wake. Now what??

[LatinMcG]

the ini should fix that. or PINI

[stradivari1723]

LatinMcGyver75, on May 26 2011, 03:37 PM, said:

the ini should fix that. or PINI

I really need some more precise help, if you have time. I've been trying, but I'm still somewhat clueless. The way I understand it, PINI is a function you create (I've been following this thread here), and I assume it would write those same registers I used in my initial device call during startup, right? But... how to I identify where the registers are located (i.e., how do I identify the device, etc.) Sorry, maybe that question doesn't even make sense??

But anyway, if I'm able to make that function successfully, then where do I call it from? _WAK? And I don't really understand the "disable register" business... is that during prepare to sleep? So where do I put that? And what would it look like?? :-(

Sorry, as you can see, I'm stumbling in the darkness. :-)

[stradivari1723]

stradivari1723, on May 29 2011, 03:52 PM, said:

I really need some more precise help, if you have time. I've been trying, but I'm still somewhat clueless. The way I understand it, PINI is a function you create (I've been following this thread here), and I assume it would write those same registers I used in my initial device call during startup, right? But... how to I identify where the registers are located (i.e., how do I identify the device, etc.) Sorry, maybe that question doesn't even make sense??

But anyway, if I'm able to make that function successfully, then where do I call it from? _WAK? And I don't really understand the "disable register" business... is that during prepare to sleep? So where do I put that? And what would it look like?? :-(

Sorry, as you can see, I'm stumbling in the darkness. :-)

Okay, I managed to seemingly get it working. All I did was to add a PINI function right before the _WAK entry:

Method (PINI, 0, NotSerialized)
	{
		Store (0xB3, \_SB.PCI0.PEX3.JMB0.M1)
		Store (0xA1, \_SB.PCI0.PEX3.JMB0.M2)
		Store (0xC2, \_SB.PCI0.PEX3.JMB0.M3)
	}

Then called PINI () from within _WAK. It seems to work fine with only those changes. Should I be worried? Am I missing something vital that will cause problems or corruption down the road?

[LatinMcG]

u got it right.

[stradivari1723]

LatinMcGyver75, on May 30 2011, 04:49 PM, said:

u got it right.

Hey! Well, that's good to hear. :-)

What was that all about Disable Registers and stuff, then? Not needed, I guess...

Now, next question. :-) How to get WOL working... guh.

[LatinMcG]

disable register or enable. is what u actually just applied. the register bits u changed to enable ahci.

wol. make sure u add pwr to the device 0x04 or 0x05

[stradivari1723]

LatinMcGyver75, on May 31 2011, 03:34 PM, said:

wol. make sure u add pwr to the device 0x04 or 0x05

You mean during _PTS?

[LatinMcG]

nah  look at the ar9285 dsdt fix.. youll see the _PWR

Name (_PRW, Package (0x02) {0x0B, 0x05}) // If you want WOL(Wake on LAN support) if not use desired sleep state.

with ioregexplorer find where lan is at. then u have to mod.

[stradivari1723]

LatinMcGyver75, on Jun 2 2011, 03:49 PM, said:

nah  look at the ar9285 dsdt fix.. youll see the _PWR

Name (_PRW, Package (0x02) {0x0B, 0x05}) // If you want WOL(Wake on LAN support) if not use desired sleep state.

with ioregexplorer find where lan is at. then u have to mod.

Thanks for your continued support!

So I can just add that into the device () entry? I think I already know where the device is listed in the DSDT (it is called Device (GIGE) I think). I'll give it a try when I get home. So with that entry, the port will remain powered during sleep... but fans and all will still go off? And WOL packets will be recognized...? I also wonder (out loud, to myself, at this point LOL!) if adding this line will cause OS X to enable the "Wake for administrative access" option in Energy Saver. It probably doesn't even need to be there though, right? I mean, WOL is a hardware solution, no?

[stradivari1723]

Okay, so this did not work. My ethernet entry looks like this:

			Device (GBE)
			{
				Name (_ADR, 0x00190000)
				Name (_PRW, Package (0x02)
				{
					0x0B, 
					0x05
				})
			}

But when I put it to sleep, same behaviour as before: goes to sleep fine, but link lights on NIC port are off, and can't WOL.

Any other ideas?? :-(

I have BIOS set to allow power on from PCI and from PCI-e. There is no "Wake on administrative access" option in Energy Saver...

[LatinMcG]

put back to original with no mod in lan then use ioregexplorer to see what it shows. screenshot ?

post your dsdt also. and model of mobo.( rev)

i think 0x0B is wrong one to use.

[stradivari1723]

LatinMcGyver75, on Jun 3 2011, 04:07 PM, said:

put back to original with no mod in lan then use ioregexplorer to see what it shows. screenshot ?

post your dsdt also. and model of mobo.( rev)

i think 0x0B is wrong one to use.

Screenshot of Intel Gigabit NIC entry in ioreg with no mod in DSDT:
 Screen_shot_2011_06_03_at_4.39.51_PM.png   105.2K   41 downloads

DSDT I am currently using, with Device(JMB0) and Device(JMB1) entries modified to get AHCI working, PINI method to restore registers for JMB, and PINI() call in _WAK to restore AHCI mode upon wake, and finally (of course) the DTGP method for hacks. LAN is untouched:
 dsdt.aml.zip   12.98K   56 downloads

Motherboard is Asus P8P67 Pro Rev. 3.0 B3

Let me know if I've missed anything...