SSE3 - Used for work, or just a roadblock?

[HotShot]

Do the SSE3 instructions actually help Rosetta work, or are they just a holdup stopping otherwise capable CPU's from doing their thing?

 

Is there any hope/development being done to get SSE2 folks (like myself) cooking with PPC compiled programs?

[INFNITE]

Do the SSE3 instructions actually help Rosetta work, or are they just a holdup stopping otherwise capable CPU's from doing their thing?

 

Is there any hope/development being done to get SSE2 folks (like myself) cooking with PPC compiled programs?

<{POST_SNAPBACK}>

 

i would like to know as well

[Guspaz]

Rosetta is an emulator. Since it uses SSE3 this probably means it uses SSE3 instructions when translating its intermediate bytecode into native x86 machine code, if and when the appropriate SSE3 instructions would result in less code.

 

COULD Rosetta as a technology work without SSE3? Yes. But if Rosetta is indeed using SSE3 instructions in its translations, it's very unlikely there will ever be a version that does not require SSE3.

 

Personally I'm more surprised that Apple isn't using AMD64/EMT64. The Pentium 4s that they are shipping in the dev boxes support AMD64/EMT64, and you get way more registers in AMD64/EMT64 mode, and register shortages are, as I understand it, one of the biggest problems with translating PPC code to x86; the PPC has way more registers (even with AMD64/EMT64).

 

Take all of this with a grain of salt, though; I'm no expert in processors or emulation.

[knux]

I just read the wikipedia articles on Rosetta and SSE3 and a this is what stood out to me:

 

SSE3 adds 13 new instructions [over SSE2]... More specifically, instructions to add and subtract the multiple values stored within a single register have been added. These instructions simplify the implementation of a number of DSP and 3D operations.

So right now making sure 3D support and things like sound are running properly in Rosetta makes good sense as these really matter to customers. I'm sure there are other reasons but this seems straight forward enough to suggest it's important to Rosetta and the anti pirate angle is a freebie.

 

Just my random thoughts, I'm no expert

[Caulfield14]

Personally I'm more surprised that Apple isn't using AMD64/EMT64. The Pentium 4s that they are shipping in the dev boxes support AMD64/EMT64, and you get way more registers in AMD64/EMT64 mode, and register shortages are, as I understand it, one of the biggest problems with translating PPC code to x86; the PPC has way more registers (even with AMD64/EMT64).

ADC has told developers who are looking to write SSE3 code to provide non-SSE3 code as well. Specifically, they are telling developers to use #IFDEFs around SSE3 code the same way they have been told for Altivec.

 

Since generating SSE3 code is a compiler option, I'm sure they will support non-SSE3 code.

 

Rosetta clearly uses SSE3 extensions for performance, and thus it may always require SSE3. As for 64-bit, I'm sure Apple will encourage more use for it once they get their OS 64-bit clean, which any G5 owner knows it is not. Since the OS runs in 32-bit mode (for now), there is no point in developing with the 64-bit instruction set, as you can't currently run the code in Mac OS.