Speedstepping Atom N270 in Dell Mini 9

[kdawg]

OK I've got speedstep working on my Desktop rig using this basic technique. Anyone have time to take a peek at this to see if there is any glaring problems? Speedstep works with the VoodooPower.kext but it's a little choppy. When I use this DSDT I only get .8 GHz.

 

Works great on my GA-EP35-DS4 with a Q9450. I know the N270 supports speedstepping so this has to be doable. Anyone?

 

 

	Scope (_PR)
{
	Processor (CPU0, 0x00, 0x00001010, 0x06){

	Name (_PPC, 0x00)
	Name (_PCT, Package (0x02)
	{
		ResourceTemplate ()
		{
			Register (FFixedHW, 	// PERF_CTL
				0x10,				  // Bit Width
				0x00,			   // Bit Offset
				0x0000000000000199, // Address
				,)
		}, 

		ResourceTemplate ()
		{
			Register (FFixedHW, 	// PERF_STATUS
				0x10,			   // Bit Width
				0x00,				// Bit Offset
				0x0000000000000198, // Address
				,)
		}
	})

	Name (_PSS, Package (0x04)
	{
		Package (0x06)// P-State 0
		{
			1596, 		// f in MHz
			2000, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x00000C20, // value written to PERF_CTL; fid=12, vid=32
			0x00000C20	// value of PERF_STATE after successful transition; fid=12, vid=32
		}, 

		Package (0x06)// P-State 1
		{
			1330, 		// f in MHz
			1500, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x00000A1A, // value written to PERF_CTL; fid=10, vid=26
			0x00000A1A	// value of PERF_STATE after successful transition; fid=10, vid=26
		}, 

		Package (0x06)// P-State 2
		{
			1064,		// f in MHz
			1000, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x00000812, // value written to PERF_CTL; fid=8, vid=18
			0x00000812	// value of PERF_STATE after successful transition; fid=8, vid=18
		}, 

		Package (0x06)// P-State 3
		{
			798, 		// f in MHz
			600, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x0000060A, // value written to PERF_CTL; fid=6, vid=10
			0x0000060A	// value of PERF_STATE after successful transition; fid=6, vid=10
		},
	})
}

Processor (CPU1, 0x01, 0x00001010, 0x06){

	Name (_PPC, 0x00)
	Name (_PCT, Package (0x02)
	{
		ResourceTemplate ()
		{
			Register (FFixedHW, 	// PERF_CTL
				0x10,				// Bit Width
				0x00,			   // Bit Offset
				0x0000000000000199, // Address
				,)
		}, 

		ResourceTemplate ()
		{
			Register (FFixedHW, 	// PERF_STATUS
				0x10,			   // Bit Width
				0x00,				// Bit Offset
				0x0000000000000198, // Address
				,)
		}
	})

	Name (_PSS, Package (0x04)
	{
		Package (0x06)// P-State 0
		{
			1596, 		// f in MHz
			2000, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x00000C20, // value written to PERF_CTL; fid=12, vid=32
			0x00000C20	// value of PERF_STATE after successful transition; fid=12, vid=32
		}, 

		Package (0x06)// P-State 1
		{
			1330, 		// f in MHz
			1500, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x00000A1A, // value written to PERF_CTL; fid=10, vid=26
			0x00000A1A	// value of PERF_STATE after successful transition; fid=10, vid=26
		}, 

		Package (0x06)// P-State 2
		{
			1064,		// f in MHz
			1000, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x00000812, // value written to PERF_CTL; fid=8, vid=18
			0x00000812	// value of PERF_STATE after successful transition; fid=8, vid=18
		}, 

		Package (0x06)// P-State 3
		{
			798, 		// f in MHz
			600, 		// P in mW
			10, 		// Transition latency in us
			10, 		// Bus Master latency in us
			0x0000060A, // value written to PERF_CTL; fid=6, vid=10
			0x0000060A	// value of PERF_STATE after successful transition; fid=6, vid=10
		},
	})
}
}