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DSDT fixes for Gigabyte boards


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#1
iSoprano

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I started this thread to get some info on making sleep work for my MB which is GA-EP35-DS3L. With the help of people in this forum, I was able to install snow leopard on to my system. I have managed to get most of the things working and was trying to get speedstepping work by following another topic on vanilla speedstepping. I've managed to put together my DSDT which works for me, may work for others too with same or similar boards.

The extensions I have are fakeSMC, LegacyHDA for Audio, OpenHaltRestart and platformUUID.
The CPU is Q6600 and my MB bios is F6.

The only thing that is not working for me right now is sleep. The monitor shuts off but the hard disk and fan keeps spinning. So please if anyone could help me in fixing this. I am a total noab when it comes to DSDT editing, i just follow whatever was given by others in the forum, pray :D and reboot

UPDATE- Fellow Gigabyte users, Master Chief, who is well known in our community has kindly agreed to help GB users in patching our DSDT to enable speedstepping, sleep(which is a major pain in most of the boards) and also polish some of the fixes which are already floating around in the forum. Part 1, USB fixes has been given below. Waiting for Part 2 from Master Chief.


UPDATE - 2 - Vanilla speedstepping with low temp, around 38-40C with sleep. The DSDT contains USB fixes by Master Chief, CMOS reset, HPET, SATA built-in,Native AppleLPC trick, DSDT entry for Nvidia 9600GT, Audio for ALC888 (still need LegacyHDA.kext in extra), SLEEP. Attached File  dsdt.aml.zip   5.88KB   1835 downloads

UPDATE - 3 - ICH9 users, we need device Id injection of ICH10 for our USB to enable sleep. Also pls mod your AppleLPC which for GA-EP35-DS3 users will be PX40. This dsdt has SMBus and EC fix by Master Chief. Thanks to user mm67 :)
Attached File  dsdt.aml_21_10_2009.zip   5.17KB   712 downloads

UPDATE - 4 - ICH9 users, we need device Id injection for SMBus. My latest DSDT has this and also few more refinements as per Master Chief.
Attached File  dsdt.aml_22_10_2009.zip   4.64KB   665 downloads

UPDATE - 5 - After Latest round of fixes (TIMR, RTC, IPIC) I've put back DSDT entry for Nvidia 9600GT
Attached File  dsdt.aml_24_10_2009.zip   4.76KB   922 downloads
Attached File  dsdt.dsl_24_10_2009.zip   9.36KB   1632 downloads

UPDATE - 6 - Latest DSDT which uses MC's OSXrestart.kext. Shutdown works (based on mm67's code). I'm no longer using openhaltrestart.kext
Attached File  dsdt.aml.zip   2.18KB   4364 downloads
Attached File  com.apple.Boot.plist.zip   875bytes   3072 downloads

This DSDT works for me for all the above fixes, so please do be careful and make appropriate changes to your DSDT by comparison.

#2
Master Chief

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Lets start by fixing USB stuff. The reason for this is that I see something that isn't right. Let's use USB0 as an example:
USB0)
{
Name (_ADR, 0x001D0000)
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}

Return (0x03)

}

Method (_DSM, 4, NotSerialized)
{
Store (Package (0x02)
{
"device-id",
Buffer (0x04)
{
0x34, 0x3A, 0x00, 0x00
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}

Name (_PRW, Package (0x02)
{
0x03,
0x03
})
} _linenums:0'>Device (<strong class='bbc'>USB0</strong>) { Name (_ADR, 0x001D0000) Method (_S3D, 0, NotSerialized) { <strong class='bbc'>If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03)</strong> } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x34, 0x3A, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x03, <strong class='bbc'>0x03</strong> }) }
And this is how is should be:
Device (UHC1) // Renamed from: USB0            {                Name (_ADR, 0x001D0000)                // Newly added: USB_RES—USB Resume Enable Register (ICH9R-3169722.pdf /16.1.24 / page 642).                OperationRegion (BAR0, PCI_Config, 0xC4, One)                Field (BAR0, ByteAcc, NoLock, Preserve)                {                    USBW,   2, Offset (0x01)                }                Method (_S3D, 0, NotSerialized) // S3 Device State                {                    Return (0x02)                }                Method (_PSW, 1, NotSerialized) // Power State Wake                {                    If (Arg0)                    {                        Store (0x03, USBW) // Monitor port for remote wakeup and connect/disconnect events.                    }                    Else                    {                        Store (Zero, USBW) // Monitoring disable.                    }                }                Name (_PRW, Package (0x02) // Power Resources for Wake                {                     0x03,                     0x04 // Lowest supported sleep state.                })                Method (_DSM, 4, NotSerialized) // Device Specific Method                {                    Store (Package (0x02)                    {                        "device-id",                         Buffer (0x02)                        {                            0x34, 0x3a, 0x00, 0x00                        }                    }, Local0)                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                    Return (Local0)                }            }
Now search and replace "USB0" with "UHC1". Then repeat this step for every single Device (USBn) in your DSDT. You should search for: 0x001D0000, 0x001D0001, 0x001D0002, 0x001A0001, 0x001A0001 and 0x001A0002. Like I said fix these first. And don't forget to change all callers of USBn !!!

Note: Comment out Device (USB3) with help of /* */

Next target, one of two for today, is Device (USBE) which currently looks like this:
Device (USBE)            {                Name (_ADR, 0x001D0007)                Method (_S3D, 0, NotSerialized)                {                    If (LEqual (OSFL, 0x02))                    {                        Return (0x02)                    }                    Return (0x03)                }                Name (_PRW, Package (0x02)                {                    0x0D,                     0x03                })                Method (_DSM, 4, NotSerialized)                {                    Store (Package (0x04)                        {                            "AAPL,clock-id",                             Buffer (One)                            {                                0x01                            },                             "device_type",                             Buffer (0x05)                            {                                "EHCI"                            }                        }, Local0)                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                    Return (Local0)                }            }
Which I want you to change to:
Device (EHCI) // Renamed from: USBE - Extended with Power Management and Port Wake Capabilities.            {                Name (_ADR, 0x001D0007)                OperationRegion (PMCS, PCI_Config, 0x54, 0x02) // Power Management Control/Status (ICH9R-3169722.pdf / 17.1.19 / page 664).                Field (PMCS, WordAcc, NoLock, Preserve)                {                        ,   15,                    PMES,   1                } // Bit 15, PME Status, single bit.                OperationRegion (PWCR, PCI_Config, 0x62, 0x02) // Port Wake Capabilities Register (ICH9R-316972.pdf / 17.1.25 / page 667).                Field (PWCR, AnyAcc, NoLock, Preserve)                {                    URE2,   9                }                Method (_PSW, 1, NotSerialized)                {                    If (LEqual (Arg0, Zero))                    {                        Store (Zero, URE2) // Clear all bits.                    }                    If (LEqual (Arg0, One))                    {                        Store (0x01FF, URE2) // Set bits 0-8                    }                }                Name (_PRW, Package (0x02)                {                    0x0D,                     0x03                })                Method (_DSM, 4, NotSerialized)                {                    Store (Package (0x06)                    {                        "AAPL,current-available",                        0x05DC,                        "AAPL,current-extra",                        0x04B0,                        "AAPL,current-in-sleep",                        0x09C4                    }, Local0)                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                    Return (Local0)                }            }
And the last Device change for today is Device (USE2) which looks like this now:
Device (USE2)            {                Name (_ADR, 0x001A0007)                Method (_S3D, 0, NotSerialized)                {                    If (LEqual (OSFL, 0x02))                    {                        Return (0x02)                    }                    Return (0x03)                }                Name (_PRW, Package (0x02)                {                    0x0D,                     0x03                })                Method (_DSM, 4, NotSerialized)                {                    Store (Package (0x04)                        {                            "AAPL,clock-id",                             Buffer (One)                            {                                0x02                            },                             "device_type",                             Buffer (0x05)                            {                                "EHCI"                            }                        }, Local0)                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                    Return (Local0)                }            }
Which I want you to change to this:
Device (UHCI) // Renamed from: USE2 - Extended with Power Management and Port Wake Capabilities.            {                Name (_ADR, 0x001A0007)                    OperationRegion (PMCS, PCI_Config, 0x54, 0x02) // Power Management Control/Status (ICH9R-3169722.pdf / 17.1.19 / page 664).                Field (PMCS, WordAcc, NoLock, Preserve)                {                        ,   15,                    PMES,   1                 } // Bit 15, PME Status, single bit.                OperationRegion (PWCR, PCI_Config, 0x62, 0x02) // Port Wake Capabilities Register (ICH9R-316972.pdf / 17.1.25 / page 667).                Field (PWCR, AnyAcc, NoLock, Preserve)                {                    URE2,   9                }                Method (_PSW, 1, NotSerialized)                {                    If (LEqual (Arg0, Zero))                    {                        Store (Zero, URE2) // Clear all bits.                    }                    If (LEqual (Arg0, One))                    {                        Store (0x01FF, URE2) // Set bits 0-8                    }                }                Name (_PRW, Package (0x02)                {                    0x0D,                    0x03                })                Method (_DSM, 4, NotSerialized)                {                    Store (Package (0x06)                    {                        "AAPL,current-available",                        0x05DC,                        "AAPL,current-extra",                        0x04B0,                        "AAPL,current-in-sleep",                        0x09C4                    }, Local0)                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                    Return (Local0)                }            }
And as you might have notices, this requires some other additions to your DSDT. And this is what you need to change:
Method (_L0D, 0, NotSerialized)
		{
			Notify (\_SB.PCI0.USBE, 0x02)
			Notify (\_SB.PCI0.USE2, 0x02)
			Notify (\_SB.PWRB, 0x02)
			Notify (\_SB.PCI0.HDEF, 0x02)
		}
Which I want you to change into this:
Method (_L0D, 0, NotSerialized)            {                // New Power Management Control                If (\_SB.PCI0.EHCI.PMES)                {                    Store (0x01, \_SB.PCI0.EHCI.PMES) // Port Wake Implemented                    Notify (\_SB.PCI0.EHCI, 0x02) // Renamed from: USBE                    Notify (\_SB.PWRB, 0x02)                }                // New Power Management Control                If (\_SB.PCI0.UHCI.PMES)                {                    Store (0x01, \_SB.PCI0.UHCI.PMES) // Port Wake Implemented                    Notify (\_SB.PCI0.UHCI, 0x02) // Renamed from: USE2                    Notify (\_SB.PWRB, 0x02)                }                Notify (\_SB.PWRB, 0x02) // You might actually don't need this. Just check it!                Notify (\_SB.PCI0.HDEF, 0x02)

It's a lot of work. A {censored} load even. And I know, but it can be done. I also know that. It just takes time and effort :)

DO NOT COPY/PASTE CODE FROM THIS FORUM INTO YOUR DSDT!!!! It adds hidden characters which makes it impossible to compile!

For now later!

#3
iSoprano

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Chief, thanks a ton for helping :D and I've fixed the USB's as per your guidelines. Pls find the latest DSDT with USB fixes attached.

Attached Files



#4
Master Chief

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Great. I just opened my eyes and are having the usual morning coffee so bear with me for a few minutes while I try to wake up/read your modified dsdt.

Ok. Attached is a diff -uw output showing a problem. You have to fix those weird looking indentions because this make it a lot harder to read. Are you perhaps using tabs instead of plain simple spaces?

And please fix your post; please don't quote the whole post, or it will become a pain for me to read – I am suffering from RSI which I tell you can be quite painful at times!

Edit: Have you tried your modified dsdt.aml already?

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#5
mm67

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With these changes I get back the old usb removal warning after sleep and wake up using usb doesn't work.

#6
Master Chief

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With these changes I get back the old usb removal warning after sleep and wake up using usb doesn't work.

First, please do not quote the whole post. See my previous post for reasoning. Thank you.

You can read the ACPI specification and see that every change is right on target, and works on all ASUS boards. We might however need to adjust something, which I am currently still unaware of, simply because I don't have a Gigabyte motherboard.

But more importantly; I don't see any files attached, so I can't do anything with this post now can I. Please attach a clean/unmodified DSDT and your patched copy, because then and only then can I try to fix it for you.

#7
iSoprano

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Chief, I compiled/Decompiled ?? the DSDT again and I didn't get any errors. Yes, I am using the modified DSDT.

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#8
mm67

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First, please do not quote the whole post. See my previous post for reasoning. Thank you.

You can read the ACPI specification and see that every change is right on target, and works on all ASUS boards. We might however need to adjust something, which I am currently still unaware of, simply because I don't have a Gigabyte motherboard.

But more importantly; I don't see any files attached, so I can't do anything with this post now can I. Please attach a clean/unmodified DSDT and your patched copy, because then and only then can I try to fix it for you.


I will check if I still have that some where. Just figured out how to enable vanilla Gigabyte steepstepping, like this:
Scope (\)    {        Name (SSDT, Package (0x18)        {            "CPU0IST ",             0xDFEEDE00,             0x0000022A,             "CPU1IST ",             0xDFEEE2C0,             0x00000152,             "CPU0CST ",             0xDFEEE6E0,             0x0000018A,             "CPU1CST ",             0xDFEEE870,             0x0000018A,             "CPU2IST ",             0xDFEEE420,             0x00000152,             "CPU3IST ",             0xDFEEE580,             0x00000152,             "CPU2CST ",             0xDFEEEA00,             0x0000018A,             "CPU3CST ",             0xDFEEEB90,             0x0000018A        })        Name (CFGD, 0x040383F2)        Name (\PDC0, 0x80000000)        Name (\PDC1, 0x80000000)        Name (\PDC2, 0x80000000)        Name (\PDC3, 0x80000000)    }    Scope (\_PR.CPU0)    {        Name (HI0, 0x00)        Name (HC0, 0x00)        Name (TLD0, 0x00)        Method (_PDC, 1, NotSerialized)        {            CreateDWordField (Arg0, 0x08, CAP0)            Store (CAP0, PDC0)            If (LEqual (TLD0, 0x00))            {                If (LEqual (And (PDC0, 0x0A), 0x0A))                {                    If (And (CFGD, 0x02))                    {                        OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02                            )))                        Load (IST0, HI0)                    }                    Store (0x01, TLD0)                }            }        }    }    Scope (\_PR.CPU1)    {        Name (HI1, 0x00)        Name (HC1, 0x00)        Name (TLD1, 0x00)        Method (_PDC, 1, NotSerialized)        {            CreateDWordField (Arg0, 0x08, CAP1)            Store (CAP1, PDC1)            If (LEqual (TLD1, 0x00))            {                If (LEqual (And (PDC1, 0x0A), 0x0A))                {                    If (And (CFGD, 0x02))                    {                        OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05                            )))                        Load (IST1, HI1)                    }                    If (And (CFGD, 0x10))                    {                        OperationRegion (CST1, SystemMemory, DerefOf (Index (SSDT, 0x0A)), DerefOf (Index (SSDT, 0x0B                            )))                        Load (CST1, HC1)                    }                    Store (0x01, TLD1)                }            }        }    }    Scope (\_PR.CPU2)    {        Name (HI2, 0x00)        Name (HC2, 0x00)        Name (TLD2, 0x00)        Method (_PDC, 1, NotSerialized)        {            CreateDWordField (Arg0, 0x08, CAP2)            Store (CAP2, PDC2)            If (LEqual (TLD2, 0x00))            {                If (LEqual (And (PDC2, 0x0A), 0x0A))                {                    If (And (CFGD, 0x02))                    {                        OperationRegion (IST2, SystemMemory, DerefOf (Index (SSDT, 0x0D)), DerefOf (Index (SSDT, 0x0E                            )))                        Load (IST2, HI2)                    }                    If (And (CFGD, 0x10))                    {                        OperationRegion (CST2, SystemMemory, DerefOf (Index (SSDT, 0x13)), DerefOf (Index (SSDT, 0x14                            )))                        Load (CST2, HC2)                    }                    Store (0x01, TLD2)                }            }        }    }    Scope (\_PR.CPU3)    {        Name (HI3, 0x00)        Name (HC3, 0x00)        Name (TLD3, 0x00)        Method (_PDC, 1, NotSerialized)        {            CreateDWordField (Arg0, 0x08, CAP3)            Store (CAP3, PDC3)            If (LEqual (TLD3, 0x00))            {                If (LEqual (And (PDC3, 0x0A), 0x0A))                {                    If (And (CFGD, 0x02))                    {                        OperationRegion (IST3, SystemMemory, DerefOf (Index (SSDT, 0x10)), DerefOf (Index (SSDT, 0x11                            )))                        Load (IST3, HI3)                    }                    If (And (CFGD, 0x10))                    {                        OperationRegion (CST3, SystemMemory, DerefOf (Index (SSDT, 0x16)), DerefOf (Index (SSDT, 0x17                            )))                        Load (CST3, HC3)                    }                    Store (0x01, TLD3)                }            }        }    }

This is pure vanilla from acpidump, all that needs to be changed is value of CFGD, new one is 0x040483F2
and these If (LEqual (And (PDC0, 0x0A), 0x0A)) lines must be like this If (LEqual (And (PDC0, 0x09), 0x09)).
This gives vanilla P-states, on my board there is only two. Changing the value of pdc makes tables load and
changing cfgd loads npss tables, original value loads spss tables

#9
Master Chief

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Chief, I compiled/Decompiled ?? the DSDT again and I didn't get any errors. Yes, I am using the modified DSDT.

Perfect. And you don't have any of the issues mm67 is having?

p.s. I still have to look at the new file, but have you fixed the weird indentions (remember I just woke up)?

#10
iSoprano

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Perfect. And you don't have any of the issues mm67 is having?

p.s. I still have to look at the new file, but have you fixed the weird indentions (remember I just woke up)?


For me still I don't have sleep so unable to test mm67's scenario. I had used tabs earlier but it's fixed now. Appreciate your help and believe me been looking forward to your next lesson :(

#11
Master Chief

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I will check if I still have that some where.

Would you mind sticking to the topic at hand, and please do not dump unrelated stuff here, which should be part of the DSDT - Vanilla Speedstep thread. Not to mention that I already posted a better solution there. End of discussion.

p.s. Show some respect for an old guy in pain – I can barely find a position in front of my computer without pain – so please, really, fix your post.

#12
mm67

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Would you mind sticking to the topic at hand, and please do not dump unrelated stuff here, which should be part of the DSDT - Vanilla Speedstep thread. Not to mention that I already posted a better solution there. End of discussion.

p.s. Show some respect for an old guy in pain – I can barely find a position in front of my computer without pain – so please, really, fix your post.


Somehow I was under the impression that this thread was about vanilla speedstepping...
Anyway, here is dsdt.dsl with Your modifications:
Attached File  usbtest.dsl.zip   11.35KB   68 downloads

and for comparison here is one with fully working usb:
Attached File  dsdt.dsl.zip   10.83KB   142 downloads

#13
Master Chief

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Somehow I was under the impression that this thread was about vanilla speedstepping...
Anyway, here is dsdt.dsl with Your modifications:
Attached File  usbtest.dsl.zip   11.35KB   68 downloads

and for comparison here is one with fully working usb:
Attached File  dsdt.dsl.zip   10.83KB   142 downloads

Changing the Device names should not be a problem. Really. And I don't think that the problem is related to the changes to/in UHCn but EHCI and/or UHCI.

You might be able to verify this, but start by looking at Method (_L0D) first. There you'll find two if clauses. I wonder if PMES is high on your board i.e. comment the If (\_SB.PCI0.[E/u]HCI.PMES) { bits out, but leave the rest intact. Don't forget to add // for the closing }. If that makes it work for your board, then that bit is not high.

And if that didn't work, then change the EHCI/UHCI methods bit by bit.

Good luck!

#14
FKA

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Somehow I was under the impression that this thread was about vanilla speedstepping...
Anyway, here is dsdt.dsl with Your modifications:
Attached File  usbtest.dsl.zip   11.35KB   68 downloads

and for comparison here is one with fully working usb:
Attached File  dsdt.dsl.zip   10.83KB   142 downloads


I don't know if this is technically correct but it works for my USB devices:

http://www.insanelym...p...8014&st=260

I'm still using RIP script but I understand this is to overcome my sh1tty TSSTCorps DVDR.

Master Chief - would really appreciate any advice can you offer regarding adding SBUS (currently using your legacy SMC and AGPM kext.)?

I've added NVPM to my 9500 GT device properties but still only have this in IOREG under PCI0:
Attached File  Screen_shot_2009_10_04_at_13.48.24.png   35.63KB   547 downloads

and how do you think this could be cleaned up:
{Processor (CPU0, 0x00, 0x00000410, 0x06) {}Processor (CPU1, 0x01, 0x00000410, 0x06) {}Processor (CPU2, 0x02, 0x00000410, 0x06) {}Processor (CPU3, 0x03, 0x00000410, 0x06) {}Name (CFGD, 0x040383F2)Name (PDC0, 0x80000000)}Scope (_PR.CPU0){Method (_CST, 0, NotSerialized){If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10)))){Return (Package (0x02){One,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x00, // Bit Width0x00, // Bit Offset0x0000000000000000, // Address,)},One,0x9D,0x03E8}})}If (And (PDC0, 0x0300)){If (And (CFGD, 0x20)){Return (Package (0x03){0x02,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000000, // Address,)},One,One,0x03E8},Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000010, // Address,)},0x02,One,0x01F4}})}}If (And (CFGD, 0x20)){Return (Package (0x03){0x02,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000000, // Address,)},One,One,0x03E8},Package (0x04){ResourceTemplate (){Register (SystemIO,0x08, // Bit Width0x00, // Bit Offset0x0000000000000414, // Address,)},0x02,One,0x01F4}})}Return (Package (0x02){One,Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01, // Bit Width0x02, // Bit Offset0x0000000000000000, // Address,)},One,One,0x03E8}})}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (Package (0x02){ResourceTemplate (){Register (FFixedHW,0x10,0x00,0x0000000000000199,,)},ResourceTemplate (){Register (FFixedHW,0x10,0x00,0x0000000000000198,,)}})}Method (_PSS, 0, NotSerialized){Return (Package (0x03){Package (0x06){0x0C20,0x000124F8,0xA0,0x0A,0x0820,0x0820},Package (0x06){0x0A9C,0xFDE8,0xA0,0x0A,0x071C,0x071C},Package (0x06){0x0918,0xEA60,0xA0,0x0A,0x061A,0x061A}})}}Scope (_PR.CPU1){Method (_CST, 0, NotSerialized){Return (^^CPU0._CST ())}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (^^CPU0._PCT ())}Method (_PSS, 0, NotSerialized){Return (^^CPU0._PSS ())}}Scope (_PR.CPU2){Method (_CST, 0, NotSerialized){Return (^^CPU0._CST ())}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (^^CPU0._PCT ())}Method (_PSS, 0, NotSerialized){Return (^^CPU0._PSS ())}}Scope (_PR.CPU3){Method (_CST, 0, NotSerialized){Return (^^CPU0._CST ())}Method (_PPC, 0, NotSerialized){Return (Zero)}Method (_PCT, 0, NotSerialized){Return (^^CPU0._PCT ())}Method (_PSS, 0, NotSerialized){Return (^^CPU0._PSS ())}}


p.s. i find the green green grass of thailand helps a bundle with RSI - doesn't do much for the old synapsis though :)

#15
mm67

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Changing the Device names should not be a problem. Really. And I don't think that the problem is related to the changes to/in UHCn but EHCI and/or UHCI.

You might be able to verify this, but start by looking at Method (_L0D) first. There you'll find two if clauses. I wonder if PMES is high on your board i.e. comment the If (\_SB.PCI0.[E/u]HCI.PMES) { bits out, but leave the rest intact. Don't forget to add // for the closing }. If that makes it work for your board, then that bit is not high.

And if that didn't work, then change the EHCI/UHCI methods bit by bit.

Good luck!


With these modifications I have no more problems with sleep.
Attached File  usbtest2.dsl.zip   11.46KB   262 downloads

Ehci modifications make ehci ports show up as internal, otherwise they are shown as expansion slots which seems to kill
power to usb during sleep.Uhci device modifications give wake up by usb.

Would you mind sticking to the topic at hand, and please do not dump unrelated stuff here, which should be part of the DSDT - Vanilla Speedstep thread. Not to mention that I already posted a better solution there. End of discussion.


Just checked Your code again, what makes You think that it is better to have a fixed PSS table in dsdt for one specific processor. My method uses motherboard's own pss tables so they are dynamical. No matter if You change processor or overclock, speedstepping always works.

Attached Files



#16
FKA

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I don't see the point in running 2 DSDT speedstepping threads.

Post moved: http://www.insanelym...p;#entry1301888

D.

#17
Master Chief

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With these modifications I have no more problems with sleep.Attached File  usbtest2.dsl.zip   11.46KB   262 downloads
Ehci modifications make ehci ports show up as internal, otherwise they are shown as expansion slots which seems to kill
power to usb during sleep.

Great. Nice work.

With these modifications I have no more problems with sleep. Uhci device modifications give wake up by usb.

That's a good start. I however fail to see any logic in using the wrong device name, and then having to set device_type to "EHCI". Yes, you might need to change the device_id but that's about it.

Just checked Your code again, what makes You think that it is better to have a fixed PSS table in dsdt for one specific processor. My method uses motherboard's own pss tables so they are dynamical. Now matter if You change processor or overclock, speedstepping always works.

The reason is pretty obvious; the PSS object data in the BIOS is usually way overpowered. Giving it less juice makes it life longer. I'll let people decide what they want to use, but I think to know the answer already.

#18
iSoprano

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Righty Hoe!

I've got as far as changing the P and C state parts as per MC's v2.8.


Do you see cst info in IO register? I've noticed that when we don't have this the processor runs 10C hotter

#19
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I don't see the point in running 2 DSDT speedstepping threads.

Post moved: http://www.insanelym...p;#entry1301888

D.

Looking pretty good. Just give it a go.

#20
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Looking pretty good. Just give it a go.


is the c-state call on CPU core No:2
{                    Or (TBLD, 0x03, TBLD) // Setting bit 0 & 1 (simulating a CST table load).                    Load (STBL, HNDL)                }

processor specific ??

D.





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