(HD Audio) How to clear TCSEL via DSDT?

[proteinshake]

Hey there,

if anybody has an idea how to clear TCSEL via DSDT - that would be great. Right now I'm running out of ideas..

Bits 0-2 need to be cleared for me in order to have audio output with AppleHDA.kext, in fact manually setpci -s 00:1b.0 44.b=0 does the magic! But upon startup and after wake from standby address offset 44h is reset to 7 - so bits 0-2 are back to 1. Damn.

I know VoodooHDA will clear TCSEL, so does ALSA. 

 

I've tried:
 

QUOTE 

Device (HDEF)
{
...
OperationRegion (TCSL, PCI_Config, 0x44, One)
Field (TCSL, ByteAcc, NoLock, Preserve)
{ 
TSEL, 8
}
...

writing 0x00 to TSEL via Method (PINI) won't work. Method (_INI) inside Device (HDEF) won't work. 

Anybody got an idea?  

[Rampage Dev]

You can use a status to return zero to kill the HDEF using a Ssdt and in the same DSDT create a new device called hdau for onboard audio with the same address as HDEF so the old code gets killed and replaced by the new one. Toledia script is coded to look for HDEF which is not a good idea but you can do a find and replace in his script to replace all HDEF to hdau then you can run his script. This is what I do for the Haswell msi boards. I can make up a ssdt if needed. Also keep in mind killing HDEF can cause the system not to boot on some boards but this is worth a try.

[proteinshake]

Many thanks for chiming in here Rampage Dev, but I have a working AppleHDA.kext and a working DSDT. Everything is loaded and setup, there's just no actual output.

 

My problem is:

 

TCSEL—Traffic Class Select Register

(Intel® High Definition Audio Controller—D27:F0)

Address Offset: 44h Attribute: R/W Default Value: 00h Size: 8 bits Function Level Reset: No

This register assigned the value to be placed in the TC field. CORB and RIRB data will always be assigned TC0.

Bit

Description

7:3

Reserved.

2:0

Intel® HIgh Definition Audio Traffic Class Assignment (TCSEL)— R/W.
This register assigns the value to be placed in the Traffic Class field for input data,

output data, and buffer descriptor transactions. 000 = TC0
001 = TC1
010 = TC2

011 = TC3 100 = TC4 101 = TC5 110 = TC6 111 = TC7

NOTE: These bits are not reset on D3HOT to D0 transition; however, they are reset by PLTRST#. 

 

 

 

After boot and wake from S3 the address offset reads 0x07 .. or 111 = TC7, this results in no sound output.

Overriding 44h manually via setpci -s 00:1b.00 44.b=00 .. and voila, sound output.

setpci -s 00:1b.00 44.b=07 .. sound output gone again.

setpci -s 00:1b.00 44.b=F8 (VoodooHDA-Style) .. sound is back, TCSEL is back to TC0.

 

Now I could do this all day long but I'd rather not.

 

For me it's all about making this stick. Maybe this can't be done via DSDT at all, cause I've tried couple of things (uncertain of what ACPI instructions OS X actually REALLY cares about) .. as mentioned .. VoodooHDA will do this and ALSA:

 

-    /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)

-     * TCSEL == Traffic Class Select Register, which sets PCI express QOS
-     * Ensuring these bits are 0 clears playback static on some HD Audio
-     * codecs
-     */
-    update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);

 

 

VoodooHDA:
 

   vendorId = mDeviceId & 0xffff;

    if (vendorId == INTEL_VENDORID) {
        /* TCSEL -> TC0 */
        UInt8 value = mPciNub->configRead8(0x44);
        mPciNub->configWrite8(0x44, value & 0xf8);
//        logMsg("TCSEL: %02x -> %02x\n", value, mPciNub->configRead8(0x44));
    }

 

[darkvoid]

proteinshake,

 

CodecCommander could be easily modified to do what you require.

https://github.com/the-darkvoid/EAPD-Codec-Commander

 

You can just add a write command on wake-up in order to set TCSEL.

 

I will see about adding it when I get home.

 

Update:

I have now added TCSEL clearing on wake-up support to CodecCommander

[proteinshake]

Darkvoid, you are the man!   I will test this ASAP.