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[Guide 2018] Z820 - HIGH SIERRA, The great guide (Sucess)

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@hugodlc 

 

Man, You've made my day - there's hope to get pm working here.

 

I've tried to use the modified SSDT-1.aml to generate the SSDT and edited the resulting DSDT to include all 16 cores.
 

The problem that persists though is an "Out of control with CPU numbers error" in the clover boot-log.

 

I suspect that the reason for that is the unique problem with the Ivy-Bridge E5 2687w v2 which needs to have cpu-scopes from Scope (\_SB.C001)  to Scope (\_SB.C010) and Scope (\_SB.C101) to Scope (\_SB.C110) instead of Scope (\_SB.C000) to Scope (\_SB.C00F) and Scope (\_SB.C100) to Scope (\_SB.C10F).

 

Attached are the files I've tried.

 

Maybe someone could point me in the right direction here since I don't have a clue how to change them properly.

 

 

 

 

SSDT-1.aml

SSDT.aml

bootlog.txt

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2 hours ago, amadeusex said:

@hugodlc 

 

Man, You've made my day - there's hope to get pm working here.

 

I've tried to use the modified SSDT-1.aml to generate the SSDT and edited the resulting DSDT to include all 16 cores.
 

The problem that persists though is an "Out of control with CPU numbers error" in the clover boot-log.

 

Is your PM working though?

I believe that dmsg flag of "Out of control with CPU numbers" is just a warning that you have more than 16 cores and OSX might not like that, but it is a Clover warning flag, not really an error AFAIK.

Edited by hugodlc

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3 hours ago, hugodlc said:

 

Is your PM working though?

I believe that dmsg flag of "Out of control with CPU numbers" is just a warning that you have more than 16 cores and OSX might not like that, but it is a Clover warning flag, not really an error AFAIK.

Hi 

 

Well that's not that easy to answer - according to HW Monitor there's activity on the Graph but the nominal readouts stay at 3.37 GHz - Have a look.

The 1st screenshot is Idle with Chrome open. - the 2nd shows a cinebench multicore run (@ 2/3 in the graph timeline )

 

Turbo gets never activated - even with the cinebench single core bechmark the frequency never goes over 3.37. (dropdown screenshot)

 

 

 

IDLE

 

Screen Shot 2019-08-12 at 10.28.25.png

 

 

CINEBENCH RUN 

 

 

Screen Shot 2019-08-12 at 09.03.52.png

 

In the non-graph the readout of the cpu CPU cores 1-8 stays always at x34 and 3.37 GHz. Only Cpu-Package average and the Power Consumption readouts fluctuate.

 

drop down hwmonitor .png

Screen Shot 2019-08-12 at 10.40.55.png

Edited by amadeusex
More clarification

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9 hours ago, amadeusex said:

Well that's not that easy to answer - according to HW Monitor there's activity on the Graph but the nominal readouts stay at 3.37 GHz - Have a look.

 

It's not working, have you done all the other steps in the guide?

-Bios settings Runtime Power Management 

-Patch AICPUPM kext

-Install Legacyx86PlattformPlugin.kext

Try this for ssdtPRGen

./ssdtPRGen.sh -cpus 2 -c 3 -l 32 -target 1 -mode custom -p 'E5-2687W v2'

 

and finally edit the resulting SSDT adding the extra cores like you did last time.

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12 hours ago, amadeusex said:

I suspect that the reason for that is the unique problem with the Ivy-Bridge E5 2687w v2 which needs to have cpu-scopes from Scope (\_SB.C001)  to Scope (\_SB.C010) and Scope (\_SB.C101) to Scope (\_SB.C110) instead of Scope (\_SB.C000) to Scope (\_SB.C00F) and Scope (\_SB.C100) to Scope (\_SB.C10F).

 

The numbering is in Hex, so 0-9,A-F. Would be 1-16 in decimal.

You can change the Scope numbering so the next CPU is 10,11,12...19,1A,1B...1F I chose to shift the numbering to 100s just because It's easier to read and less likely to make mistakes at 3am.

The CPU numbering is cosmetic in the sense that as long as the cores get assigned a unique id and they are in ascending sequence to one another, the kernel will hopefully recognize them and use them correctly. 

But if it's a numbering mess, then you SSDT will be very messy and hard to understand and tweak.

 

The only thing I'm not sure about my setup is if the Cores should be populated like I did.

Cpu1-Core1

Cpu1-Core2

Cpu1-Core3

...

Cpu2-Core1

Cpu2-Core2

Cpu3-Core3

 

Or... 

Cpu1-Core1

Cpu2-Core1

Cpu1-Core2

Cpu2-Core2

Cpu1-Core3

....

 

It may also be something to consider, but at least in my case with the 2667 the current way works, and my benchmark numbers are equal or better than Windows numbers.

 

Also another thing that confused me before is that when you do get PM to work (with my CPU at least) you will see the frequency numbers change and have many other options but mostly down. So I thought turbo wasn't working, but it looks to be a HW sensors problem not reporting single CPU turbo states, and also the fact that these CPU's turbo at 4000MHz is only single core turbo, but when all cores get the boost, x34 is the maximum.

Hope all this helps a bit

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1 hour ago, hugodlc said:

The numbering is in Hex, so 0-9,A-F. Would be 1-16 in decimal.

 

- that's why You end up with \_SB.C010 and \_SB.C110 instead of \_SB.C00F and \_SB.C10F when You start with \_SB.C001 / C101.

 

 

Well - I've tried what you suggested but still no c-states working.

 

I really have wasted a couple of days trying and editing and whatnot.

 

Multicore results aren't that bad - slightly better than on Win 10 so i guess in general the machine is working.

Single core is way lower though (3100 vs 3670 in Win 10) but looking at the bright side here and not worrying so much.

 

On another note I've edited Your SSDT-1.aml because there was something i've noticed with the scopes.

 

 

 

Screen Shot 2019-08-12 at 21.37.42.png

 

Here's the (supposedly) corrected SSDT-1.aml

 

SSDT-1.aml

Edited by amadeusex

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15 minutes ago, amadeusex said:

Well - I've tried what you suggested but still no c-states working

 

Can you post your SSDT as generated by ssdt script?

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3 hours ago, amadeusex said:

On another note I've edited Your SSDT-1.aml because there was something i've noticed with the scopes.

 

 

 

Screen Shot 2019-08-12 at 21.37.42.png

 

Here's the (supposedly) corrected SSDT-1.aml

 

SSDT-1.aml

 

Which was wrong - here's another one.

 

SSDT-1.aml

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39 minutes ago, amadeusex said:

 

Which was wrong - here's another one. 

 

SSDT-1.aml

 

Thanks for finding those errors, like I said figuring out PM at 3am is not an exact science.
I've tweaked your SSDT file and hope it will work.

ssdt.aml

 

As for my fixed and updated files, if they help anyone with dual E5-2667 V2 CPU's

Here they are:

SSDT-1.aml

SSDT.aml

DSDT.aml

 

 

PM working... :)

1685884578_ScreenShot2019-08-12at7_06_56PM.png.d6b72510e1bab89e5a025a0a6e53f784.png

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Thanks for tweaking it but id still doesn't work ... 

 

Could You share Your 

AICPUPM.kext & Legacyx86PlattformPlugin.kext ?

 

 

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1 hour ago, amadeusex said:

Thanks for tweaking it but id still doesn't work ... 

 

Could You share Your 

AICPUPM.kext & Legacyx86PlattformPlugin.kext ? 

 

 

Kexts.zip

 

Sure, here. (they go in S>L>E)

 

Remember to rebuild your caches after install.

Edited by hugodlc

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Now if this isn't going to drive me crazy I don't know what is ...

 

I had a HDD failure while trying to get working PM. I also had an old SSD with High Sierra from my other machine z820 v1 with the dual sandy bridge 2670 v1.

 

Now ... I thought it is worth a shot and booted up with the USB drive and copied the EFI from the z820 v2 to the SSD. 

The elaborate SSDT and DSDT combo didn't work of course so i tried an earlier combo and take a guess - C-states are still not working but the CPU now runs up to 3.8 GHz.

 

My best guess is that (i remember reading somewhere about it but can't remember where) the 2687w v2 needs the also the sandy-bridge patch (step 1 of stinga's  tutorial - step 28 of bilbo's guide)

because i left the AICPUPM.kext i've patched for the 2670v1 (<- Sandy Bridge CPU) untouched on purpose. 

 

Strange though is that albeit the single-core performance climbed from 3100 to 3500 in geekbench 4 the multicore sacked to 26700 (from 37-38k).

 

... to be continued - sigh !

 

 

Edit - Do we have PM ?

 

1302443903_ScreenShot2019-08-13at06_32_58.png.dad59b9c6198a5a1b3fdf7b449621384.png

Edited by amadeusex

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That looks like PM, can't say for sure why your performance is down, but at least it looks like you're getting proper power states.

Is it stable?

In the past I've had PM working but after a few minutes the computer slows down and then crashes.

 

This slow process is what kept me in El Capitan for so long, it takes a lot of time to get it right as most people don't have these CPU's and there's no help, so it's a lot of research and trial and error. (But so worth it in the end)

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Now here's the catch ...

 

Turns out the SSDT-1.aml i've used is the one bilbo provided (the one with the many scopes).

The system was sluggish already and i just kept it on an older SSD as a backup so it's difficult to judge from here about the what causes it.

 

 

I've just replaced it with the one i've edited and am stuck again without any c-states whatsoever.

 

Right now i have to get some sleep bc i promised to take my daughter to the beach and will be on tour (Wednesday till Sunday) so no more tinkering for now.

We're closing in i guess ... somehow hahaha 

 

Take care and thanks a lot :) 

 

Here's geekbench 4 without c-states btw ...

 

 

 

Screen Shot 2019-08-13 at 07.10.20.png

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7 hours ago, hugodlc said:

Ok, when you have time, test these...

 

SSDT-1.aml

ssdt.aml

 

The document “ssdt.aml” could not be opened. 

 

iASL returned:

 

Loading Acpi table from file iASLte2IZw.aml

Acpi table [SSDT] successfully installed and loaded

Pass 1 parse of [SSDT]

 

:)

 

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On 8/11/2019 at 4:07 PM, hugodlc said:

Weird, I just saw that, but it is not an issue for boot or PM right? 

 

I really don't know what's going on. And I don't think PM works at all. You highlighted on a following post how cpu loading order on my system isn't an issue related to the 26x7 26x3 CPUs issue.

As things stand right now, the machine sometimes crashes on boot, or while using a pro-app (FCP or Logic Pro, Adobe suite). On the other hand, I could surf the web and listen to music all day without a crash.

I'm using an hp z620, late bios jul-2019 (03.95 Rev.A), dual e5-2650 v2 cpus. With an nvidia k500 on the first graphics slot, a bluetooth/wifi card in the 3rd slot, and a firewire400/800 card in the 2nd graphics slot (x16). The fusion card was taken off the system, and I have no plans on using it. Overall the system seems stabler and with higher scores in mojave than it did with high sierra. Things become progressively worse after applying patches. After generating the ssdt-1 file I couldn't even drop ssdt oem tables without a boot freeze (just plain freeze, no KP) You're welcome to look at both my pre and post patched DSDT/SSDTs and config file. Just keep in mind I haven't progressed beyond IRQ/HDEF patching in the supplied patched dsdt/ssdt files.

 

Here's the 1st issue that I'm having. The EUSB->EH01/USBE->EH02 patch doesn't work in the DSDT.aml. This results in no USB at all. However, after rolling the DSDT edits back to syntax-errors post-patching, and applying the USB patch via clover config, USB works fine.

z620_latest_BIOS_v2_cpus_DSDT-SSDT_patched.zip

z620_latest_BIOS_v2_cpus_DSDT-SSDT_unpatched.zip

config.plist

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Finally ...

 

z820v2 with 3.92 Bios dual Xeon E5 2687W v2 64GB ram and a Radeon Red Devil RX-580 8 GB

 

My EFI Folder - EFI.zip

My aicpupm.kext AICPUPM.kext

My patched LegacyX86PlatformPlugin.kext LegacyX86PlatformPlugin.kext Put both Kexts to S/L/E and repair permissions.

ssdrPRGen command used : ./ssdtPRGen.sh -m custom (ssdt-1.aml provided by @bilbo renamed to SSDT.aml and placed to Desktop together with APIC.aml)

 

What did the trick was to use both patches mentioned in bilbos guide under point 28 !

 

What remains now is to reinstall High Sierra on a bigger disk or maybe even just restore the one i have to another SSD (i know bilbo doesn't like the idea but this is going to save a lot of time).

 

Thanks to @bilbo for the excellent guide and all the effort and to  @hugodlc for taking the time and all the back and forth tinkering ! 

 

1948496594_ScreenShot2019-08-14at02_00_03.png.0b3d6d41eca8d53ff0c1ed8e24ea84e8.png

1286888805_ScreenShot2019-08-14at01_28_06.thumb.png.b9a88e5e60a83efeac58c56173ff0d1b.png

756716851_ScreenShot2019-08-14at01_32_52.png.32ec0a773d0b9eee2451f32727ab811f.png

1883636697_ScreenShot2019-08-14at01_34_32.thumb.png.8033b34fdb362134cf3a1f51905963b4.png

 

 

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20 hours ago, amadeusex said:

What did the trick was to use both patches mentioned in bilbos guide under point 28 !

 

 

Weird that you need to use Sandy Bridge patches, but glad it works.

 

I studied your working SSDT and I believe that your CPU's probably show up out of order in IORegistry explorer, but that doesn't seem to be a problem for PM. I think this is because the new SSDTs generated behave like you have 1 CPU with 32 cores and everything clocks to the first CPU core.

 

I like this simplistic approach to making PM work on dual CPU computers, and I'm still trying to make it work on mine, but it refuses to work for some reason.  I got it to work but with a workaround.

I inserted my SSDT-1 details at the bottom of my main DSDT like we had to do before, and then ran the ssdrPRGen command, but I see there's either a bug or a condition with this dual CPU config and the script.

If I run it without the 'cpus 2' flag, it builds the SSDT with a ton of errors, but with all the CPU's.

If I run it with the flag, I get no errors, but only CPU cores 1-16.

 

So in the end I had to manually add the missing cores to the version without errors.

 

I was trying to come up with a simple way to make PM work on these CPU's to add to the guide, but it looks like it's a bit more complicated and can vary case by case.

 

Another note for anyone reading this with dual 2667 v2's I tried going back to my (SSDT-1 and SSDT) I posted in a previous post, and PM would not work. I don't fully understand why using this SSDT-1 and SSDT combo refuses to work when it was working before, so I traced my steps back, and the process that works is to first boot from a DSDT with the SSDT-1 info at the bottom of it and then add the SSDT info in a later boot. I guess a kernel cache is being made somewhere in the process, and it changes by doing it this way.

 

So the best way to make PM work for dual E5-2667 v2 is this.

 

Use this CPUs for your cpu definitions

Paste it at the end of your DSDT file just before the last closing bracket

2016072185_ScreenShot2019-08-14at12_01_18PM.png.8721b786f577916bee4a18870d2aa41e.png

etc...

641702303_ScreenShot2019-08-14at12_01_41PM.png.b49818c7c94effdfbc2db7b411ea011d.png

 

Then use this: SSDT.aml

 

Edit - Remove the old SSDT-1.aml, it's redundant now and may cause conflicts

 

In case different bios versions change anything, you can run the ssdrPRGen script to generate your own, but you will need to manually edit the resulting ssdt.aml to add the missing cores, but at least you can use mine for comparison.

 

 

Edited by hugodlc

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Yeah I guess the 1 CPU with 32 threads is the most plausible explanation but to be honest, after all those hours wasted I couldn't care less about why it works right now. :)

 

 

 

 

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Holy {censored}! I think I've made progress. I had to manually add more processor entries in my SSDT after the ssdtPRgen would only add 16 logical cores. I duplicated the first block of 16 logical entries C000-C00F and numerated each entry from C100 to C10F for the second block.

These are the flag/switches I fed ssdtPRGen.

ssdtPRGen.sh -mode custom -p 'E5-2650 v2' -b Mac-F60DEB81FF30ACF6 -c 3 -x 1 -cpus 2 -l 32 -target 1

This resulted in the first part of the screenshot below. Only 16 logical cores were defined in that block. My scores were very low. Didn't have low power or turbo modes. Speeds were stuck at 2.6ghz. Low and behold, with the edited SSDT (on the right side of the screenshot). Speeds fluctuated between 1.10ghz, and 3.4ghz as demanded. This resulted in higher scores for both GB4 and cinemabench. Now I have to test it for stability.

 

Screen Shot 2019-08-14 at 2.16.05 PM.png

Screen Shot 2019-08-14 at 1.56.32 PM.png

Screen Shot 2019-08-14 at 2.07.25 PM.png

Edited by gawdemmet
typoes and poor grammar

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5 hours ago, hugodlc said:

I studied your working SSDT and I believe that your CPU's probably show up out of order in IORegistry explorer, but that doesn't seem to be a problem for PM. I think this is because the new SSDTs generated behave like you have 1 CPU with 32 cores and everything clocks to the first CPU core.

 

 

I'm on tour now as mentioned earlier. I'll check the IOreg readings when I get back.

 

As far as I remember though they show up just fine while clover boots for whatever reason.

 

Man I'm used to really weird stuff and a lot of times I think it has to do with Voodoo.

 

But it's also fun and just looking at a working system gives you the satisfaction to justify all the hassle :)

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16 minutes ago, gawdemmet said:

Speeds fluctuated between 1.10ghz, and 3.4ghz as demanded.

 

That looks like working PM!

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