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KernelAndKextPatches 10.13x,10.14.x,10.15.x X99/X299

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On 5/17/2019 at 6:16 AM, jamiethemorris said:

What is the xcpm_bootstrap patch for? Is it still useful necessary? My X99 wouldn't boot with it enabled after the 10.14.5 update (Thank you pitrysha for your help!). 

try this 

<dict>
				<key>Comment</key>
				<string>_xcpm_pkg_scope_msrs © PMHeart 10.14.5</string>
				<key>Disabled</key>
				<false/>
				<key>Find</key>
				<data>
				MdLotPz//w==
				</data>
				<key>MatchOS</key>
				<string>10.14.5</string>
				<key>Replace</key>
				<data>
				MdKQkJCQkA==
				</data>
			</dict>

 

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On 2/20/2019 at 3:33 PM, Pavo said:

Key thing to remember about this thread is it does not apply to you since you are using a C612 chipset not a X99 chipset. The thread is specific to X99 chipset builds.

No.    

 

The key thing to remember about this thread is that all of it applies to anyone with a C612.  Anything that goes for the X99, likewise goes and is applicable to the C612.  

 

Why?  Because the X99 and C612 are two different yield optimizations of the same chip.  They're not just the same chipset, but the same chip, down to the electrical pinout and die mask.  The X99 just has a couple features disabled to boost yield (specifically, support IPIMI/remote management and intel SPS server services).  But don't take my word for it - check for yourself - the X99 and C612 have the same datasheet.  The only distinction between them is a single SKU table that shows just how trivially different they are.  No distinction is made between them anywhere else in the datasheet.  All the same bits and registers and what have you are definitely the same :). 

 

Furthermore, as someone running a C612 motherboard - a Supermicro X10DAi - with dual Xeons and 56 logical cores working 100%, including power management, audio, XHCI etc. for a couple years now, I can empirically confirm that everything that applies to the X99 applies to the C612 in exactly the same way, and without exception. 

 

When I first discovered this, it was a bit surprising, especially given how unrelated to the two PCH names were.  But it makes sense - why bother designing an entire extra PCH for a relatively small slice of the consumer PC market (High End Desktop) when you can just use the enterprise server PCHs but with looser requirements (giving slightly better yields).  Regardless, I made the same assumption as you initially, but thankfully, all the work regarding the C612 was already done for me in the form of the work done for the X99 :).

Edited by metacollin

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Hello everyone,

 

First post on this forum. I post here because Kernel Patches are my problem, I think.

I am clean installing Mojave on my machine (X99-UD4 5820k), vanilla style. Very happy to better understand what I am doing.

 

I am trying to use those Kernel Patches to get power management working. But for the moment, the best I can do is this (picture), so not very good, CPU idle @ 3Ghz.

I think maybe it's because I'm using 10.14.5, maybe I should have started with 10.14.4, maybe the patch are not up yet?

Anybody here having good results with X99 and 10.14.5?

Would you mind telling me witch patches did you use?

 

I'm trying to get some help from reddit too, will update if need.

Thanks a lot. :)

 

EDIT: trying to delete one of my 2 pictures but can't find how to do it

 

1093413291_Screenshot2019-05-19at16_07_59.thumb.png.c610cb6b0a9438670dc19bea56ad4b54.png

 

idle.png

Edited by Isidore Isou
trying to delete one of my 2 pictures but can't find how to do it

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Also, I don't think this is as widely known as it should be, but most (if not all) of the security updates for 10.13.6 break the EIST Performance patch.  So the patches are build specific :(.  You can check what build you're running by going to About This Mac in the Apple menu, and clicking on the version number in the window.  

 

Anyway, I just created a version of oskarit's patch for the latest 10.13.6 build, 17G7024.

Note: the EIST patches are the same for Broadwell and Haswell.

EIST Performance fix by Okrasit modified by metacollin for 10.13.6 build 17G7024

Comment    String  <-> EIST Performance (c) Okrasit fix by metacollin for 10.13.6 build 17G7024
Disabled   Boolean <-> No
Find       Data    <-> C1E30848 63D389D0 48C1EA20 B9990100 000F3048 FF0559AF 6B004883 C4085B5D C3662E0F 1F840000 000000
MatchOS    String  <-> 10.13.6
MatchBuild String  <-> 17G7024
Replace    Data    <-> BB00FF00 004863D3 89D048C1 EA20B999 0100000F 3048FF05 59AF6B00 4883C408 5B5DC390 90909090 909090
Edited by metacollin

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Hello, metacollin

 

I tried to reach you out several times but I know that you're extremely busy.

So I have the same setup as you with the same CPUs and X10dai motherboard but I use Mojave 10.14.5 and Vega FE Graphic card.

 

Everything works fluidly expect the sleep.what's happing is my system goes to deep sleep but it restarts itself instead of resuming from the last state.

I worked with @MaLd0n to solve the sleep problems and we reached a dead end that is why I'm asking for help.

What I did:

 

1- I unlocked MSR registers to have native power management.

2- I mod my bios to get full NVMe support using this guide

 

What @MaLd0n helped me with:

 

1- fixing my DSDT file and added the proper patches.

2- adding my devices to the PCI list.

3- Add plug-in type in DSDT, so we can remove SSDT for pm.

4- testing all the darkwake=10 boot config. Nothing from the above worked.

*I attached my debug files using Runme.app

 

 

If you can have look in my debug files and maybe point me in what I'm missing I will be super grateful.

if you don't have the time please share with me your EFI folder and your DSDT file and the moded bios you use currently so maybe it will help me in figuring out what is the problem.

Send me Idriss-iMac-Pro.lan_2.zip

Edited by MMido

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XCPM 10.15Beta-1 updated for X99 System.

Thanks @PMheart

Edited by nmano

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XCPM 10.14.5 updated for X99 System.

Thanks to @vit9696 @PMheart.

 

Screen Shot 2019-06-23 at 11.17.15 PM.png

Edited by nmano

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On 5/28/2019 at 5:37 AM, MMido said:

Hello, metacollin

 

I tried to reach you out several times but I know that you're extremely busy.

So I have the same setup as you with the same CPUs and X10dai motherboard but I use Mojave 10.14.5 and Vega FE Graphic card.

 

Everything works fluidly expect the sleep.what's happing is my system goes to deep sleep but it restarts itself instead of resuming from the last state.

I worked with @MaLd0n to solve the sleep problems and we reached a dead end that is why I'm asking for help.

What I did:

 

1- I unlocked MSR registers to have native power management.

2- I mod my bios to get full NVMe support using this guide

 

What @MaLd0n helped me with:

 

1- fixing my DSDT file and added the proper patches.

2- adding my devices to the PCI list.

3- Add plug-in type in DSDT, so we can remove SSDT for pm.

4- testing all the darkwake=10 boot config. Nothing from the above worked.

*I attached my debug files using Runme.app

 

 

If you can have look in my debug files and maybe point me in what I'm missing I will be super grateful.

if you don't have the time please share with me your EFI folder and your DSDT file and the moded bios you use currently so maybe it will help me in figuring out what is the problem.

Send me Idriss-iMac-Pro.lan_2.zip

 

Hi MMido, I just upgraded to Mojave so I'm looking into the sleep problem.  FYI, the issue is much more difficult than simply restarting upon wake.  It isn't restarting per se, it is kernel panicking, but the default behavior is to immediately reboot.  You can find the panic logs after the fact, however.  

 

It seems that MacOS is having problems dealing with the PCIE non-transparent bridge between PCI0 and PCI1.  This is nothing you'll fix with DSDT hacks or Clover, it will require a kext or kernel patch at the minimum most likely.  I'll let you know if I figure anything out, but I wouldn't get to hopeful on this one.  Also, sleep is not really a priority for me and the X10DAI has mediocre sleep performance regardless (I'm sure you've noticed how long it takes to actually go to sleep).  This is just the nature of the board, it is meant as a workstation with 24/7 uptime  so the sleep is fairly rudimentary.  But I'll at least look into it.

 

Also, your machine is operating at 50% memory bandwidth, which will have a significant impact on performance in almost every task.  You should always run a minimum of 8 ram modules, as each CPU has 4 memory channels.  It would have been preferable to use 8x8GB sticks vs 4 x 16GB sticks.  It won't fix sleep or anything, but I strongly recommend getting 4 more sticks of RAM so all channels are populated as soon as you can, your machine will love you for it.  

Edited by metacollin

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On 5/20/2019 at 2:13 PM, metacollin said:

No.    

 

The key thing to remember about this thread is that all of it applies to anyone with a C612.  Anything that goes for the X99, likewise goes and is applicable to the C612.  

 

Why?  Because the X99 and C612 are two different yield optimizations of the same chip.  They're not just the same chipset, but the same chip, down to the electrical pinout and die mask.  The X99 just has a couple features disabled to boost yield (specifically, support IPIMI/remote management and intel SPS server services).  But don't take my word for it - check for yourself - the X99 and C612 have the same datasheet.  The only distinction between them is a single SKU table that shows just how trivially different they are.  No distinction is made between them anywhere else in the datasheet.  All the same bits and registers and what have you are definitely the same :). 

 

Furthermore, as someone running a C612 motherboard - a Supermicro X10DAi - with dual Xeons and 56 logical cores working 100%, including power management, audio, XHCI etc. for a couple years now, I can empirically confirm that everything that applies to the X99 applies to the C612 in exactly the same way, and without exception. 

 

When I first discovered this, it was a bit surprising, especially given how unrelated to the two PCH names were.  But it makes sense - why bother designing an entire extra PCH for a relatively small slice of the consumer PC market (High End Desktop) when you can just use the enterprise server PCHs but with looser requirements (giving slightly better yields).  Regardless, I made the same assumption as you initially, but thankfully, all the work regarding the C612 was already done for me in the form of the work done for the X99 :).

 

 

 

Hello bro,how to find the right patch?  I upgraded to 10.13.6 17G8037 ,but I can't Find the new patch

 

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I update 10.14.x and 10.15.x patches.

I disabled some XCPM Performance patches that's mean you don't need or disabled.

 

AppleIntelInfo.kext v3.0 Copyright © 2012-2017 Pike R. Alpha. All rights reserved.

Settings:
------------------------------------------
enableHWP............................... : 0
logMSRs................................. : 1
logIGPU................................. : 0
logIntelRegs............................ : 0
logCStates.............................. : 1
logIPGStyle............................. : 1
InitialTSC.............................. : 0x5bdabae44384 (3366 MHz)
MWAIT C-States.......................... : 8480

Processor Brandstring................... : Intel(R) Core(TM) i7-5960X CPU @ 3.00GHz

Processor Signature..................... : 0x306F2
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 2
 - Model................................ : 0x3F (63)

Model Specific Registers (MSRs)
------------------------------------------

MSR_IA32_PLATFORM_ID..............(0x17) : 0x8000000000000
------------------------------------------
 - Processor Flags...................... : 2

MSR_CORE_THREAD_COUNT.............(0x35) : 0x80010
------------------------------------------
 - Core Count........................... : 8
 - Thread Count......................... : 16

MSR_PLATFORM_INFO.................(0xCE) : 0x20080C3BF3811E00
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x1E (3000 MHz)
 - Ratio Limit for Turbo Mode........... : 1 (programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 1 (LPM supported)
 - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL........(0xE2) : 0x7E000403
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 1 (enabled)
 - C1 State Auto Demotion............... : 1 (enabled)
 - C3 State Undemotion.................. : 1 (enabled)
 - C1 State Undemotion.................. : 1 (enabled)
 - Package C-State Auto Demotion........ : 1 (enabled)
 - Package C-State Undemotion........... : 1 (enabled)

MSR_PMG_IO_CAPTURE_BASE...........(0xE4) : 0x10414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 1 (C6 is the max C-State to include)

IA32_MPERF........................(0xE7) : 0x426B47EBF6
IA32_APERF........................(0xE8) : 0x112EF4C5D45

MSR_FLEX_RATIO...................(0x194) : 0xE0000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x266E00002A00
------------------------------------------
 - Current Performance State Value...... : 0x2A00 (4200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0xFF00
------------------------------------------
 - Target performance State Value....... : 0xFF00 (25500 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0

IA32_THERM_INTERRUPT.............(0x19B) : 0x0

IA32_THERM_STATUS................(0x19C) : 0x88370000
------------------------------------------
 - Thermal Status....................... : 0
 - Thermal Log.......................... : 0
 - PROCHOT # or FORCEPR# event.......... : 0
 - PROCHOT # or FORCEPR# log............ : 0
 - Critical Temperature Status.......... : 0
 - Critical Temperature log............. : 0
 - Thermal Threshold #1 Status.......... : 0
 - Thermal Threshold #1 log............. : 0
 - Thermal Threshold #2 Status.......... : 0
 - Thermal Threshold #2 log............. : 0
 - Power Limitation Status.............. : 0
 - Power Limitation log................. : 0
 - Current Limit Status................. : 0
 - Current Limit log.................... : 0
 - Cross Domain Limit Status............ : 0
 - Cross Domain Limit log............... : 0
 - Digital Readout...................... : 55
 - Resolution in Degrees Celsius........ : 1
 - Reading Valid........................ : 1 (valid)

MSR_THERM2_CTL...................(0x19D) : 0x0

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - FOPCODE compatibility mode Enable.... : 0
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Split-lock Disable................... : 0
 - Performance Monitoring............... : 1 (available)
 - Bus Lock On Cache Line Splits Disable : 0
 - Hardware prefetch Disable............ : 0
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - GV1/2 legacy Enable.................. : 0
 - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - Adjacent sector prefetch Disable..... : 0
 - CFG Lock............................. : 0 (MSR not locked)
 - xTPR Message Disable................. : 1 (disabled)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x591200
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 89
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400000
------------------------------------------
 - EIST Hardware Coordination........... : 0 (hardware coordination enabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)
 - SpeedShift Technology Enable......... : 0 (disabled)
 - SpeedShift Interrupt Coordination.... : 0 (disabled)
 - SpeedShift Energy Efficient Perf..... : 0 (disabled)
 - SpeedShift Technology Setup for HWP.. : No (not setup for HWP)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x2A2A2A2A2A2A2A2A
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 2A (4200 MHz) 
 - Maximum Ratio Limit for C02.......... : 2A (4200 MHz) 
 - Maximum Ratio Limit for C03.......... : 2A (4200 MHz) 
 - Maximum Ratio Limit for C04.......... : 2A (4200 MHz) 
 - Maximum Ratio Limit for C05.......... : 2A (4200 MHz) 
 - Maximum Ratio Limit for C06.......... : 2A (4200 MHz) 
 - Maximum Ratio Limit for C07.......... : 2A (4200 MHz) 
 - Maximum Ratio Limit for C08.......... : 2A (4200 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x0

MSR_POWER_CTL....................(0x1FC) : 0x2104005B
------------------------------------------
 - Bi-Directional Processor Hot......... : 1 (enabled)
 - C1E Enable........................... : 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 14 (61 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x7FFD00014EA82
------------------------------------------
 - Package Power Limit #1............... : 3408 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 0 (disabled)
 - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)
 - Package Power Limit #2............... : 4090 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
 - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)
 - Lock................................. : 0 (MSR not locked)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x27442170
------------------------------------------
 - Total Energy Consumed................ : 40208 Joules (Watt = Joules / seconds)

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x1E
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x940000001B0460
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x94000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x0
MSR_PKGC6_IRTL...................(0x60b) : 0x0
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x26F4386B4F4C
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x11B14336
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x26F4386B4F4C
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x11B14336
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x2E4E3605AB42

IA32_TSC_DEADLINE................(0x6E0) : 0x5BDABF093E98

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency...... : 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency....... : 30 (3000 MHz)
Maximum Turbo Ratio/Frequency........... : 42 (4200 MHz)
P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ (12) 39 42 ]
CPU C3-Cores [ 1 2 5 6 8 12 14 ]
CPU C6-Cores [ 0 2 4 6 8 10 12 14 ]
CPU P-States [ (12) 34 39 42 ]
CPU C3-Cores [ 0 1 2 4 5 6 7 8 12 14 ]
CPU C6-Cores [ 0 2 4 6 8 10 12 14 15 ]
CPU P-States [ 12 34 35 39 (42) ]
CPU C3-Cores [ 0 1 2 4 5 6 7 8 12 14 15 ]
CPU P-States [ 12 32 34 35 39 (42) ]
CPU P-States [ 12 29 32 34 35 39 (42) ]
CPU C3-Cores [ 0 1 2 4 5 6 7 8 12 13 14 15 ]
CPU P-States [ (12) 29 32 34 35 37 39 42 ]
CPU P-States [ 12 29 30 32 34 35 37 39 (42) ]
CPU P-States [ 12 29 30 32 34 35 36 37 39 (42) ]
CPU P-States [ 12 29 30 31 32 34 35 36 37 39 (42) ]
CPU P-States [ 12 29 30 31 32 33 34 35 36 37 39 (42) ]
CPU C6-Cores [ 0 2 4 6 7 8 10 12 14 15 ]
CPU P-States [ (12) 28 29 30 31 32 33 34 35 36 37 39 42 ]
CPU C6-Cores [ 0 2 4 6 7 8 10 12 13 14 15 ]
CPU P-States [ 12 27 28 29 30 31 32 33 34 35 36 37 39 (42) ]
CPU C6-Cores [ 0 2 4 5 6 7 8 10 12 13 14 15 ]

 

Screen Shot 2019-10-11 at 5.04.33 AM.png

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A heads-up to any would be updaters:

The 10.15.1 update breaks the "xcpm_bootstrap_ © Pike R. Alpha 10.15.x" patch.
I don't know if any of the others are effected but I managed to boot by disabling just the  xcpm_bootstrap patch.

(Also there are new versions of Lilu, VirtualSMC, WhateverGreen and AppleALC for this update.)

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Hi, 

 

Everything works fine, but my Frequency Vectors are not loaded.

 

"sysctl -n machdep.xcpm.vectors_loaded_count" returns "0"

 

I have removed whatevergreen and lilu kexts

I had ssdt.aml and was returning 0. Then checked PluginType and removed ssdt.aml, same thing.

i7 5930k with radeon RX 5770 XT

 

Any thoughts? Don't want to be rude and spam my config before anyone asks.

Thanks!

 

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On 11/2/2019 at 3:20 PM, Chris192 said:

A heads-up to any would be updaters:

The 10.15.1 update breaks the "xcpm_bootstrap_ © Pike R. Alpha 10.15.x" patch.
I don't know if any of the others are effected but I managed to boot by disabling just the  xcpm_bootstrap patch.

(Also there are new versions of Lilu, VirtualSMC, WhateverGreen and AppleALC for this update.)

Also for me...:(

I have xcpm enabled, only with the flag on "Kernel XCPM". I tested a 20% performance loss with ceekbench compared to: 10.14.6. I don't understand... :wallbash:

HELP! nmano, HELP!

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Hi all, I have an ASUS X99-E 2101 with updated microcode and patched MSR. The 6800K is stuck on the base clock speed (3.40HGz) flat, in 10.15.1. Would really like to have the patches for 10.15.1 to allow for power management and overclocking.

 

Using all patches from OP for 10.15.x, excluding "_xcpm_core_scope_msrs © Pike R. Alpha". 

 

When disabling SpeedStep and setting a Tubo of 4.2GHz, this speed is always maintained.

Edited by Allubz

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10.15.2 WORKING KERNEL PATCHES!

 

Comment: _xcpm_performance_patch by JamesK

Find: 41C1E608 4963D689 D048C1EA 20

Replace: 41C1E608 B800FF00 0031D290 90

 

Comment: _xcpm_SMT_scope_msrs_1 by JamesK

Find: BE060000 005DE908 000000

Replace: BE060000 005DC390 909090

 

Comment: _xcpm_SMT_scope_msrs_2 by JamesK

Find: 31D2E844 FDFFFF

Replace: 31D29090 909090

 

Comment: _xcpm_pkg_scope_msrs by JamesK

Find: 31D2E879 FDFFFF

Replace: 31D29090 909090

 

Comment: _xcpm_core_scope_msrs by JamesK

Find: 31D2E857 FDFFFF

Replace: 31D29090 909090

 

Patches work. Enjoy!

Edited by JamesK
Update #3: Patches are now fully working enjoy!

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5 hours ago, Mike Ranger said:

Seems that there are new patches needed for 10.15.2.....

Any insight on what those will be?

 

Please see my post for the working patches. Enjoy.

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4 hours ago, JamesK said:

10.15.2 WORKING KERNEL PATCHES!

 

Comment: _xcpm_performance_patch by JamesK

Find: 41C1E608 4963D689 D048C1EA 20

Replace: 41C1E608 B800FF00 0031D290 90

 

Comment: _xcpm_SMT_scope_msrs_1 by JamesK

Find: BE060000 005DE908 000000

Replace: BE060000 005DC390 909090

 

Comment: _xcpm_SMT_scope_msrs_2 by JamesK

Find: 31D2E844 FDFFFF

Replace: 31D29090 909090

 

Comment: _xcpm_pkg_scope_msrs by JamesK

Find: 31D2E879 FDFFFF

Replace: 31D29090 909090

 

Comment: _xcpm_core_scope_msrs by JamesK

Find: 31D2E857 FDFFFF

Replace: 31D29090 909090

 

Patches work. Enjoy!

 

Confirmed, working. Thank you. Output from AppleIntelInfo.kext is as follows. 

 

AppleIntelInfo.kext v2.9 Copyright © 2012-2017 Pike R. Alpha. All rights reserved.

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 0
logCStates...............................: 1
logIPGStyle..............................: 1
InitialTSC...............................: 0xa3a9ef4d5f7 (340 MHz)
MWAIT C-States...........................: 8480

Processor Brandstring....................: Intel(R) Core(TM) i7-5820K CPU @ 3.30GHz

Processor Signature..................... : 0x306F2
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 2
 - Model................................ : 0x3F (63)

Model Specific Registers (MSRs)
------------------------------------------

MSR_IA32_PLATFORM_ID.............(0x17)  : 0x8000000000000
------------------------------------------
 - Processor Flags...................... : 2

MSR_CORE_THREAD_COUNT............(0x35)  : 0x6000C
------------------------------------------
 - Core Count........................... : 6
 - Thread Count......................... : 12

MSR_PLATFORM_INFO................(0xCE)  : 0x20080C3BF3812100
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x21 (3300 MHz)
 - Ratio Limit for Turbo Mode........... : 1 (programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 1 (LPM supported)
 - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x402
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 0 (disabled/unsupported)
 - C1 State Auto Demotion............... : 0 (disabled/unsupported)
 - C3 State Undemotion.................. : 0 (disabled/unsupported)
 - C1 State Undemotion.................. : 0 (disabled/unsupported)
 - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
 - Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x10414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 1 (C6 is the max C-State to include)

IA32_MPERF.......................(0xE7)  : 0x15ACE57876
IA32_APERF.......................(0xE8)  : 0x3B3F82F101

MSR_FLEX_RATIO...................(0x194) : 0xE0000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x266200002800
------------------------------------------
 - Current Performance State Value...... : 0x2800 (4000 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0xFF00
------------------------------------------
 - Target performance State Value....... : 0xFF00 (25500 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0

IA32_THERM_INTERRUPT.............(0x19B) : 0x0

IA32_THERM_STATUS................(0x19C) : 0x88460000
------------------------------------------
 - Thermal Status....................... : 0
 - Thermal Log.......................... : 0
 - PROCHOT # or FORCEPR# event.......... : 0
 - PROCHOT # or FORCEPR# log............ : 0
 - Critical Temperature Status.......... : 0
 - Critical Temperature log............. : 0
 - Thermal Threshold #1 Status.......... : 0
 - Thermal Threshold #1 log............. : 0
 - Thermal Threshold #2 Status.......... : 0
 - Thermal Threshold #2 log............. : 0
 - Power Limitation Status.............. : 0
 - Power Limitation log................. : 0
 - Current Limit Status................. : 0
 - Current Limit log.................... : 0
 - Cross Domain Limit Status............ : 0
 - Cross Domain Limit log............... : 0
 - Digital Readout...................... : 70
 - Resolution in Degrees Celsius........ : 1
 - Reading Valid........................ : 1 (valid)

MSR_THERM2_CTL...................(0x19D) : 0x0

IA32_MISC_ENABLES................(0x1A0) : 0x840089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - FOPCODE compatibility mode Enable.... : 0
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Split-lock Disable................... : 0
 - Performance Monitoring............... : 1 (available)
 - Bus Lock On Cache Line Splits Disable : 0
 - Hardware prefetch Disable............ : 0
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - GV1/2 legacy Enable.................. : 0
 - Enhanced Intel SpeedStep Technology.. : 0 (disabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - Adjacent sector prefetch Disable..... : 0
 - CFG Lock............................. : 0 (MSR not locked)
 - xTPR Message Disable................. : 1 (disabled)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x690A00
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 105
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400000
------------------------------------------
 - EIST Hardware Coordination........... : 0 (hardware coordination enabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)
 - SpeedShift Technology Enable......... : 0 (disabled)
 - SpeedShift Interrupt Coordination.... : 0 (disabled)
 - SpeedShift Energy Efficient Perf..... : 0 (disabled)
 - SpeedShift Technology Setup for HWP.. : No (not setup for HWP)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x2222282828282828
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 28 (4000 MHz) 
 - Maximum Ratio Limit for C02.......... : 28 (4000 MHz) 
 - Maximum Ratio Limit for C03.......... : 28 (4000 MHz) 
 - Maximum Ratio Limit for C04.......... : 28 (4000 MHz) 
 - Maximum Ratio Limit for C05.......... : 28 (4000 MHz) 
 - Maximum Ratio Limit for C06.......... : 28 (4000 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x0

MSR_POWER_CTL....................(0x1FC) : 0x2904005B
------------------------------------------
 - Bi-Directional Processor Hot..........: 1 (enabled)
 - C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 14 (61 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x7FFF80015FFF8
------------------------------------------
 - Package Power Limit #1............... : 4095 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
 - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)
 - Package Power Limit #2............... : 4095 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
 - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)
 - Lock................................. : 0 (MSR not locked)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x552033F
------------------------------------------
 - Total Energy Consumed................ : 5448 Joules (Watt = Joules / seconds)

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x21
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x940000001E0460
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x94000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x0
MSR_PKGC6_IRTL...................(0x60b) : 0x0
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x3153C9D05
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x3153F632A
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x11A2CD9750

IA32_TSC_DEADLINE................(0x6E0) : 0xA3AAF562EBC

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 33 (3300 MHz)
Maximum Turbo Ratio/Frequency............: 40 (4000 MHz)
P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ (12) 37 40 ]
CPU C6-Cores [ 0 2 4 6 8 10 ]
CPU P-States [ 12 35 37 (40) ]
CPU C6-Cores [ 0 2 4 6 8 9 10 ]
CPU P-States [ 12 32 35 37 (40) ]
CPU C6-Cores [ 0 2 3 4 5 6 8 9 10 ]
CPU P-States [ (12) 32 35 36 37 40 ]
CPU C6-Cores [ 0 2 3 4 5 6 8 9 10 11 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 8 9 10 11 ]
CPU P-States [ 12 32 35 36 37 39 (40) ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 ]
CPU P-States [ (12) 32 35 36 37 38 39 40 ]
CPU P-States [ 12 31 32 35 36 37 38 39 (40) ]
CPU P-States [ 12 31 32 33 35 36 37 38 39 (40) ]
CPU P-States [ 12 30 31 32 33 35 36 37 38 39 (40) ]
CPU P-States [ 12 30 31 32 33 34 35 36 37 38 39 (40) ]
CPU P-States [ 12 28 30 31 32 33 34 35 36 37 38 39 (40) ]
CPU P-States [ (12) 28 29 30 31 32 33 34 35 36 37 38 39 40 ]
CPU P-States [ (12) 25 28 29 30 31 32 33 34 35 36 37 38 39 40 ]
CPU P-States [ 12 25 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]
CPU P-States [ 12 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]
CPU P-States [ (12) 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ]
CPU P-States [ (12) 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ]
CPU P-States [ 12 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]
CPU P-States [ 12 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]
CPU P-States [ 12 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]

Geekbench 5.0.3 Run. 

438026797_Screenshot2019-12-11at11_33_52AM.thumb.png.fe7a0d71991f9730a94f5aed65837438.png

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2 hours ago, pitrysha said:

Thanks  JamesK !

Can anyone explain how this is calculated .

 

Well it requires a program like Hopper Disassembler to achieve it. Back when Catalina first came out, the patches posted by nmano didn't work for me, so I started digging in on how the other patches were done in Mojave by comparing, then I got the way on how to change those and have been making my own patches since as needed, in a nutshell.

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