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AICPMvers missing (but now found)

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Posted (edited)

...well, I've been dsdt diving...lol, and have a semi-working dsdt22.aml....the result however leaves me with higher than normal temps for cpu cores and heatsink and no AICPMvers in ioreg....I'm including one: dsdt.aml that does give me AICPM...and two: the dsdt22.aml that I want to use...but does not activate AICPM...dsdt22 needs the fix....

...a little guidance please...





edit: found my solution....moved scope, P001,P002,P003,P004 from dsdt to dsdt22, replacing existing... compiled and loaded up  :trumpet: ... now for onboard sound, as hdmi audio already works thru gfx card... :smoke:

...all this on Box 2 (P5N7A-VM)



AICPMVers 19136773.png

Edited by RobertX
just because

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Posted (edited)

If you think you have no proper or native SpeedStep with your Core2Quad CPU, you should not need any DSDT tuning. C2D/C2Q SpeedStep normally natively works with:

  1. activation of P-States + C-States generation in your Clover or Chameleon/Enoch settings
  2. FakeSMC keys (smc-compatible + REV/RVBF/RVUF) tuned to the values for the selected SMBIOS Mac model (for iMac10,1 profile: smc-mcp + 1.53f13)
  3. SMBIOS of Mac model with similar specs (in your case, iMac10,1 is the correct target imo)


Full details available through this post: https://osxlatitude.com/forums/topic/2673-performance-tuning-with-fakesmc/

Edited by Hervé

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Posted (edited)

hey Herve' ...my initial reason for the dsdt mucking was to get my chipset identified as MCP79(Nvidia) and not generic...in doing so, I lost AICPM support and temps increased on average 15 degrees C....around 51 -57 degrees C at idle....after this fix, temps are high 20s at idle and mid 50s under full load...and chipset is recognized.....so yes, I can run Box2 without dsdt edit...still, ...this board was a royal pain...mostly from outdated info circa 2009...but it just works!! 

...thanks for the reply



edit: removed this bold  text reference too from clover..just p and c state generation now



.clover does a drop cpupm table in ssdt  to avoid a kp at boot...and generates p and c states and enables c6


Edited by RobertX

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