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Been a while since I looked at this thread. Glad to see everyone got it working.  Awesome contributions from everyone involved that doesn’t just want answers without the hard work and testing...

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i 've read this tread i try to have my antelope zentour working on my asus prime X299-A with the TB3 ex.

i've install the SSDT from KGP and modified it with my PCIe location, but i've no luck.

i can see the the device when i plug it but there is no new audio device installed.

here is the picture when the device is plugged.

465120743_Capturedecran2018-08-04a11_08_57.thumb.png.46789ecc4237df466ea128de825071f6.png

 

and here is the modified SSDT

SSDT-X299-TB3-iMacPro-Combo-ASUS.aml

Anyone have a idea how to got this device working?

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zeyoung,

 

Does this antelope device use an kernel extension located in /Library/Extensions?

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Hi there.

 

Thanks to all for this amazing and useful topic!

 

Anybody has a problem with enabled iGPU and installed Alpine Ridge rev. 2.0?

When i enable iGPU macOS can start and say ‘error loading kernel cache 0x9‘ and when iGPU disabled macOS can start.

 

I manage to create my own ssdt for TB3 also i tried use arbitrary, different version of kext and uefi 64bit drivers, disconnect THB_C cable and High Sierra and Mojave.

All of this not working for my case.

 

After them i insert Alpine Ridge card into pci x8 and it works with igpu, but only in display output mode without TB3 (i have LG ultrafine 5k) and BIOS doesn't have TB setting menu in this case.

 

I need iGPU enabled for h264 encoding, for example, for recording video from screen.

 

Anybody has advice for me?

Edited by enotus

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On 8/12/2018 at 10:52 PM, remote.syst3m said:

zeyoung,

 

Does this antelope device use an kernel extension located in /Library/Extensions?

yes it use AntelopeUnifiedDriver.kext

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Great seeing the progress in this thread!

 

Has anyone had any success connecting a gigabyte alpine ridge card without the internal header, and making it appear with a device turned on and connected?

Edited by Ribor92

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Today I updated the bios of my GB Z370 to the F10 version, and I noticed new settings in the Thunderbolt section.
Now I have the THB_C cable disconnected and it is not comfortable to install it, so, someone who has the cable already connected (with similar hardware) can do some tests and see if anything changes?

 

1536103683_2018-08-3012_14_56.thumb.jpg.ee02e697e094f2b112bdbf7243eeb93a.jpg1829610176_2018-08-3012_15_10.thumb.jpg.9c2bb3790947c2c28d5af2b79bd80e3a.jpg

Edited by lelet

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Hi Guys,

 

Suddenly my Asus TB3 card started to appear in System Info/Thunderbolt with a lot of thunderbolt kexts loaded!!! 

 

For the very first time I've got:

  • 2 x Thunderbolt port information - although it seems no version info is gathered
  • 2 x Thunderbolt IP adapter detection - not in operation
  • Thunderbolt DP adapter detection  

 

Now, I'm not sure if I have a damaged card, since it does appear in my Asus X99 Deluxe II BIOS fully configured, but as soon as I power off or reset the motherboard the PCIEX16_5 slot shows "Not Present"...

 

The only way to get it back is to power off (power off PSU!) for about 10 minutes and it then gets detected again by Macosx...

 

Unfortunately at the moment I on't have a working Win10 installation to test...

 

What do you guys think ? Damage TB3 adaptor or a "miracle" ? :wink_anim:

 

180920164316.jpg

180920164425.jpg

180920164438.jpg

%22magic%22 thunderbolt 4.jpeg

%22magic%22 thunderbolt 3.jpeg

%22magic%22 thunderbolt 2.jpeg

%22magic%22 thunderbolt 1.jpeg

Send me Paulos-Mac-Pro.zip

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3 hours ago, augustopaulo said:

Hi Guys,

 

Suddenly my Asus TB3 card started to appear in System Info/Thunderbolt with a lot of thunderbolt kexts loaded!!! 

 

Looks rather like a miracle... or to say it in simple words... you are the one out of millions not affected by the virus... and nobody knows why.. :drool:

 

My goodness... you have a fully implemented local thunderbolt node

 

1630945565_Screenshot2018-09-20at22_18_05.png.1eac54b8f7807e2e33165951377de085.png

 

and even the thunderbolt bus driver loaded 

 

1339808352_Screenshot2018-09-20at22_22_22.png.98ad63d548d93b08734eaa4e5d74e820.png

 

While usually in TB Hackintosh systems only the IOThunderboltFamily.kext and ThunderboltNHI.kext are active, you also have the AppleThunderboltDPAdapaterFamily.kext, the AppleThunderboltDPOutAdapter.kext, the AppleThunderboltIP.kext  the AppleThunderboltPCIDownAdapter.kext active on your system.. 

 

Some TB kexts not marked in red are still missing though also on your system.. 

 

1640172455_Screenshot2018-09-20at22_19_41.png.b19490f36ad4f33b4e37c686136dae16.png

 

 

 

Anyway.. no idea how all this is possible without doing anything else then configuring the TB BIOS settings like we all did?

 

You do not even mention a SSDT, although I do not understand how you obtain without the latter the UPSB, DSB0, DSB1, DSB2, DSB4, NHI0 and XHC2 ACPI implementation.. 

 

 

Edited by KGP-iMacPro

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19 minutes ago, Tony Arnold said:

@augustopaulo would you mind uploading a copy of your EFI directory?

 

I guess he implemented it in his post? See his Send me Paulos-Mac-Pro.zip... 

 

But there is nothing than a DSDT.aml in EFI/CLOVER/ACPI/patched/.. 

Edited by KGP-iMacPro

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Seems that @augustopaulo performs some DSDT patching... Now the question is where all this comes from?

 

    Scope (_GPE)
    {
        OperationRegion (TCOS, SystemIO, 0x0464, 0x02)
        Field (TCOS, ByteAcc, NoLock, WriteAsZeros)
        {
            Offset (0x01), 
                ,   1, 
            DSCI,   1
        }

        Method (_L01, 0, NotSerialized)  // _Lxx: Level-Triggered GPE
        {
            Sleep (0xC8)
            Store (One, IO80)
            Sleep (0x0A)
            Store (Zero, Local1)
            If (LEqual (\_SB.PCI0.BR1A.PMEP, One))
            {
                Store (\_SB.PCI0.BR1A.PMEH (0x09), Local0)
            }
            Else
            {
                Store (\_SB.PCI0.BR1A.HPEH (0x09), Local0)
            }

            If (LEqual (ToInteger (TBRP), 0x22))
            {
                Store (0xFF, Local0)
                Store (One, Local1)
            }

            If (LNotEqual (Local0, 0xFF))
            {
                Store (One, Local1)
                Notify (\_SB.PCI0.BR1A.UPSB, Local0)
                Notify (\_SB.PCI0.BR1A.H001, Local0)
                Notify (\_SB.PCI0.BR1A.H002, Local0)
                Notify (\_SB.PCI0.BR1A.H003, Local0)
                Notify (\_SB.PCI0.BR1A.H004, Local0)
                Notify (\_SB.PCI0.BR1A.H005, Local0)
                Notify (\_SB.PCI0.BR1A.H006, Local0)
                Notify (\_SB.PCI0.BR1A.H007, Local0)
            }
          }
        }

            Device (BR1A)
            {
                Name (_ADR, 0x00010000)  // _ADR: Address
                OperationRegion (MCTL, SystemMemory, 0xE001A188, 0x04)
                Field (MCTL, ByteAcc, NoLock, Preserve)
                {
                        ,   3, 
                    HGPE,   1, 
                        ,   7, 
                        ,   8, 
                        ,   8
                }

                Method (_INI, 0, NotSerialized)  // _INI: Initialize
                {
                    Store (One, HGPE)
                    Return (Zero)
                }

                Name (_HPP, Package (0x04)  // _HPP: Hot Plug Parameters
                {
                    0x08, 
                    0x40, 
                    One, 
                    Zero
                })
                Name (SHPC, 0x40)
                Name (SPDS, 0x40)
                Name (MRLS, Zero)
                Name (CCOM, 0x10)
                Name (SPDC, 0x08)
                Name (MRLC, 0x04)
                Name (SPFD, 0x02)
                Name (SABP, One)
                Name (SPOF, 0x10)
                Name (SPON, 0x0F)
                Name (ALMK, 0x1C)
                Name (ALON, One)
                Name (ALBL, 0x02)
                Name (ALOF, 0x03)
                Name (PLMK, 0x13)
                Name (PLON, 0x04)
                Name (PLBL, 0x08)
                Name (PLOF, 0x0C)
                Name (HPEV, 0x0F)
                OperationRegion (PPA4, PCI_Config, Zero, 0x0100)
                Field (PPA4, ByteAcc, NoLock, Preserve)
                {
                    Offset (0xA0), 
                        ,   4, 
                    LDIS,   1, 
                    Offset (0xA2), 
                    Offset (0xA4), 
                    ATBP,   1, 
                        ,   1, 
                    MRSP,   1, 
                    ATIP,   1, 
                    PWIP,   1, 
                    HPSR,   1, 
                    HPCP,   1, 
                        ,   12, 
                    PSNM,   13, 
                    ABIE,   1, 
                    PFIE,   1, 
                    MSIE,   1, 
                    PDIE,   1, 
                    CCIE,   1, 
                    HPIE,   1, 
                    SCTL,   5, 
                    Offset (0xAA), 
                    SSTS,   7, 
                    Offset (0xAB), 
                    Offset (0xB0), 
                    Offset (0xB2), 
                    PMES,   1, 
                    PMEP,   1, 
                    Offset (0xB4)
                }

                Method (ATID, 0, NotSerialized)
                {
                    Return (And (SCTL, 0x03))
                }

                Method (PWID, 0, NotSerialized)
                {
                    Return (ShiftRight (And (SCTL, 0x0C), 0x02))
                }

                Method (PWCC, 0, NotSerialized)
                {
                    Return (ShiftRight (And (SCTL, 0x10), 0x04))
                }

                Method (ABPS, 1, NotSerialized)
                {
                    If (LEqual (Arg0, One))
                    {
                        Or (SSTS, One, SSTS)
                    }

                    Return (And (SSTS, One))
                }

                Method (PFDS, 1, NotSerialized)
                {
                    If (LEqual (Arg0, One))
                    {
                        Or (SSTS, 0x02, SSTS)
                    }

                    Return (ShiftRight (And (SSTS, 0x02), One))
                }

                Method (MSCS, 1, NotSerialized)
                {
                    If (LEqual (Arg0, One))
                    {
                        Or (SSTS, 0x04, SSTS)
                    }

                    Return (ShiftRight (And (SSTS, 0x04), 0x02))
                }

                Method (PDCS, 1, NotSerialized)
                {
                    If (LEqual (Arg0, One))
                    {
                        Or (SSTS, 0x08, SSTS)
                    }

                    Return (ShiftRight (And (SSTS, 0x08), 0x03))
                }

                Method (CMCS, 1, NotSerialized)
                {
                    If (LEqual (Arg0, One))
                    {
                        Or (SSTS, 0x10, SSTS)
                    }

                    Return (ShiftRight (And (SSTS, 0x10), 0x04))
                }

                Method (MSSC, 1, NotSerialized)
                {
                    If (LEqual (Arg0, One))
                    {
                        Or (SSTS, 0x20, SSTS)
                    }

                    Return (ShiftRight (And (SSTS, 0x20), 0x05))
                }

                Method (PRDS, 1, NotSerialized)
                {
                    If (LEqual (Arg0, One))
                    {
                        Or (SSTS, 0x40, SSTS)
                    }

                    Return (ShiftRight (And (SSTS, 0x40), 0x06))
                }

                Method (OSHP, 0, NotSerialized)
                {
                    Store ("SSTS", SSTS)
                    Store (Zero, HGPE)
                }

                Method (HPCC, 1, NotSerialized)
                {
                    Store (SCTL, Local0)
                    Store (Zero, Local1)
                    If (LNotEqual (Arg0, Local0))
                    {
                        Store (Arg0, SCTL)
                        While (LAnd (LNot (CMCS (Zero)), LNotEqual (0x64, Local1)))
                        {
                            Sleep (0x02)
                            Add (Local1, 0x02, Local1)
                        }

                        CMCS (One)
                    }
                }

                Method (ATCM, 1, NotSerialized)
                {
                    Store (SCTL, Local0)
                    And (Local0, ALMK, Local0)
                    If (LEqual (Arg0, One))
                    {
                        Or (Local0, ALON, Local0)
                    }

                    If (LEqual (Arg0, 0x02))
                    {
                        Or (Local0, ALBL, Local0)
                    }

                    If (LEqual (Arg0, 0x03))
                    {
                        Or (Local0, ALOF, Local0)
                    }

                    HPCC (Local0)
                }

                Method (PWCM, 1, NotSerialized)
                {
                    Store (SCTL, Local0)
                    And (Local0, PLMK, Local0)
                    If (LEqual (Arg0, One))
                    {
                        Or (Local0, PLON, Local0)
                    }

                    If (LEqual (Arg0, 0x02))
                    {
                        Or (Local0, PLBL, Local0)
                    }

                    If (LEqual (Arg0, 0x03))
                    {
                        Or (Local0, PLOF, Local0)
                    }

                    HPCC (Local0)
                }

                Method (PWSL, 1, NotSerialized)
                {
                    Store (SCTL, Local0)
                    If (Arg0)
                    {
                        And (Local0, SPON, Local0)
                    }
                    Else
                    {
                        Or (Local0, SPOF, Local0)
                    }

                    HPCC (Local0)
                }

                Method (_OST, 3, Serialized)  // _OST: OSPM Status Indication
                {
                    Switch (And (Arg0, 0xFF))
                    {
                        Case (0x03)
                        {
                            Switch (ToInteger (Arg1))
                            {
                                Case (Package (0x04)
                                    {
                                        0x80, 
                                        0x81, 
                                        0x82, 
                                        0x83
                                    }

)
                                {
                                    If (LNot (PWCC ()))
                                    {
                                        PWCM (One)
                                        Store (One, ABIE)
                                    }
                                }

                            }
                        }

                    }
                }

                Method (EJ0L, 1, NotSerialized)
                {
                    Store (0xFF, IO80)
                    Store (SCTL, Local0)
                    If (LNotEqual (ATID (), One))
                    {
                        And (Local0, ALMK, Local0)
                        Or (Local0, ALBL, Local0)
                    }

                    HPCC (Local0)
                    Store (SCTL, Local0)
                    Or (Local0, SPOF, Local0)
                    HPCC (Local0)
                    Store (SCTL, Local0)
                    Or (Local0, PLOF, Local0)
                    HPCC (Local0)
                    Store (SCTL, Local0)
                    Or (Local0, ALOF, Local0)
                    HPCC (Local0)
                }

                Method (PMEH, 1, NotSerialized)
                {
                    If (And (HPEV, SSTS))
                    {
                        If (ABPS (Zero))
                        {
                            ABPS (One)
                            Sleep (0xC8)
                        }
                    }

                    Return (0xFF)
                }

                Method (HPEH, 1, NotSerialized)
                {
                    If (LNot (HPCP))
                    {
                        Return (0xFF)
                    }

                    Sleep (0x64)
                    Store (Zero, CCIE)
                    If (And (HPEV, SSTS))
                    {
                        Store (0xFD, IO80)
                        Sleep (0x0A)
                        Store (PPXH (Zero), Local0)
                        Return (Local0)
                    }
                    Else
                    {
                        Return (0xFF)
                    }

                    Store (0xFC, IO80)
                    Sleep (0x0A)
                }

                Method (PPXH, 1, NotSerialized)
                {
                    Sleep (0xC8)
                    If (ABPS (Zero))
                    {
                        If (LNot (PRDS (Zero)))
                        {
                            Store (One, LDIS)
                            PWSL (Zero)
                            PWCM (0x03)
                            If (LEqual (MSSC (Zero), MRLS))
                            {
                                ATCM (0x02)
                            }
                            Else
                            {
                                ATCM (0x03)
                            }

                            ABPS (One)
                            Sleep (0xC8)
                            Return (0xFF)
                        }

                        Store (Zero, ABIE)
                        ABPS (One)
                        Sleep (0xC8)
                        If (PWCC ())
                        {
                            ATCM (0x02)
                            Sleep (0x0258)
                            Store (0x0258, Local0)
                            ABPS (One)
                            While (LNot (ABPS (Zero)))
                            {
                                Sleep (0xC8)
                                Add (Local0, 0xC8, Local0)
                                If (LEqual (0x1388, Local0))
                                {
                                    Store (One, ABIE)
                                    ATCM (0x03)
                                    PWCM (0x02)
                                    Sleep (0x0258)
                                    Store (Zero, LDIS)
                                    PWSL (One)
                                    Sleep (0x01F4)
                                    If (LNot (PFDS (Zero)))
                                    {
                                        PWCM (One)
                                        Store (Zero, Local1)
                                        Store (One, ABIE)
                                    }
                                    Else
                                    {
                                        PWSL (Zero)
                                        PWCM (0x03)
                                        ATCM (One)
                                        Store (One, LDIS)
                                        Store (0x03, Local1)
                                        Store (One, ABIE)
                                    }

                                    ABPS (One)
                                    Sleep (0xC8)
                                    Return (Local1)
                                }
                            }

                            Return (0xFF)
                        }
                        Else
                        {
                            ATCM (0x02)
                            Sleep (0x0258)
                            Store (0x0258, Local0)
                            ABPS (One)
                            Sleep (0xC8)
                            While (LNot (ABPS (Zero)))
                            {
                                Sleep (0xC8)
                                Add (Local0, 0xC8, Local0)
                                If (LEqual (0x1388, Local0))
                                {
                                    ABPS (One)
                                    ATCM (0x03)
                                    PWCM (0x02)
                                    Sleep (0xC8)
                                    Store (One, ABIE)
                                    Store (One, LDIS)
                                    PWCM (0x03)
                                    Return (0x03)
                                }
                            }

                            PWCM (One)
                            ABPS (One)
                            Sleep (0xC8)
                            Store (One, ABIE)
                            Return (0xFF)
                        }
                    }

                    If (PFDS (Zero))
                    {
                        PFDS (One)
                        PWSL (Zero)
                        PWCM (0x03)
                        ATCM (One)
                        Store (One, LDIS)
                        Return (0x03)
                    }

                    If (PDCS (Zero))
                    {
                        PDCS (One)
                        If (LNot (PRDS (Zero)))
                        {
                            PWSL (Zero)
                            PWCM (0x03)
                            If (LEqual (MSSC (Zero), MRLS))
                            {
                                ATCM (0x02)
                            }
                            Else
                            {
                                ATCM (0x03)
                            }

                            Store (One, LDIS)
                            Return (0xFF)
                        }
                        Else
                        {
                            Store (Zero, LDIS)
                            ABPS (One)
                            Sleep (0xC8)
                            Store (One, ABIE)
                            Sleep (0xC8)
                            Return (Local1)
                        }
                    }

                    Return (0xFF)
                }

                Method (SNUM, 0, Serialized)
                {
                    Store (PSNM, Local0)
                    Return (Local0)
                }

                Device (UPSB)
                {
                    Name (_ADR, Zero)  // _ADR: Address
                    Device (DSB0)
                    {
                        Name (_ADR, Zero)  // _ADR: Address
                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            If (LEqual (Arg2, Zero))
                            {
                                Return (Buffer (One)
                                {
                                     0x03                                           
                                })
                            }

                            Return (Package (0x02)
                            {
                                "PCIHotplugCapable", 
                                Zero
                            })
                        }

                        Device (NHI0)
                        {
                            Name (_ADR, Zero)  // _ADR: Address
                            Name (_STR, Unicode ("Thunderbolt"))  // _STR: Description String
                            Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                            {
                                If (LEqual (Arg2, Zero))
                                {
                                    Return (Buffer (One)
                                    {
                                         0x03                                           
                                    })
                                }

                                Return (Package (0x08)
                                {
                                    "AAPL,slot-name", 
                                    "Built In", 
                                    "name", 
                                    "Thunderbolt 3 Controller", 
                                    "device_type", 
                                    Buffer (0x0E)
                                    {
                                        "Thunderbolt 3"
                                    }, 

                                    "model", 
                                    Buffer (0x27)
                                    {
                                        "Thunderbolt 3 NHI Alpine Ridge 4C 2015"
                                    }
                                })
                            }
                        }
                    }

                    Device (DSB1)
                    {
                        Name (_ADR, 0x00010000)  // _ADR: Address
                        Device (UPS0)
                        {
                            Name (_ADR, Zero)  // _ADR: Address
                        }
                    }

                    Device (DSB2)
                    {
                        Name (_ADR, 0x00020000)  // _ADR: Address
                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            If (LEqual (Arg2, Zero))
                            {
                                Return (Buffer (One)
                                {
                                     0x03                                           
                                })
                            }

                            Return (Package (0x02)
                            {
                                "PCIHotplugCapable", 
                                Zero
                            })
                        }

                        Device (XHC2)
                        {
                            Name (_ADR, Zero)  // _ADR: Address
                            Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                            {
                                If (LEqual (Arg2, Zero))
                                {
                                    Return (Buffer (One)
                                    {
                                         0x03                                           
                                    })
                                }

                                Return (Package (0x0E)
                                {
                                    "AAPL,slot-name", 
                                    "Built In", 
                                    "name", 
                                    "USB 3.1 Controller", 
                                    "device_type", 
                                    Buffer (0x13)
                                    {
                                        "USB 3.1 Controller"
                                    }, 

                                    "model", 
                                    Buffer (0x35)
                                    {
                                        "Intel Corporation, USB 3.1 Controller [Alpine Ridge]"
                                    }, 

                                    "USBBusNumber", 
                                    Zero, 
                                    "AAPL,xhci-clock-id", 
                                    One, 
                                    "UsbCompanionControllerPresent", 
                                    One
                                })
                            }
                        }
                    }

                    Device (DSB4)
                    {
                        Name (_ADR, 0x00040000)  // _ADR: Address
                        Device (UPS0)
                        {
                            Name (_ADR, Zero)  // _ADR: Address
                        }
                    }
                }

                Device (H001)
                {
                    Name (_ADR, One)  // _ADR: Address
                    Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number
                    {
                        Return (SNUM ())
                    }
                }

                Device (H002)
                {
                    Name (_ADR, 0x02)  // _ADR: Address
                    Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number
                    {
                        Return (SNUM ())
                    }
                }

                Device (H003)
                {
                    Name (_ADR, 0x03)  // _ADR: Address
                    Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number
                    {
                        Return (SNUM ())
                    }
                }

                Device (H004)
                {
                    Name (_ADR, 0x04)  // _ADR: Address
                    Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number
                    {
                        Return (SNUM ())
                    }
                }

                Device (H005)
                {
                    Name (_ADR, 0x05)  // _ADR: Address
                    Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number
                    {
                        Return (SNUM ())
                    }
                }

                Device (H006)
                {
                    Name (_ADR, 0x06)  // _ADR: Address
                    Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number
                    {
                        Return (SNUM ())
                    }
                }

                Device (H007)
                {
                    Name (_ADR, 0x07)  // _ADR: Address
                    Method (_SUN, 0, NotSerialized)  // _SUN: Slot User Number
                    {
                        Return (SNUM ())
                    }
                }

                OperationRegion (PXCS, PCI_Config, Zero, 0xE0)
                Field (PXCS, AnyAcc, NoLock, Preserve)
                {
                    VDID,   32, 
                    Offset (0x54), 
                        ,   6, 
                    HPCE,   1, 
                    Offset (0x5A), 
                    ABPX,   1, 
                        ,   2, 
                    PDCX,   1, 
                        ,   2, 
                    PDSX,   1, 
                    Offset (0x5B), 
                    Offset (0x60), 
                    Offset (0x62), 
                    PMEX,   1, 
                    Offset (0xDC), 
                        ,   31, 
                    PMCS,   1
                }

                Method (DEVS, 0, NotSerialized)
                {
                    If (LEqual (VDID, 0xFFFFFFFF))
                    {
                        Return (Zero)
                    }
                    Else
                    {
                        Return (0x0F)
                    }
                }

                Method (HPME, 0, Serialized)
                {
                    If (PMEX)
                    {
                        Store (0xC8, Local0)
                        While (Local0)
                        {
                            Store (One, PMEX)
                            If (PMEX)
                            {
                                Decrement (Local0)
                            }
                            Else
                            {
                                Store (Zero, Local0)
                            }
                        }

                        Store (One, PMCS)
                    }
                }

                Method (_PRW, 0, NotSerialized)  // _PRW: Power Resources for Wake
                {
                    Return (GPRW (0x09, 0x04))
                }

                Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
                {
                    If (PICM)
                    {
                        Return (AG22)
                    }

                    Return (PG22)
                }

                Device (D07C)
                {
                    Name (_ADR, 0xFFFF)  // _ADR: Address
                }
            }

These DSDT code snippets roughly contain the entire TB ACPI definition.. 

 

Some difference with SSDT-9.aml are the actual _GPE and method _INI implementation of BR1A , which however seem to be also part of there original Asus X99 Deluxe II DSDT.aml, while the respective iMac Pro SSDT-9.aml implementations 

 

            Scope (\_GPE)
            {
                Method (_L32, 0, NotSerialized)  // _Lxx: Level-Triggered GPE
                {
                    If (LNot (OSDW ()))
                    {
                        If (LEqual (\_SB.PC01.BR1A.POC0, One))
                        {
                            Return (Zero)
                        }

                        Sleep (0x0190)
                        If (LEqual (\_SB.PC01.BR1A.WTLT (), One))
                        {
                            \_SB.PC01.BR1A.ICMS ()
                        }
                        Else
                        {
                        }

                        If (\_SB.PC01.BR1A.UPMB)
                        {
                            Store (Zero, \_SB.PC01.BR1A.UPMB)
                            Sleep (One)
                        }
                        Else
                        {
                        }

                        \_SB.PC01.BR1A.CMPE ()
                    }
                    ElseIf (LEqual (\_SB.GGII (0x01030012), One))
                    {
                        \_SB.SGII (0x01030012, Zero)
                    }
                    Else
                    {
                        \_SB.SGII (0x01030012, One)
                    }

                    \_SB.PC01.BR1A.UPSB.AMPE ()
                    Return (Zero)
                }

                Return (One)
            }

            Name (EICM, Zero)
            Name (R020, Zero)
            Name (R024, Zero)
            Name (R028, Zero)
            Name (R02C, Zero)
            Name (R118, Zero)
            Name (R119, Zero)
            Name (R11A, Zero)
            Name (R11C, Zero)
            Name (R120, Zero)
            Name (R124, Zero)
            Name (R128, Zero)
            Name (R12C, Zero)
            Name (R218, Zero)
            Name (R219, Zero)
            Name (R21A, Zero)
            Name (R21C, Zero)
            Name (R220, Zero)
            Name (R224, Zero)
            Name (R228, Zero)
            Name (R22C, Zero)
            Name (R318, Zero)
            Name (R319, Zero)
            Name (R31A, Zero)
            Name (R31C, Zero)
            Name (R320, Zero)
            Name (R324, Zero)
            Name (R328, Zero)
            Name (R32C, Zero)
            Name (R418, Zero)
            Name (R419, Zero)
            Name (R41A, Zero)
            Name (R41C, Zero)
            Name (R420, Zero)
            Name (R424, Zero)
            Name (R428, Zero)
            Name (R42C, Zero)
            Name (RVES, Zero)
            Name (R518, Zero)
            Name (R519, Zero)
            Name (R51A, Zero)
            Name (R51C, Zero)
            Name (R520, Zero)
            Name (R524, Zero)
            Name (R528, Zero)
            Name (R52C, Zero)
            Name (R618, Zero)
            Name (R619, Zero)
            Name (R61A, Zero)
            Name (R61C, Zero)
            Name (R620, Zero)
            Name (R624, Zero)
            Name (R628, Zero)
            Name (R62C, Zero)
            Name (RH10, Zero)
            Name (RH14, Zero)
            Name (POC0, Zero)

            OperationRegion (RSTR, SystemMemory, NHI1, 0x0100)
            Field (RSTR, DWordAcc, NoLock, Preserve)
            {
                CIOR,   32, 
                Offset (0xB8), 
                ISTA,   32, 
                Offset (0xF0), 
                ICME,   32
            }

            OperationRegion (T2PM, SystemMemory, T2P1, 0x08)
            Field (T2PM, DWordAcc, NoLock, Preserve)
            {
                T2PR,   32, 
                P2TR,   32
            }

            OperationRegion (RPSM, SystemMemory, 0x60510000, 0x54)
            Field (RPSM, DWordAcc, NoLock, Preserve)
            {
                RPVD,   32, 
                RPR4,   8, 
                Offset (0x18), 
                RP18,   8, 
                RP19,   8, 
                RP1A,   8, 
                Offset (0x1C), 
                RP1C,   16, 
                Offset (0x20), 
                R_20,   32, 
                R_24,   32, 
                R_28,   32, 
                R_2C,   32, 
                Offset (0x52), 
                    ,   11, 
                RPLT,   1, 
                Offset (0x54)
            }

            OperationRegion (UPSM, SystemMemory, TUP1, 0x0548)
            Field (UPSM, DWordAcc, NoLock, Preserve)
            {
                UPVD,   32, 
                UP04,   8, 
                Offset (0x08), 
                CLRD,   32, 
                Offset (0x18), 
                UP18,   8, 
                UP19,   8, 
                UP1A,   8, 
                Offset (0x1C), 
                UP1C,   16, 
                Offset (0x20), 
                UP20,   32, 
                UP24,   32, 
                UP28,   32, 
                UP2C,   32, 
                Offset (0xD2), 
                    ,   11, 
                UPLT,   1, 
                Offset (0xD4), 
                Offset (0x544), 
                UPMB,   1, 
                Offset (0x548)
            }

            OperationRegion (DNSM, SystemMemory, TDB1, 0xD4)
            Field (DNSM, DWordAcc, NoLock, Preserve)
            {
                DPVD,   32, 
                DP04,   8, 
                Offset (0x18), 
                DP18,   8, 
                DP19,   8, 
                DP1A,   8, 
                Offset (0x1C), 
                DP1C,   16, 
                Offset (0x20), 
                DP20,   32, 
                DP24,   32, 
                DP28,   32, 
                DP2C,   32, 
                Offset (0xD2), 
                    ,   11, 
                DPLT,   1, 
                Offset (0xD4)
            }

            OperationRegion (DS3M, SystemMemory, TD11, 0x40)
            Field (DS3M, DWordAcc, NoLock, Preserve)
            {
                D3VD,   32, 
                D304,   8, 
                Offset (0x18), 
                D318,   8, 
                D319,   8, 
                D31A,   8, 
                Offset (0x1C), 
                D31C,   16, 
                Offset (0x20), 
                D320,   32, 
                D324,   32, 
                D328,   32, 
                D32C,   32
            }

            OperationRegion (DS4M, SystemMemory, TD21, 0x0568)
            Field (DS4M, DWordAcc, NoLock, Preserve)
            {
                D4VD,   32, 
                D404,   8, 
                Offset (0x18), 
                D418,   8, 
                D419,   8, 
                D41A,   8, 
                Offset (0x1C), 
                D41C,   16, 
                Offset (0x20), 
                D420,   32, 
                D424,   32, 
                D428,   32, 
                D42C,   32, 
                Offset (0x564), 
                DVES,   32
            }

            OperationRegion (DS5M, SystemMemory, TD41, 0x40)
            Field (DS5M, DWordAcc, NoLock, Preserve)
            {
                D5VD,   32, 
                D504,   8, 
                Offset (0x18), 
                D518,   8, 
                D519,   8, 
                D51A,   8, 
                Offset (0x1C), 
                D51C,   16, 
                Offset (0x20), 
                D520,   32, 
                D524,   32, 
                D528,   32, 
                D52C,   32
            }

            OperationRegion (NHIM, SystemMemory, TNH1, 0x40)
            Field (NHIM, DWordAcc, NoLock, Preserve)
            {
                NH00,   32, 
                NH04,   8, 
                Offset (0x10), 
                NH10,   32, 
                NH14,   32
            }

            Method (_INI, 0, NotSerialized)  // _INI: Initialize
            {
                If (LNot (OSDW ()))
                {
                    Store (One, TBG2)
                    Store (R_20, R020)
                    Store (R_24, R024)
                    Store (R_28, R028)
                    Store (R_2C, R02C)
                    Store (UP18, R118)
                    Store (UP19, R119)
                    Store (UP1A, R11A)
                    Store (UP1C, R11C)
                    Store (UP20, R120)
                    Store (UP24, R124)
                    Store (UP28, R128)
                    Store (UP2C, R12C)
                    Store (DP18, R218)
                    Store (DP19, R219)
                    Store (DP1A, R21A)
                    Store (DP1C, R21C)
                    Store (DP20, R220)
                    Store (DP24, R224)
                    Store (DP28, R228)
                    Store (DP28, R228)
                    Store (D318, R318)
                    Store (D319, R319)
                    Store (D31A, R31A)
                    Store (D31C, R31C)
                    Store (D320, R320)
                    Store (D324, R324)
                    Store (D328, R328)
                    Store (D32C, R32C)
                    Store (D418, R418)
                    Store (D419, R419)
                    Store (D41A, R41A)
                    Store (D41C, R41C)
                    Store (D420, R420)
                    Store (D424, R424)
                    Store (D428, R428)
                    Store (D42C, R42C)
                    Store (DVES, RVES)
                    Store (D518, R518)
                    Store (D519, R519)
                    Store (D51A, R51A)
                    Store (D51C, R51C)
                    Store (D520, R520)
                    Store (D524, R524)
                    Store (D528, R528)
                    Store (D52C, R52C)
                    Store (NH10, RH10)
                    Store (NH14, RH14)
                    Sleep (One)
                    ICMB ()
                }
            }

etc.
etc. 

anyway fail on our Hackintosh systems.. Noticeable, that in the actual DSDT.aml,  UPSB is also part of the  the_GPE implementation. The remaining TB DSDT patches seem to consist of a simple DSB0 and DSB2 "PCIHotplugCapable" property injection and the usual ACPI TB device definitions. In my opinion, nothing that could result in the TB miracle observed above.. :rofl:

Edited by KGP-iMacPro

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Spoiler

 

 

 

Yes , yesterday night I compiled a SSDT with appropriate parts from this DSDT and no miracle...:cry:

 

( even with adjusting thunderbolt settings in bios) 

Edited by Loloflat6

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I also wanted to bring my experience because I currently have the hotplug working properly without using strange tricks.

Gigabyte recently released an BIOS update for the Z370 motherboard, which adds compatibility to the new 9th Gen processors.
I had read earlier that the Z390 chipset would bring greater compatibility with the Thunderbolt connection, and I think this BIOS update brought some of these changes.
In fact now, not only do I have new Thunderbolt settings in the BIOS, but the hotplug also works perfectly with the THB_C header connected!

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59 minutes ago, lelet said:

I also wanted to bring my experience because I currently have the hotplug working properly without using strange tricks.

Gigabyte recently released an BIOS update for the Z370 motherboard, which adds compatibility to the new 9th Gen processors.
I had read earlier that the Z390 chipset would bring greater compatibility with the Thunderbolt connection, and I think this BIOS update brought some of these changes.
In fact now, not only do I have new Thunderbolt settings in the BIOS, but the hotplug also works perfectly with the THB_C header connected!

 

I have sucessefully connected an USB C ethernet PCi on USB C TB EX3  and internet connection 10/100/1000 was right pass through in.

Edited by Loloflat6

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Hi Guys, 

 

I still think that this TB adapter is not working properly since I'm not able anymore to successfully transfer data on a TB connection between 2 devices as before (my 1st post here), but has got something configure/misconfigured that somehow triggers the full TB detection from OSX, which is what is very impressive!!

 

Also agree with KGP-iMacPro, that I don't have any special configuration or settings from before...

 

Anyway, some more testing that I did with this "miracle" Asus EX3 TB adapter:

 

Windows 10 64bits:

On a fresh install, with latest ASUS drivers ver 17.3.74, the ASUS EX3 TB adapter is detected by windows but the ASUS TB SW doesn't detect any adapter (as per OSX) connected!

817407293_ThunderboltWindows1064bits.thumb.PNG.6274942303c19f99d182ac23aa633e67.PNG

 

Also, a new USB device (associated with this TB adapter) is detected but the windows driver halted from starting with error 42!

479389867_ThunderboltWindows1064bits1.thumb.PNG.a311796b8b7b43738ec721da694e2e62.PNG

 

MOJAVE:

The same full TB functionality detection is achieved on MOJAVE beta configured as an iMac Pro -  so it does not seem to be OSX version dependent!

 

976701000_Capturadeecr2018-09-21s08_18_42.png.c74ca5f053832b9abc8788d2be66abd9.png1401391057_Capturadeecr2018-09-18s08_08_01.thumb.png.a8ad8e106a056e7998045b0be64c018a.png

576820536_Capturadeecr2018-09-18s08_12_32.thumb.png.3ebcd9ebb798d64ca74e2383899bb26e.png

Apple TB 2 cable connectivity testing:

 

In order to verify if my Apple Thunderbolt 2m cable (MD861ZM/A) is still functional, I've used 2 x MacBooPro's (2015 & 2016 models), with one of them with Windows 10 64bits (bootcamp) through this cable and I can transfers files at a blazing 20GB/s speed between the 2 x MBPs!

425418901_ThunderboltCablebetween2xMBPretina15.thumb.png.a30f4861c7e0eb35b19d8b0a2d3f9949.png1913928987_ThunderboltCablebetween2xMBPretina15-2.thumb.png.697e51ad8c29ed43619e72f5e23b41d9.png

 

CONCLUSION:

If I can no longer connect 2 devices via TB connection using my Asus EX3 TB adapter, I'm going to check its warranty and request for a RMA or, maybe consider the next intel TB 3 card with chips set JHL 7xxx series (apparenty with latest MBP 2018) link:

 

Intel's Thunderbolt 3 Controllers
  DSL
6240
DSL
6340
DSL
6540
JHL
6340
JHL
6540
JHL
7340
JHL
7440
JHL
7540
Family Alpine Ridge Titan Ridge
Launch Date Q2 2016 Q3 2015 Q2 2016 Q1 2018
TDP 1.2 W 1.7 W 2.2 W 1.7 W 2.2 W ? ? ?
Number of Ports 1 2 1 2 1 2
DisplayPort 2x 1.2 2x 1.4
Package Size 10.7 × 10.7 mm ? ? ?
Price $6.45 $8.00 $8.55 $8.00 $8.55 ? ? ?

 

 

Anyway, please send me your testing scrips or apps for me to do further testing and help discover why my TB adapter is triggering OSX to fully detect the TB functionality, ok ?

Captura de ecrã 2018-09-18, às 08.13.53 1.png

Thunderbolt Cable between 2 x MBP retina 15 - 3.png

Thunderbolt Cable between 2 x MBP retina 15 - 4 1.png

Thunderbolt Cable between 2 x MBP retina 15 - 4.png

Edited by augustopaulo

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@augustopaulo, I rather think the opposite! 

 

This adaptor or your current configuration might be a unique opportunity to shed new light onto the entire TB Hackintosh story.. we just don't know yet why and in which way. The only thing I would like to ask you: please never return it to the manufacturer until we deeply investigated cause and effects of your recent discovery.. 

 

Generally I don't think that it is a good idea to mix things between Windows and macOS.. Don't forget that we are dealing with UEFI.. thus specific settings under some certain operating system might affect the adopters functionality in the other operating system. Me myself many times I even reached to a situation where the removal and replugging of the adopter was the only possibility to make the adopter work again under any system.

 

Also don't be scared that the adopter is not fully functional and reveals errors.. While we might miss some of your implementations and functionalities you might miss some of our implementations and functionalities.. The fusion and merge of our different implementations, results, discoveries, and experiences might lead to some breakthrough though.. We have to wait and see..   

 

Thus please, once more don't request any RMA for the adopter. It is a 50$ investment that could change many things! I rather encourage you to purchase a second adopter to see whether or not you would be able to replicate the same effects with an else unchanged system configuration.  

 

 

 

Edited by KGP-iMacPro

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3 minutes ago, KGP-iMacPro said:

@augustopaulo, I rather think the opposite! 

 

This adaptor or your current configuration might be a unique opportunity to shed new light onto the entire TB Hackintosh story.. we just don't know yet why and in which way. The only thing I would like to ask you: please never return it to the manufacturer until we deeply investigated cause and effects of your recent discovery.. 

 

Generally I don't think that it is a good idea to mix things between Windows and macOS.. Don't forget that we are dealing with UEFI.. thus specific settings under some certain operating system might affect the adopters functionality in the other operating system. Me myself many times I even reached to a situation where the removal and replugging of the adopter was the only possibility to make the adopter work again under any system.

 

Thus please, once more don't request any RMA for the adopter. It is a 50$ investment that could change many things! I rather encourage you to purchase a second adopter to see whether or not you would be able to replicate the same effects with an else unchanged system configuration.  

 

 

 

 

Hi KGP-iMacPro, 

 

Point well made.

 

I won't return it/RMA, I promise!

 

Now, tell me (& others) what do you want me to further test this Asus TB3 adapter, ok ?

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1 minute ago, augustopaulo said:

 

Hi KGP-iMacPro, 

 

Point well made.

 

I won't return it/RMA, I promise!

 

Now, tell me (& others) what do you want me to further test this Asus TB3 adapter, ok ?

 

let me think and come back to you with certain proposals.. :wink_anim: ideas and input of others of course also would be highly welcome at this place..

 

The most interesting test for now would be if you could replicate the same effects also with a second different adopter. This would limit the open variables and might shed light onto the open question if the miracle is really caused by the current, special adopter or rather by something else in your overall system configuration. 

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12 minutes ago, fabiosun said:

Have you connected tb header cable?

Rev 1.00 on your PCB card is visible?

Thank you

Yes, header cable always connected.

 

As for version, see if you can see it from the 2 photos I've taken.. (my son is using the PC for now) and don't look at the dust!!:blush:

 

But, later today I'll take it out an take proper pictures...

IMG_1284.JPG

IMG_1278.JPG

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Pictures are fine..it is rev 1.00 as mine

For testing purpose I will put one I have on my x299  rig , I have no thunderbolt header connection in my designare Ex...so maybe it is unesuful test

will see ;)

 

 

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GC-Titan Ridge 40GB/S Intel Thunderbolt 3 Certified Add-in Card fully functional under macOS! 

 

GC-Titan Ridge working OoB under macOS 10.14 Mojave with SSDT-X299-TB3HP-TTR.aml and SSDT-X99-TB3HP-TTR.aml :superman:

 

307242-00f6ad24ada8fb002882c54b48853b4a.jpg.d78a3f367a85580f009157b4f522c78f.jpg

 

GC-Titan Ridge Features: 

2x PCIe 6pin power connectors
1x USB2.0 Header Cable
1x THB_C Header Cable

2x mini-DP 1.4 input
2x TB3 out
1x DP 1.4 out

 

GC-Titan Ridge macOS Implementation:

897843326_Screenshot2018-09-24at15_35_06.thumb.png.df12ec41e0f790acaa09c14a52c32d1a.png

 

 

424265117_Screenshot2018-09-24at15_34_42.thumb.png.74d60c0eb7abe84b1d8038560577dc9d.png

 

 

Gorgeous! :plane:

 

Enjoy and have fun :thumbsup_anim:

 

kgp.png.ad2fba50ebe15d0a53b891b8490ad277.png

 

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