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ATI Radeon unsupported cards debugging


jalavoui
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This must be the worst graphic card ever made http://www.notebookcheck.net/AMD-Radeon-R2-Mullins-Beema.115402.0.html

 

Anyway atm i got this...

 

9852.jpg

 

 

This is just a small step in making it full usuable. Current stage loads framebuffer only.

 

Tested on ATI 0x9852 - os x 10.11.4

 

 

Howto use

 

- Download latest attach

- Get your card bios rom file.

- Open and paste in ATY,bin_image in AMD8000Controller.kext plist file.

- Care if you're changing aty_config parameters.

- reboot and cross fingers.

 

 

V02 fixes

- no need to edit framebuffer/connectors in kext/clover/dsdt - they will be auto assigned from bios table.

- removed patch from 7000. added info.plist from 8000

- out of sync when using a 2nd screen can be fixed using the attached s.zip script + fixedid (move edid folder to s/l/displays)

 

 

 

 

Developper notes

 

- Debug tool from http://www.insanelymac.com/forum/topic/312254-realtek-ethernet-panic-debug-driver-using-xcode-ui/

- i've just compiled DisableMonitor.app from github - maybe usefull for some1

v01.zip

v02.zip

DisableMonitor.zip

atomdis.zip

s.zip

FixEDID.zip

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  • 1 month later...

Update for Mac OS X Siera 10.12.5

 

Sierra added legacy support.kext

 

edit AMDLegacySupport.kext info.plist with your card for legacy framebuffer or use AMDSupport.kext if it fails

 

 

debug functions for framebuffer/controller start

ATIController::start

PP_Initialize_internal
AtiAtomBiosDceInterface::parseHotPlugId:
AtiAtomBiosUtilities::getGpioPinLutInfo(unsigned char)
AtiAtomBiosDceInterface::populateConnectorInfo
CIDisplayEngineClock::GetDPRefClkFrequency
parseSenseId
CIDpAudioConnection::init
reorderConnectorBuffer

acceleration functions

this is my lldbinit file atm

settings set target.load-script-from-symbol-file true
settings set target.process.thread.step-out-avoid-nodebug true
settings set target.process.detach-keeps-stopped true
settings set plugin.process.kdp-remote.packet-timeout 30
kdp-remote 192.168.2.4
showlldbtypesummaries
command script import /sim/trace.py
target modules add /sim/1
target modules add /sim/2
target modules add /sim/3
target modules add /sim/4
target modules add /sim/5
target modules add /sim/6
target modules add /sim/7
target modules add /sim/8
target modules add /sim/9
target modules add /sim/10
b ATIController::start
b AMDRadeonX4000_AMDGraphicsAccelerator::start
b IOGraphicsAccelerator2::start
b AMDRadeonX4000_AMDAccelDisplayMachine::init
b PP_Initialize_internal
b CAILEarlyASICInit
b AMDBonaireHardware::powerUp
b Cail_MCILWaitForIsGfxHung
b Bonaire_LoadUcode
b get_asic_caps_set_from_table
b CopyDDI_CAPS
b PHM_Initialize
b findDeviceAsicCaps
b PECI_SetupInitInfo
b createPCIDeviceList

traced ucode sample (for 0x9852) 

 

#9 rlc

#114 ce
#217 pfp
#179 me
#76 sdma

 

 

kextwait en0 helper

 

modify the info.plist (see attach) to load this kext after en0 is plugged to a router

the 30sec delay will help avoid invalid IP address on debug start and

will make the debugger stop on a start function (works on amd/intel drivers)

 

 

AMDLegacySupport.kext.zip

AMDSupport.kext.zip

Info.plist.zip

kextwait.kext.zip

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  • 1 month later...

i would like to figure out why i get wrong bios reading - i'm shure must be some memory address mapping. check this code from amd8000controller:

            }
          }
        }
      }
    }
  }
  else
  {
    v9 = -536870211;
  }
  return (unsigned int)v9;
}

probably this canbe fixed for any card.how? idk

 

 

all cards need tobe assigned special functions in order to work. code is here (from AMDRadeonX4000.kext)

LABEL_23:
  result = CailCapsEnabled(v1, 328LL);
  if ( result )
  {
    Cail_Greenland_InitFunctionPointer(a1, 328LL);
    result = CailCapsEnabled(v1, 83LL);
    if ( result )
      result = Cail_Raven_InitFunctionPointer(a1, 83LL);
  }
  return result;
}

small changes might help. on a bogus card like the1 i have i get a wrong family id of 120 (should be 125. where can this be fixed? check next function

signed __int64 __fastcall get_asic_caps_set_from_table(__int64 a1, __int64 a2, int a3)
{
  __int64 v3; // r13@1
  __int64 v4; // rcx@1
  signed __int64 result; // rax@1
  __int64 v6; // r9@2
  __int64 v7; // r8@2
  char *v8; // rbx@2
  signed int v9; // er14@2
  signed int v10; // er12@2
  unsigned int v11; // er11@2
  __int64 v12; // rcx@4
  signed int v13; // esi@8
  unsigned __int64 v14; // rsi@9
  signed __int64 v15; // r12@18
  __int64 v16; // rcx@19
  __int64 v17; // rbx@22
  int v18; // eax@22
  __int64 *v19; // rax@24
  __int64 v20; // rax@26
  __int64 *v21; // rax@28
  __int64 v22; // r14@28
  int v23; // eax@29
  int v24; // ecx@31
  unsigned int v25; // esi@32
  char *v26; // rdx@32
  bool v27; // cl@35
  int v28; // ecx@37
  int v29; // ecx@41
  unsigned int v30; // ecx@43
  int v31; // edi@43

  v3 = a2;
  v4 = CAILAsicCapsInitTable[1];
  result = 5LL;
  if ( v4 == 0xFFFFFFFFLL )
    return result;
  v6 = *(_DWORD *)(a2 + 4);
  v7 = *(_DWORD *)(a2 + 28);
  v8 = (char *)&CAILAsicCapsInitTable[2];
  v9 = -1;
  v10 = 0;
  v11 = 0;
  while ( 1 )
  {
    if ( v4 == v6 )
    {
      v12 = *((_QWORD *)v8 + 2);
      if ( v12 == 0xFFFFFFFFLL || a3 || v12 == *(_DWORD *)(v3 + 16) )
        break;
    }
LABEL_14:
    ++v10;
    v4 = *((_QWORD *)v8 + 6);
    v8 += 56;
    v13 = v9;
    if ( v4 == 0xFFFFFFFFLL )
      goto LABEL_17;
  }
  if ( !a3 )
  {
    v13 = v10;
    if ( *(_QWORD *)v8 == v7 )
      goto LABEL_17;
    v14 = *((_QWORD *)v8 + 1);
    if ( v11 < v14 )
      v9 = v10;
    if ( v11 >= v14 )
      LODWORD(v14) = v11;
    v11 = v14;
    goto LABEL_14;
  }
  v13 = v10;
LABEL_17:
  if ( v13 != -1 )
  {
    v15 = 7LL * v13;
    if ( CAILAsicCapsInitTable[v15 + 1] == *(_DWORD *)(v3 + 4) )
    {
      v16 = CAILAsicCapsInitTable[v15 + 4];
      if ( v16 == 0xFFFFFFFFLL || a3 || v16 == *(_DWORD *)(v3 + 16) )
      {
        v17 = *(_QWORD *)CAILAsicCapsInitTable[v15 + 6];
        *(_QWORD *)(v3 + 456) = &CAILAsicCapsInitTable[v15];
        *(_DWORD *)(v3 + 24) = CAILAsicCapsInitTable[v15];
        v18 = CAILAsicCapsInitTable[v15 + 3];
        *(_DWORD *)(v3 + 32) = v18;
        *(_DWORD *)(v3 + 36) = v18;
        Cail_Detect_Grenada(a1);
        if ( *(_DWORD *)v17 >= 3u )
        {
          if ( *(_DWORD *)v17 >= 5u )
          {
            v19 = *(__int64 **)(v17 + 48);
            if ( v19 || (v19 = *(__int64 **)(CAILAsicCapsInitTable[v15 + 6] + 16LL)) != 0LL )
            {
              v20 = *v19;
              goto LABEL_28;
            }
            goto LABEL_30;
          }
          v20 = *(_QWORD *)(v17 + 48);
          if ( !v20 )
            goto LABEL_30;
LABEL_28:
          v21 = (__int64 *)(v20 + 8);
          v22 = *v21;
          if ( *v21 )
          {
            v23 = GetStringLength(*v21);
            *(_DWORD *)(v3 + 1204) = StringToUlong(v22, (unsigned int)v23);
          }
          else
          {
LABEL_30:
            *(_DWORD *)(v3 + 1204) = 0;
          }
        }
        MemoryCopy(v3 + 464, CAILAsicCapsInitTable[v15 + 5], 64LL);
        LOWORD(v24) = CAILAsicCapsExceptionTable[0];
        result = 0LL;
        if ( CAILAsicCapsExceptionTable[0] != 0xFFFF )
        {
          v25 = *(_WORD *)(v3 + 4);
          v26 = (char *)&CAILAsicCapsExceptionTable[5];
          do
          {
            if ( (unsigned __int16)v24 > v25 )
              break;
            if ( (unsigned __int16)v24 == v25 )
            {
              v27 = (unsigned __int8)*(v26 - 6) == *(_BYTE *)(v3 + 16) || (unsigned __int8)*(v26 - 6) == 255;
              if ( *(v26 - 4) )
              {
                if ( v27 )
                {
                  v28 = *((_WORD *)v26 - 4);
                  if ( v28 == 0xFFFF || v28 == *(_DWORD *)(v3 + 8) )
                    *(_DWORD *)(v3 + 4LL * ((unsigned int)*((_WORD *)v26 - 1) >> 5) + 464) |= 1 << *((_WORD *)v26 - 1);
                }
              }
              else if ( v27 )
              {
                v29 = *((_WORD *)v26 - 4);
                if ( v29 == 0xFFFF || v29 == *(_DWORD *)(v3 + 8) )
                {
                  v30 = *((_WORD *)v26 - 1);
                  v31 = __ROL4__(-2, v30);
                  *(_DWORD *)(v3 + 4LL * (v30 >> 5) + 464) &= v31;
                }
              }
            }
            v24 = *(_WORD *)v26;
            v26 += 10;
          }
          while ( v24 != 0xFFFF );
        }
      }
    }
  }
  return result;
}

this is also valid for the 8000controller.kext - check here

__int64 __fastcall findDeviceAsicCaps(__int64 a1)
{
  unsigned int i; // [sp+4h] [bp-14h]@1
  char v3; // [sp+17h] [bp-1h]@9

  for ( i = 0; i < 0x9C; ++i )
  {
    if ( *((_DWORD *)&CAIL_ASIC_CAPS_TABLE + 8 * (signed int)i) == *(_DWORD *)(a1 + 24)
      && *((_DWORD *)&CAIL_ASIC_CAPS_TABLE + 8 * (signed int)i + 1) == *(_DWORD *)(a1 + 16)
      && *((_DWORD *)&CAIL_ASIC_CAPS_TABLE + 8 * (signed int)i + 3) == *(_DWORD *)(a1 + 28)
      && *((_DWORD *)&CAIL_ASIC_CAPS_TABLE + 8 * (signed int)i + 2) == *(_DWORD *)(a1 + 20)
      && (*((_DWORD *)&CAIL_ASIC_CAPS_TABLE + 8 * (signed int)i + 4) == *(_BYTE *)(a1 + 35)
       || -1 == *((_DWORD *)&CAIL_ASIC_CAPS_TABLE + 8 * (signed int)i + 4)) )
    {
      *(_QWORD *)(a1 + 40) = *((_QWORD *)&CAIL_ASIC_CAPS_TABLE + 4 * (signed int)i + 3);
      v3 = 1;
      return v3 & 1;
    }
  }
  v3 = 0;
  return v3 & 1;
}

some fixes can bemade in order to get the right card family.etc.

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  • 4 months later...

The Amdsupport patch doesn't fix hotplugsid - this makes multiple screens detection fails.

 

setting CFG_NO_HDCP to off does fix this. (on 1st multiscreen detection you might need to use the sleep trick).

 

in attach the info.plist I'm using on 8000controller

notice the ATY,bin_image is also added (delete or replace for your card)

 

other parameters will depend on which controller u're using so change with care.

 

this works fine on 10.12 but not so good for 10.11

 

if edid detection fails just use the fixedid tool posted above.

 

Info.plist.zip

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  • 1 year later...
  • 7 months later...
  • 9 months later...

using kextutil -s /sim -l "kext" you can create debug symbols to load into ldb or xcode

 

sample list from /sim folder:

 

com.apple.AppleGraphicsDeviceControl.sym
com.apple.driver.AppleMobileFileIntegrity.sym
com.apple.iokit.IOACPIFamily.sym
com.apple.iokit.IOAcceleratorFamily2.sym
com.apple.iokit.IOGraphicsFamily.sym
com.apple.iokit.IOPCIFamily.sym
com.apple.iokit.IOReportFamily.sym
com.apple.iokit.IOSurface.sym
com.apple.kec.corecrypto.sym
com.apple.kext.AMD8000Controller.sym
com.apple.kext.AMDFramebuffer.sym
com.apple.kext.AMDRadeonX4000.sym
com.apple.kext.AMDRadeonX4000HWServices.sym
com.apple.kext.AMDRadeonX4050HWLibs.sym
com.apple.kext.AMDSupport.sym
com.apple.kext.CoreTrust.sym

this helps a lot if you are debugging with diferrent os x versions

 

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AMDRadeonX4000_AMDHardware::setupCAIL

 

memset((char *)this + 1488, 0, 0x20000uLL);
  v2 = (*(__int64 (__fastcall **)(_QWORD, const char *))(**((_QWORD **)this + 2) + 696LL))(
         *((_QWORD *)this + 2),
         "ATY,bin_image");
  if ( v2 )
  {
    v1 = (const void *)(*(__int64 (__fastcall **)(__int64))(*(_QWORD *)v2 + 376LL))(v2);
    if ( v1 )
    {
      if ( (*(unsigned int (__fastcall **)(__int64))(*(_QWORD *)v2 + 320LL))(v2) == 0x10000 )
      {
        memcpy((char *)this + 1488, v1, 0x10000uLL);
        v3 = IOMalloc(760LL, v1);
        *((_QWORD *)this + 184) = v3;
        if ( !(unsigned int)AMDRadeonX4000_AMDHardware::MCIL_Initialize(v3) )
        {
          *(_QWORD *)(*((_QWORD *)this + 184) + 8LL) = this;
          LOBYTE(v1) = (*(unsigned int (**)(void))(**((_QWORD **)this + 87) + 16LL))() == 0;
          return (unsigned int)v1;
        }
      }
    }
    goto LABEL_6;
  }

this code validates the bios ATY,bin_image to  0x10000 ( 65536 bytes) 

this means the bios as to be filled with "FF" (use a hex editor)

found this on 10.14 - it causes the driver to fail on config stage and on loading

note that 0x10000 is the bios legacy size

 

on the hardware libs theres also a validation

 

AmdCailServices::earlyInitialize

memset((void *)(a1 + 21), 0, (size_t)&loc_20000);
      v5 = (*(__int64 (__fastcall **)(_QWORD, const char *))(**(_QWORD **)(a1 + 8) + 696LL))(
             *(_QWORD *)(a1 + 8),
             "ATY,bin_image");
      if ( !v5 )
      {
        kprintf("AMD Error: ");
        kprintf("Unable to find ROM image\n");
        return (unsigned int)-536870212;
      }
      v6 = (const void *)(*(__int64 (__fastcall **)(__int64))(*(_QWORD *)v5 + 376LL))(v5);
      if ( (*(unsigned int (__fastcall **)(__int64))(*(_QWORD *)v5 + 320LL))(v5) > 0x1FFFF )
        v7 = (size_t)&loc_20000;
      else
        v7 = (*(unsigned int (__fastcall **)(__int64))(*(_QWORD *)v5 + 320LL))(v5);
      v9 = a1 + 21;
      v10 = v6;
      memmove((void *)(v3 + 21), v6, v7);

 

loc_20000 = 0x20000 (131072 bytes)

 

 

Edited by jalavoui
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  • 1 year later...

I'm debugging the x6000 framebuffer and like to share this finding (from linux)

 

on Mac OS X we have this 

 

void _dal_bios_parser_init_cmd_tbl(long param_1)

{
  char cVar1;
  byte bVar2;
  code *pcVar3;
  undefined *puVar4;
  code *pcVar5;
  code *pcVar6;
  undefined local_2a;
  byte local_29;
  
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs(*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),4);
  if (cVar1 == '\0') {
    local_29 = 0;
  }
  if (local_29 == 2) {
    pcVar3 = _encoder_control_digx_v3;
  }
  else if (local_29 == 5) {
    pcVar3 = _encoder_control_digx_v5;
  }
  else if (local_29 == 4) {
    pcVar3 = _encoder_control_digx_v4;
  }
  else {
    pcVar5 = (code *)0x0;
    local_2a = 0;
    local_29 = 0;
    cVar1 = _cgs_atom_get_cmd_table_revs
                      (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x4a,&local_2a,&local_29);
    pcVar3 = _encoder_control_dig1_v1;
    if (local_29 != 1) {
      pcVar3 = pcVar5;
    }
    if (cVar1 == '\0') {
      pcVar3 = pcVar5;
    }
    *(code **)(param_1 + 0xe8) = pcVar3;
    local_2a = 0;
    local_29 = 0;
    cVar1 = _cgs_atom_get_cmd_table_revs
                      (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x4b,&local_2a,&local_29);
    pcVar3 = _encoder_control_dig2_v1;
    if (local_29 != 1) {
      pcVar3 = pcVar5;
    }
    if (cVar1 == '\0') {
      pcVar3 = pcVar5;
    }
    *(code **)(param_1 + 0xf0) = pcVar3;
    pcVar3 = _encoder_control_dig_v1;
  }
  *(code **)(param_1 + 0xe0) = pcVar3;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs(*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x4c);
  if (cVar1 == '\0') {
    _kprintf("%s:%u BREAK_TO_DEBUGGER point !!!.\n","init_transmitter_control",0x19a);
  }
  if ((byte)(local_29 - 2) < 5) {
    puVar4 = (&PTR__transmitter_control_v2_002a4648)[(char)(local_29 - 2)];
  }
  else {
    puVar4 = (undefined *)0x0;
  }
  *(undefined **)(param_1 + 0xf8) = puVar4;
  puVar4 = (undefined *)0x0;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs(*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0xc);
  bVar2 = 0xfd;
  if (cVar1 != '\0') {
    bVar2 = local_29 - 3;
  }
  if (bVar2 < 5) {
    puVar4 = (&PTR__set_pixel_clock_v3_002a4670)[(char)bVar2];
  }
  *(undefined **)(param_1 + 0x100) = puVar4;
  pcVar3 = (code *)0x0;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs(*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x41);
  bVar2 = 0xff;
  if (cVar1 != '\0') {
    bVar2 = local_29 - 1;
  }
  if (bVar2 < 3) {
    puVar4 = (&PTR__enable_spread_spectrum_on_ppll_v1_002a4698)[(char)bVar2];
  }
  else {
    puVar4 = (undefined *)0x0;
  }
  *(undefined **)(param_1 + 0x108) = puVar4;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x11,&local_2a);
  if (cVar1 == '\0') {
    local_29 = 0;
  }
  pcVar5 = _adjust_display_pll_v3;
  if (local_29 != 3) {
    pcVar5 = pcVar3;
  }
  pcVar6 = _adjust_display_pll_v2;
  if (local_29 != 2) {
    pcVar6 = pcVar5;
  }
  *(code **)(param_1 + 0x110) = pcVar6;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x18,&local_2a,&local_29);
  pcVar5 = _dac1_encoder_control_v1;
  if (local_29 != 1) {
    pcVar5 = pcVar3;
  }
  if (cVar1 == '\0') {
    pcVar5 = pcVar3;
  }
  *(code **)(param_1 + 0x118) = pcVar5;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x19,&local_2a,&local_29);
  pcVar5 = _dac2_encoder_control_v1;
  if (local_29 != 1) {
    pcVar5 = pcVar3;
  }
  if (cVar1 == '\0') {
    pcVar5 = pcVar3;
  }
  *(code **)(param_1 + 0x120) = pcVar5;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x44,&local_2a,&local_29);
  pcVar5 = _dac1_output_control_v1;
  if (local_29 != 1) {
    pcVar5 = pcVar3;
  }
  if (cVar1 == '\0') {
    pcVar5 = pcVar3;
  }
  *(code **)(param_1 + 0x128) = pcVar5;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x45,&local_2a,&local_29);
  pcVar5 = _dac2_output_control_v1;
  if (local_29 != 1) {
    pcVar5 = pcVar3;
  }
  if (cVar1 == '\0') {
    pcVar5 = pcVar3;
  }
  *(code **)(param_1 + 0x130) = pcVar5;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x31,&local_2a);
  if (cVar1 == '\0') {
    local_29 = 0;
  }
  if (local_29 < 3) {
    local_2a = 0;
    local_29 = 0;
    cVar1 = _cgs_atom_get_cmd_table_revs(*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x27);
    if ((cVar1 == '\0') || (local_29 != 1)) goto LAB_001bb539;
    pcVar3 = _set_crtc_timing_v1;
  }
  else {
    if (local_29 != 3) {
LAB_001bb539:
      *(undefined8 *)(param_1 + 0x138) = 0;
      goto LAB_001bb545;
    }
    pcVar3 = _set_crtc_using_dtd_timing_v3;
  }
  *(code **)(param_1 + 0x138) = pcVar3;
LAB_001bb545:
  pcVar5 = (code *)0x0;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x23,&local_2a,&local_29);
  pcVar3 = _enable_crtc_v1;
  if (local_29 != 1) {
    pcVar3 = pcVar5;
  }
  if (cVar1 == '\0') {
    pcVar3 = pcVar5;
  }
  *(code **)(param_1 + 0x140) = pcVar3;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),6,&local_2a,&local_29);
  pcVar3 = _enable_crtc_mem_req_v1;
  if (local_29 != 1) {
    pcVar3 = pcVar5;
  }
  if (cVar1 == '\0') {
    pcVar3 = pcVar5;
  }
  *(code **)(param_1 + 0x148) = pcVar3;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0xc,&local_2a);
  if (cVar1 == '\0') {
    local_29 = 0;
  }
  pcVar3 = _program_clock_v6;
  if (local_29 != 6) {
    pcVar3 = pcVar5;
  }
  pcVar6 = _program_clock_v5;
  if (local_29 != 5) {
    pcVar6 = pcVar3;
  }
  *(code **)(param_1 + 0x150) = pcVar6;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x32,&local_2a,&local_29);
  pcVar3 = _external_encoder_control_v3;
  if (local_29 != 3) {
    pcVar3 = pcVar5;
  }
  if (cVar1 == '\0') {
    pcVar3 = pcVar5;
  }
  *(code **)(param_1 + 0x158) = pcVar3;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0xd,&local_2a,&local_29);
  pcVar3 = _enable_disp_power_gating_v2_1;
  if (local_29 != 1) {
    pcVar3 = pcVar5;
  }
  if (cVar1 == '\0') {
    pcVar3 = pcVar5;
  }
  *(code **)(param_1 + 0x160) = pcVar3;
  local_2a = 0;
  local_29 = 0;
  cVar1 = _cgs_atom_get_cmd_table_revs
                    (*(undefined8 *)(*(long *)(param_1 + 0x20) + 0x18),0x2e,&local_2a,&local_29);
  pcVar3 = _set_dce_clock_v2_1;
  if (local_29 != 1) {
    pcVar3 = pcVar5;
  }
  if (cVar1 == '\0') {
    pcVar3 = pcVar5;
  }
  *(code **)(param_1 + 0x168) = pcVar3;
  return;
}

 

on linux I found the missing code:

 

static void init_transmitter_control(struct bios_parser *bp)
{
	uint8_t frev;
	uint8_t crev;

	if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
			frev, crev) == false)
		BREAK_TO_DEBUGGER();
	switch (crev) {
	case 2:
		bp->cmd_tbl.transmitter_control = transmitter_control_v2;
		break;
	case 3:
		bp->cmd_tbl.transmitter_control = transmitter_control_v3;
		break;
	case 4:
		bp->cmd_tbl.transmitter_control = transmitter_control_v4;
		break;
	case 5:
		bp->cmd_tbl.transmitter_control = transmitter_control_v1_5;
		break;
	case 6:
		bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
		break;
	default:
		dm_output_to_console("Don't have transmitter_control for v%d\n", crev);
		bp->cmd_tbl.transmitter_control = NULL;
		break;
	}
}

this means on x6000 frame we have PTR__transmitter_control_v2_002a4648 i.ie., allows only transmitter_control_v2 !!

this is just a sample others like PTR__set_pixel_clock_v3_002a4670 etc on x6000

the code is just limited to specific versions

this can be fixed cause the x6000 as code for transmitter_control_v15 up to v4

 

 

this is from linux boot log:

 

[    1.188658] [drm:amdgpu_dm_irq_init [amdgpu]] DM_IRQ
[    1.188910] [drm:dal_firmware_parser_init_cmd_tbl [amdgpu]] Don't have set_crtc_timing for v1
[    1.189148] [drm] DM_PPLIB: values for F clock
[    1.189149] [drm] DM_PPLIB:	 400000 in kHz, 3124 in mV
[    1.189150] [drm] DM_PPLIB:	 933000 in kHz, 3599 in mV
[    1.189151] [drm] DM_PPLIB:	 1200000 in kHz, 4399 in mV
[    1.189152] [drm] DM_PPLIB:	 1467000 in kHz, 4399 in mV
[    1.189153] [drm] DM_PPLIB: values for DCF clock
[    1.189154] [drm] DM_PPLIB:	 300000 in kHz, 3124 in mV
[    1.189155] [drm] DM_PPLIB:	 600000 in kHz, 3599 in mV
[    1.189155] [drm] DM_PPLIB:	 626000 in kHz, 4250 in mV
[    1.189156] [drm] DM_PPLIB:	 654000 in kHz, 4399 in mV
[    1.189740] [drm:create_links [amdgpu]] BIOS object table - number of connectors: 4
[    1.189961] [drm:create_links [amdgpu]] DC: create_links: connectors_num: physical:4, virtual:0
[    1.190180] [drm:create_links [amdgpu]] BIOS object table - printing link object info for connector number: 0, link_index: 0
[    1.190397] [drm:link_create [amdgpu]] BIOS object table - link_id: 12
[    1.190612] [drm:link_create [amdgpu]] BIOS object table - is_internal_display: 0
[    1.190840] [drm:link_create [amdgpu]] BIOS object table - hpd_gpio id: 3
[    1.191059] [drm:link_create [amdgpu]] BIOS object table - hpd_gpio en: 0
[    1.191274] [drm:link_create [amdgpu]] Connector[0] description:signal 4
[    1.191489] [drm:dal_ddc_service_create [amdgpu]] BIOS object table - i2c_line: 0
[    1.191702] [drm:dal_ddc_service_create [amdgpu]] BIOS object table - i2c_engine_id: 1
[    1.191916] [drm:link_create [amdgpu]] BIOS object table - DP_IS_USB_C: 0
[    1.192130] [drm:link_create [amdgpu]] BIOS object table - IS_DP2_CAPABLE: 0
[    1.192344] [drm:link_create [amdgpu]] BIOS object table - device_tag.acpi_device: 0
[    1.192557] [drm:link_create [amdgpu]] BIOS object table - device_tag.dev_id.device_type: 3
[    1.192771] [drm:link_create [amdgpu]] BIOS object table - device_tag.dev_id.enum_id: 2
[    1.192984] [drm:link_create [amdgpu]] BIOS object table - ddi_channel_mapping: 0x00E4
[    1.193198] [drm:link_create [amdgpu]] BIOS object table - chip_caps: 0
[    1.193428] [drm:link_create [amdgpu]] BIOS object table - dc_link_construct_legacy finished successfully.

on the x6000 I get blank connectors and the driver fails

 

found the code here

void _dal_bios_parser_create(undefined8 param_1,undefined4 param_2)

{
  long lVar1;
  
  lVar1 = _firmware_parser_create();
  if (lVar1 != 0) {
    return;
  }
  _bios_parser_create(param_1,param_2);
  return;
}

 

Edited by jalavoui
  • Like 2
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uint _resource_parse_asic_id(void)

{
  uint uVar1;
  undefined8 in_stack_00000008;
  int iStack000000000000000c;
  undefined8 in_stack_00000010;
  uint uStack0000000000000014;
  
  if (iStack000000000000000c < 0x87) {
    if (iStack000000000000000c == 0x78) {
      return 0;
    }
    if (iStack000000000000000c == 0x7d) {
      if (uStack0000000000000014 - 0x81 < 0x7e) {
        return 2;
      }
      if (uStack0000000000000014 - 0x85 < 0x1c) {
        return 2;
      }
      return 1;
    }
    if (iStack000000000000000c == 0x82) {
      if (uStack0000000000000014 - 0x14 < 0x14) {
        return 3;
      }
      if (uStack0000000000000014 - 0x3c < 0x14) {
        return 3;
      }
      uVar1 = 0xffffffff;
      if (uStack0000000000000014 - 0x5a < 10) {
        uVar1 = 5;
      }
      if (uStack0000000000000014 - 0x50 < 10) {
        uVar1 = 5;
      }
      if (uStack0000000000000014 - 100 < 10) {
        uVar1 = 5;
      }
      if (uStack0000000000000014 < 0x6e) {
        return uVar1;
      }
      return 6;
    }
switchD_000abb00_caseD_88:
    uVar1 = 0xffffffff;
  }
  else {
    switch(iStack000000000000000c) {
    case 0x87:
      uVar1 = 4;
      break;
    default:
      goto switchD_000abb00_caseD_88;
    case 0x8d:
      uVar1 = (uStack0000000000000014 - 0x28 < 0xd7) + 7;
      break;
    case 0x8e:
      if (0x5e < uStack0000000000000014 - 0x91) {
        return uStack0000000000000014 - 0x81 < 0x10 | 10;
      }
      return 0xd;
    case 0x8f:
      uVar1 = 0xf;
      if (9 < uStack0000000000000014 - 0x3c) {
        uVar1 = (uint)(uStack0000000000000014 - 0x28 < 0x14) * 2 + 0xc;
      }
    }
  }
  return uVar1;
}

china code translated to linux:

enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
{
	enum dce_version dc_version = DCE_VERSION_UNKNOWN;

	switch (asic_id.chip_family) {

#if defined(CONFIG_DRM_AMD_DC_SI)
	case FAMILY_SI:
		if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
		    ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
		    ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
			dc_version = DCE_VERSION_6_0;
		else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
			dc_version = DCE_VERSION_6_4;
		else
			dc_version = DCE_VERSION_6_1;
		break;
#endif
	case FAMILY_CI:
		dc_version = DCE_VERSION_8_0;
		break;
	case FAMILY_KV:
		if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
		    ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
		    ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
			dc_version = DCE_VERSION_8_3;
		else
			dc_version = DCE_VERSION_8_1;
		break;
	case FAMILY_CZ:
		dc_version = DCE_VERSION_11_0;
		break;

	case FAMILY_VI:
		if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
				ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
			dc_version = DCE_VERSION_10_0;
			break;
		}
		if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
				ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
				ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
			dc_version = DCE_VERSION_11_2;
		}
		if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
			dc_version = DCE_VERSION_11_22;
		break;
	case FAMILY_AI:
		if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
			dc_version = DCE_VERSION_12_1;
		else
			dc_version = DCE_VERSION_12_0;
		break;
	case FAMILY_RV:
		dc_version = DCN_VERSION_1_0;
		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_1_01;
		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_2_1;
		if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_2_1;
		break;

	case FAMILY_NV:
		dc_version = DCN_VERSION_2_0;
		if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {
			dc_version = DCN_VERSION_2_01;
			break;
		}
		if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_3_0;
		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_3_02;
		if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_3_03;
		break;

	case FAMILY_VGH:
		dc_version = DCN_VERSION_3_01;
		break;

	case FAMILY_YELLOW_CARP:
		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_3_1;
		break;
	case AMDGPU_FAMILY_GC_10_3_6:
		if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_3_15;
		break;
	case AMDGPU_FAMILY_GC_10_3_7:
		if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_3_16;
		break;
	case AMDGPU_FAMILY_GC_11_0_0:
		dc_version = DCN_VERSION_3_2;
		if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
			dc_version = DCN_VERSION_3_21;
		break;
	case AMDGPU_FAMILY_GC_11_0_1:
		dc_version = DCN_VERSION_3_14;
		break;
	default:
		dc_version = DCE_VERSION_UNKNOWN;
		break;
	}
	return dc_version;
}

much better now

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int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
{
	int r;

	switch (adev->asic_type) {
	case CHIP_VEGA10:
		vega10_reg_base_init(adev);
		adev->sdma.num_instances = 2;
		adev->gmc.num_umc = 4;
		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
		adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
		adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
		adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
		adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
		break;
	case CHIP_VEGA12:
		vega10_reg_base_init(adev);
		adev->sdma.num_instances = 2;
		adev->gmc.num_umc = 4;
		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
		adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
		adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
		adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
		adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
		break;
	case CHIP_RAVEN:
		vega10_reg_base_init(adev);
		adev->sdma.num_instances = 1;
		adev->vcn.num_vcn_inst = 1;
		adev->gmc.num_umc = 2;
		if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
			adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
			adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
			adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
			adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
			adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
			adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
			adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
			adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
			adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
			adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
			adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
			adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
			adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
			adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
			adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
		} else {
			adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
			adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
			adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
			adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
			adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
			adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
			adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
			adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
			adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
			adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
			adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
			adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
			adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
			adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
			adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
		}
		break;
	case CHIP_VEGA20:
		vega20_reg_base_init(adev);
		adev->sdma.num_instances = 2;
		adev->gmc.num_umc = 8;
		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
		adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
		adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
		adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
		adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
		adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
		adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
		break;
	case CHIP_ARCTURUS:
		arct_reg_base_init(adev);
		adev->sdma.num_instances = 8;
		adev->vcn.num_vcn_inst = 2;
		adev->gmc.num_umc = 8;
		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
		adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
		adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
		adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
		adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
		adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
		adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
		adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
		adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
		adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
		adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
		break;
	case CHIP_ALDEBARAN:
		aldebaran_reg_base_init(adev);
		adev->sdma.num_instances = 5;
		adev->vcn.num_vcn_inst = 2;
		adev->gmc.num_umc = 4;
		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
		adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
		adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
		adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
		adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
		adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
		adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
		adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
		adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
		break;
	default:
		r = amdgpu_discovery_reg_base_init(adev);
		if (r)
			return -EINVAL;

		amdgpu_discovery_harvest_ip(adev);
		amdgpu_discovery_get_gfx_info(adev);
		amdgpu_discovery_get_mall_info(adev);
		amdgpu_discovery_get_vcn_info(adev);
		break;
	}

	switch (adev->ip_versions[GC_HWIP][0]) {
	case IP_VERSION(9, 0, 1):
	case IP_VERSION(9, 2, 1):
	case IP_VERSION(9, 4, 0):
	case IP_VERSION(9, 4, 1):
	case IP_VERSION(9, 4, 2):
		adev->family = AMDGPU_FAMILY_AI;
		break;
	case IP_VERSION(9, 1, 0):
	case IP_VERSION(9, 2, 2):
	case IP_VERSION(9, 3, 0):
		adev->family = AMDGPU_FAMILY_RV;
		break;
	case IP_VERSION(10, 1, 10):
	case IP_VERSION(10, 1, 1):
	case IP_VERSION(10, 1, 2):
	case IP_VERSION(10, 1, 3):
	case IP_VERSION(10, 1, 4):
	case IP_VERSION(10, 3, 0):
	case IP_VERSION(10, 3, 2):
	case IP_VERSION(10, 3, 4):
	case IP_VERSION(10, 3, 5):
		adev->family = AMDGPU_FAMILY_NV;
		break;
	case IP_VERSION(10, 3, 1):
		adev->family = AMDGPU_FAMILY_VGH;
		break;
	case IP_VERSION(10, 3, 3):
		adev->family = AMDGPU_FAMILY_YC;
		break;
	case IP_VERSION(10, 3, 6):
		adev->family = AMDGPU_FAMILY_GC_10_3_6;
		break;
	case IP_VERSION(10, 3, 7):
		adev->family = AMDGPU_FAMILY_GC_10_3_7;
		break;
	case IP_VERSION(11, 0, 0):
	case IP_VERSION(11, 0, 2):
		adev->family = AMDGPU_FAMILY_GC_11_0_0;
		break;
	case IP_VERSION(11, 0, 1):
		adev->family = AMDGPU_FAMILY_GC_11_0_1;
		break;
	default:
		return -EINVAL;
	}

	switch (adev->ip_versions[GC_HWIP][0]) {
	case IP_VERSION(9, 1, 0):
	case IP_VERSION(9, 2, 2):
	case IP_VERSION(9, 3, 0):
	case IP_VERSION(10, 1, 3):
	case IP_VERSION(10, 1, 4):
	case IP_VERSION(10, 3, 1):
	case IP_VERSION(10, 3, 3):
	case IP_VERSION(10, 3, 6):
	case IP_VERSION(10, 3, 7):
	case IP_VERSION(11, 0, 1):
		adev->flags |= AMD_IS_APU;
		break;
	default:
		break;
	}

	if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
		adev->gmc.xgmi.supported = true;

	/* set NBIO version */
	switch (adev->ip_versions[NBIO_HWIP][0]) {
	case IP_VERSION(6, 1, 0):
	case IP_VERSION(6, 2, 0):
		adev->nbio.funcs = &nbio_v6_1_funcs;
		adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
		break;
	case IP_VERSION(7, 0, 0):
	case IP_VERSION(7, 0, 1):
	case IP_VERSION(2, 5, 0):
		adev->nbio.funcs = &nbio_v7_0_funcs;
		adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
		break;
	case IP_VERSION(7, 4, 0):
	case IP_VERSION(7, 4, 1):
	case IP_VERSION(7, 4, 4):
		adev->nbio.funcs = &nbio_v7_4_funcs;
		adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
		break;
	case IP_VERSION(7, 2, 0):
	case IP_VERSION(7, 2, 1):
	case IP_VERSION(7, 3, 0):
	case IP_VERSION(7, 5, 0):
	case IP_VERSION(7, 5, 1):
		adev->nbio.funcs = &nbio_v7_2_funcs;
		adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
		break;
	case IP_VERSION(2, 1, 1):
	case IP_VERSION(2, 3, 0):
	case IP_VERSION(2, 3, 1):
	case IP_VERSION(2, 3, 2):
	case IP_VERSION(3, 3, 0):
	case IP_VERSION(3, 3, 1):
	case IP_VERSION(3, 3, 2):
	case IP_VERSION(3, 3, 3):
		adev->nbio.funcs = &nbio_v2_3_funcs;
		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
		break;
	case IP_VERSION(4, 3, 0):
	case IP_VERSION(4, 3, 1):
		adev->nbio.funcs = &nbio_v4_3_funcs;
		adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
		break;
	case IP_VERSION(7, 7, 0):
		adev->nbio.funcs = &nbio_v7_7_funcs;
		adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
		break;
	default:
		break;
	}

	switch (adev->ip_versions[HDP_HWIP][0]) {
	case IP_VERSION(4, 0, 0):
	case IP_VERSION(4, 0, 1):
	case IP_VERSION(4, 1, 0):
	case IP_VERSION(4, 1, 1):
	case IP_VERSION(4, 1, 2):
	case IP_VERSION(4, 2, 0):
	case IP_VERSION(4, 2, 1):
	case IP_VERSION(4, 4, 0):
		adev->hdp.funcs = &hdp_v4_0_funcs;
		break;
	case IP_VERSION(5, 0, 0):
	case IP_VERSION(5, 0, 1):
	case IP_VERSION(5, 0, 2):
	case IP_VERSION(5, 0, 3):
	case IP_VERSION(5, 0, 4):
	case IP_VERSION(5, 2, 0):
		adev->hdp.funcs = &hdp_v5_0_funcs;
		break;
	case IP_VERSION(5, 2, 1):
		adev->hdp.funcs = &hdp_v5_2_funcs;
		break;
	case IP_VERSION(6, 0, 0):
	case IP_VERSION(6, 0, 1):
		adev->hdp.funcs = &hdp_v6_0_funcs;
		break;
	default:
		break;
	}

	switch (adev->ip_versions[DF_HWIP][0]) {
	case IP_VERSION(3, 6, 0):
	case IP_VERSION(3, 6, 1):
	case IP_VERSION(3, 6, 2):
		adev->df.funcs = &df_v3_6_funcs;
		break;
	case IP_VERSION(2, 1, 0):
	case IP_VERSION(2, 1, 1):
	case IP_VERSION(2, 5, 0):
	case IP_VERSION(3, 5, 1):
	case IP_VERSION(3, 5, 2):
		adev->df.funcs = &df_v1_7_funcs;
		break;
	default:
		break;
	}

	switch (adev->ip_versions[SMUIO_HWIP][0]) {
	case IP_VERSION(9, 0, 0):
	case IP_VERSION(9, 0, 1):
	case IP_VERSION(10, 0, 0):
	case IP_VERSION(10, 0, 1):
	case IP_VERSION(10, 0, 2):
		adev->smuio.funcs = &smuio_v9_0_funcs;
		break;
	case IP_VERSION(11, 0, 0):
	case IP_VERSION(11, 0, 2):
	case IP_VERSION(11, 0, 3):
	case IP_VERSION(11, 0, 4):
	case IP_VERSION(11, 0, 7):
	case IP_VERSION(11, 0, 8):
		adev->smuio.funcs = &smuio_v11_0_funcs;
		break;
	case IP_VERSION(11, 0, 6):
	case IP_VERSION(11, 0, 10):
	case IP_VERSION(11, 0, 11):
	case IP_VERSION(11, 5, 0):
	case IP_VERSION(13, 0, 1):
	case IP_VERSION(13, 0, 9):
	case IP_VERSION(13, 0, 10):
		adev->smuio.funcs = &smuio_v11_0_6_funcs;
		break;
	case IP_VERSION(13, 0, 2):
		adev->smuio.funcs = &smuio_v13_0_funcs;
		break;
	case IP_VERSION(13, 0, 6):
	case IP_VERSION(13, 0, 8):
		adev->smuio.funcs = &smuio_v13_0_6_funcs;
		break;
	default:
		break;
	}

	switch (adev->ip_versions[LSDMA_HWIP][0]) {
	case IP_VERSION(6, 0, 0):
	case IP_VERSION(6, 0, 1):
	case IP_VERSION(6, 0, 2):
		adev->lsdma.funcs = &lsdma_v6_0_funcs;
		break;
	default:
		break;
	}

	r = amdgpu_discovery_set_common_ip_blocks(adev);
	if (r)
		return r;

	r = amdgpu_discovery_set_gmc_ip_blocks(adev);
	if (r)
		return r;

	/* For SR-IOV, PSP needs to be initialized before IH */
	if (amdgpu_sriov_vf(adev)) {
		r = amdgpu_discovery_set_psp_ip_blocks(adev);
		if (r)
			return r;
		r = amdgpu_discovery_set_ih_ip_blocks(adev);
		if (r)
			return r;
	} else {
		r = amdgpu_discovery_set_ih_ip_blocks(adev);
		if (r)
			return r;

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
			r = amdgpu_discovery_set_psp_ip_blocks(adev);
			if (r)
				return r;
		}
	}

	if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
		r = amdgpu_discovery_set_smu_ip_blocks(adev);
		if (r)
			return r;
	}

	r = amdgpu_discovery_set_display_ip_blocks(adev);
	if (r)
		return r;

	r = amdgpu_discovery_set_gc_ip_blocks(adev);
	if (r)
		return r;

	r = amdgpu_discovery_set_sdma_ip_blocks(adev);
	if (r)
		return r;

	if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
	     !amdgpu_sriov_vf(adev)) ||
	    (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
		r = amdgpu_discovery_set_smu_ip_blocks(adev);
		if (r)
			return r;
	}

	r = amdgpu_discovery_set_mm_ip_blocks(adev);
	if (r)
		return r;

	r = amdgpu_discovery_set_mes_ip_blocks(adev);
	if (r)
		return r;

	return 0;
}

 

so goal is make this work:

 

case CHIP_RAVEN:
		if (adev->pdev->device == 0x15dd)
			adev->apu_flags |= AMD_APU_IS_RAVEN;
		if (adev->pdev->device == 0x15d8)
			adev->apu_flags |= AMD_APU_IS_PICASSO;
		break;
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I'm following the work of https://github.com/NootInc/WhateverRed

 

I've made 2 files to help compile using clang - sharing here for other developers

the tricky part Is the info.c file - its needed cause the project is ,cpp

other kexts made in .c don't need this

took me a while to figure this out - bb Xcode

 

CMakeLists.txt WhateverRed_info.c

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this is from a linux boot log:

 

[    1.188658] [drm:amdgpu_dm_irq_init [amdgpu]] DM_IRQ
[    1.188910] [drm:dal_firmware_parser_init_cmd_tbl [amdgpu]] Don't have set_crtc_timing for v1
[    1.189148] [drm] DM_PPLIB: values for F clock
[    1.189149] [drm] DM_PPLIB:	 400000 in kHz, 3124 in mV
[    1.189150] [drm] DM_PPLIB:	 933000 in kHz, 3599 in mV
[    1.189151] [drm] DM_PPLIB:	 1200000 in kHz, 4399 in mV
[    1.189152] [drm] DM_PPLIB:	 1467000 in kHz, 4399 in mV
[    1.189153] [drm] DM_PPLIB: values for DCF clock
[    1.189154] [drm] DM_PPLIB:	 300000 in kHz, 3124 in mV
[    1.189155] [drm] DM_PPLIB:	 600000 in kHz, 3599 in mV
[    1.189155] [drm] DM_PPLIB:	 626000 in kHz, 4250 in mV
[    1.189156] [drm] DM_PPLIB:	 654000 in kHz, 4399 in mV
[    1.189740] [drm:create_links [amdgpu]] BIOS object table - number of connectors: 4
[    1.189961] [drm:create_links [amdgpu]] DC: create_links: connectors_num: physical:4, virtual:0
[    1.190180] [drm:create_links [amdgpu]] BIOS object table - printing link object info for connector number: 0, link_index: 0
[    1.190397] [drm:link_create [amdgpu]] BIOS object table - link_id: 12
[    1.190612] [drm:link_create [amdgpu]] BIOS object table - is_internal_display: 0
[    1.190840] [drm:link_create [amdgpu]] BIOS object table - hpd_gpio id: 3
[    1.191059] [drm:link_create [amdgpu]] BIOS object table - hpd_gpio en: 0
[    1.191274] [drm:link_create [amdgpu]] Connector[0] description:signal 4
[    1.191489] [drm:dal_ddc_service_create [amdgpu]] BIOS object table - i2c_line: 0
[    1.191702] [drm:dal_ddc_service_create [amdgpu]] BIOS object table - i2c_engine_id: 1
[    1.191916] [drm:link_create [amdgpu]] BIOS object table - DP_IS_USB_C: 0
[    1.192130] [drm:link_create [amdgpu]] BIOS object table - IS_DP2_CAPABLE: 0
[    1.192344] [drm:link_create [amdgpu]] BIOS object table - device_tag.acpi_device: 0
[    1.192557] [drm:link_create [amdgpu]] BIOS object table - device_tag.dev_id.device_type: 3
[    1.192771] [drm:link_create [amdgpu]] BIOS object table - device_tag.dev_id.enum_id: 2
[    1.192984] [drm:link_create [amdgpu]] BIOS object table - ddi_channel_mapping: 0x00E4
[    1.193198] [drm:link_create [amdgpu]] BIOS object table - chip_caps: 0
[    1.193428] [drm:link_create [amdgpu]] BIOS object table - dc_link_construct_legacy finished successfully.
[    1.193642] [drm:create_links [amdgpu]] BIOS object table - printing link object info for connector number: 1, link_index: 1
[    1.193857] [drm:link_create [amdgpu]] BIOS object table - link_id: 0
[    1.194092] [drm:link_create [amdgpu]] BIOS object table - is_internal_display: 0
[    1.194320] [drm:link_create [amdgpu]] dc_link_construct_legacy: Invalid Connector ObjectID from Adapter Service for connector index:1! type 0 expected 3
[    1.194529] [drm:link_create [amdgpu]] BIOS object table - dc_link_construct_legacy failed.
[    1.194741] [drm:create_links [amdgpu]] BIOS object table - printing link object info for connector number: 2, link_index: 1
[    1.194951] [drm:link_create [amdgpu]] BIOS object table - link_id: 0
[    1.195162] [drm:link_create [amdgpu]] BIOS object table - is_internal_display: 0
[    1.195369] [drm:link_create [amdgpu]] dc_link_construct_legacy: Invalid Connector ObjectID from Adapter Service for connector index:2! type 0 expected 3
[    1.195577] [drm:link_create [amdgpu]] BIOS object table - dc_link_construct_legacy failed.
[    1.195776] [drm:create_links [amdgpu]] BIOS object table - printing link object info for connector number: 3, link_index: 1
[    1.195961] [drm:link_create [amdgpu]] BIOS object table - link_id: 19
[    1.196119] [drm:link_create [amdgpu]] BIOS object table - is_internal_display: 0
[    1.196290] [drm:link_create [amdgpu]] BIOS object table - hpd_gpio id: 3
[    1.196448] [drm:link_create [amdgpu]] BIOS object table - hpd_gpio en: 3
[    1.196605] [drm:link_create [amdgpu]] Connector[3] description:signal 32
[    1.196764] [drm:dal_ddc_service_create [amdgpu]] BIOS object table - i2c_line: 3
[    1.196921] [drm:dal_ddc_service_create [amdgpu]] BIOS object table - i2c_engine_id: 1
[    1.197079] [drm:link_create [amdgpu]] BIOS object table - DP_IS_USB_C: 1
[    1.197237] [drm:link_create [amdgpu]] BIOS object table - IS_DP2_CAPABLE: 0
[    1.197395] [drm:link_create [amdgpu]] BIOS object table - device_tag.acpi_device: 0
[    1.197553] [drm:link_create [amdgpu]] BIOS object table - device_tag.dev_id.device_type: 3
[    1.197711] [drm:link_create [amdgpu]] BIOS object table - device_tag.dev_id.enum_id: 1
[    1.197868] [drm:link_create [amdgpu]] BIOS object table - ddi_channel_mapping: 0x00E4
[    1.198026] [drm:link_create [amdgpu]] BIOS object table - chip_caps: 256
[    1.198200] [drm:link_create [amdgpu]] BIOS object table - dc_link_construct_legacy finished successfully.
[    1.198358] [drm:create_links [amdgpu]] BIOS object table - end
[    1.198521] [drm:dc_create [amdgpu]] Display Core initialized
[    1.198695] [drm] Display Core initialized with v3.2.177!

this is a dump of raven/picasso generic bios connectors:

 

 0174:  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo :
    0174:  ATOM_COMMON_TABLE_HEADER sHeader                    :
      0174:  USHORT usStructureSize                              = 0x0000     (0)
      0176:  UCHAR ucTableFormatRevision                         = 0x00       (0)
      0177:  UCHAR ucTableContentRevision                        = 0x00       (0)
    0178:  UCHAR ucGuid                                    [0] = 0x00       (0)
    0179:  UCHAR ucGuid                                    [1] = 0x00       (0)
    017a:  UCHAR ucGuid                                    [2] = 0x00       (0)
    017b:  UCHAR ucGuid                                    [3] = 0x00       (0)
    017c:  UCHAR ucGuid                                    [4] = 0x00       (0)
    017d:  UCHAR ucGuid                                    [5] = 0x00       (0)
    017e:  UCHAR ucGuid                                    [6] = 0x00       (0)
    017f:  UCHAR ucGuid                                    [7] = 0x00       (0)
    0180:  UCHAR ucGuid                                    [8] = 0x00       (0)
    0181:  UCHAR ucGuid                                    [9] = 0x00       (0)
    0182:  UCHAR ucGuid                                   [10] = 0x00       (0)
    0183:  UCHAR ucGuid                                   [11] = 0x00       (0)
    0184:  UCHAR ucGuid                                   [12] = 0x00       (0)
    0185:  UCHAR ucGuid                                   [13] = 0x00       (0)
    0186:  UCHAR ucGuid                                   [14] = 0x00       (0)
    0187:  UCHAR ucGuid                                   [15] = 0x00       (0)
    0188:  EXT_DISPLAY_PATH sPath                          [0] :
      0188:  USHORT usDeviceTag                                  = 0x0000     (0)
      018a:  USHORT usDeviceACPIEnum                             = 0x0000     (0)
      018c:  USHORT usDeviceConnector                            = 0x0000     (0)
      018e:  UCHAR ucExtAUXDDCLutIndex                           = 0x00       (0)
      018f:  UCHAR ucExtHPDPINLutIndex                           = 0x00       (0)
      0190:  USHORT usExtEncoderObjId                            = 0x0000     (0)
        <unparsable> line 3469:   union{
      skipping...
    0198:  EXT_DISPLAY_PATH sPath                          [1] :
      0198:  USHORT usDeviceTag                                  = 0x0000     (0)
      019a:  USHORT usDeviceACPIEnum                             = 0x0000     (0)
      019c:  USHORT usDeviceConnector                            = 0x0000     (0)
      019e:  UCHAR ucExtAUXDDCLutIndex                           = 0x00       (0)
      019f:  UCHAR ucExtHPDPINLutIndex                           = 0x00       (0)
      01a0:  USHORT usExtEncoderObjId                            = 0x0000     (0)
        <unparsable> line 3469:   union{
      skipping...
    01a8:  EXT_DISPLAY_PATH sPath                          [2] :
      01a8:  USHORT usDeviceTag                                  = 0x0000     (0)
      01aa:  USHORT usDeviceACPIEnum                             = 0x0000     (0)
      01ac:  USHORT usDeviceConnector                            = 0x0000     (0)
      01ae:  UCHAR ucExtAUXDDCLutIndex                           = 0x00       (0)
      01af:  UCHAR ucExtHPDPINLutIndex                           = 0x00       (0)
      01b0:  USHORT usExtEncoderObjId                            = 0x0000     (0)
        <unparsable> line 3469:   union{
      skipping...
    01b8:  EXT_DISPLAY_PATH sPath                          [3] :
      01b8:  USHORT usDeviceTag                                  = 0x0000     (0)
      01ba:  USHORT usDeviceACPIEnum                             = 0x0000     (0)
      01bc:  USHORT usDeviceConnector                            = 0x0000     (0)
      01be:  UCHAR ucExtAUXDDCLutIndex                           = 0x00       (0)
      01bf:  UCHAR ucExtHPDPINLutIndex                           = 0x00       (0)
      01c0:  USHORT usExtEncoderObjId                            = 0x0000     (0)
        <unparsable> line 3469:   union{
      skipping...
    01c8:  EXT_DISPLAY_PATH sPath                          [4] :
      01c8:  USHORT usDeviceTag                                  = 0x0000     (0)
      01ca:  USHORT usDeviceACPIEnum                             = 0x0000     (0)
      01cc:  USHORT usDeviceConnector                            = 0x0000     (0)
      01ce:  UCHAR ucExtAUXDDCLutIndex                           = 0x00       (0)
      01cf:  UCHAR ucExtHPDPINLutIndex                           = 0x00       (0)
      01d0:  USHORT usExtEncoderObjId                            = 0x0000     (0)
        <unparsable> line 3469:   union{
      skipping...
    01d8:  EXT_DISPLAY_PATH sPath                          [5] :
      01d8:  USHORT usDeviceTag                                  = 0x0000     (0)
      01da:  USHORT usDeviceACPIEnum                             = 0x0000     (0)
      01dc:  USHORT usDeviceConnector                            = 0x0000     (0)
      01de:  UCHAR ucExtAUXDDCLutIndex                           = 0x00       (0)
      01df:  UCHAR ucExtHPDPINLutIndex                           = 0x00       (0)
      01e0:  USHORT usExtEncoderObjId                            = 0x0000     (0)
        <unparsable> line 3469:   union{
      skipping...
    01e8:  EXT_DISPLAY_PATH sPath                          [6] :
      01e8:  USHORT usDeviceTag                                  = 0x0000     (0)
      01ea:  USHORT usDeviceACPIEnum                             = 0x0000     (0)
      01ec:  USHORT usDeviceConnector                            = 0x0000     (0)
      01ee:  UCHAR ucExtAUXDDCLutIndex                           = 0x00       (0)
      01ef:  UCHAR ucExtHPDPINLutIndex                           = 0x00       (0)
      01f0:  USHORT usExtEncoderObjId                            = 0x0000     (0)
        <unparsable> line 3469:   union{
      skipping...
    01f8:  UCHAR ucChecksum                                    = 0x00       (0)
    01f9:  UCHAR uc3DStereoPinId                               = 0x00       (0)
    01fa:  UCHAR Reserved                                  [0] = 0x00       (0)
    01fb:  UCHAR Reserved                                  [1] = 0x00       (0)
    01fc:  UCHAR Reserved                                  [2] = 0x00       (0)
    01fd:  UCHAR Reserved                                  [3] = 0x00       (0)
    01fe:  UCHAR Reserved                                  [4] = 0x00       (0)
    01ff:  UCHAR Reserved                                  [5] = 0x00       (0)

  Total data structure size:  0200

the problem in the x6000 code (OS X log):


(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AMDRadeonX6000_AmdLogger::writeLog(LogType, LogSeverity, char const*, ...) const> [7:0:0] [VRAM] mapMemorySpace() !!! Failed to get descriptor for ROM Base.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdAsicInit *AmdAsicInit::createAsicInit(AmdAtomFwHelper *) --- tableIndex:0, V 2.1.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdDisplayControllerInit *AmdDisplayControllerInit::createDisplayControllerInit(AmdAtomFwHelper *) --- tableIndex:0xd, V 2.1.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdDmcuService *AmdDmcuService::createDmcuService(AmdAtomFwHelper *) --- tableIndex:0x42, V 0.0.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdAtomFirmwareInfo *AmdAtomFirmwareInfo::createFirmwareInfo(AmdAtomFwHelper *, uint32_t) --- V 3.1.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdAtomDcInfo *AmdAtomDcInfo::createDcInfo(AmdAtomFwHelper *, uint32_t) --- V 4.2.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdAtomSmuInfo *AmdAtomSmuInfo::createSmuInfo(AmdAtomFwHelper *, uint32_t) --- V 3.1.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomPspDirectory::createPspDirectory(AmdAtomFwHelper*, unsigned int)> ATOM: static AmdAtomPspDirectory *AmdAtomPspDirectory::createPspDirectory(AmdAtomFwHelper *, uint32_t): ASSERT(0 != tableOffset)
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomVramInfo::createVramInfo(AmdAtomFwHelper*, unsigned int)> ATOM: static AmdAtomVramInfo *AmdAtomVramInfo::createVramInfo(AmdAtomFwHelper *, uint32_t): ASSERT(0 != tableOffset)
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdAtomVramUsageByFw *AmdAtomVramUsageByFw::createVramUsage(AmdAtomFwHelper *, uint32_t) --- V 2.1.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdAtomObjectInfo *AmdAtomObjectInfo::createObjectInfo(AmdAtomFwHelper *, uint32_t) --- V 1.4.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwHelper::debugPrint(unsigned int, char const*, ...) const> [7:0:0][ATOM][LIB] static AmdAtomGpioPinLut *AmdAtomGpioPinLut::createGpioPinLutTable(AmdAtomFwHelper *, uint32_t) --- V 2.1.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomFwServices::getPspFirmwareInfo(AtomPspFirmwareInfo&) const> ATOM: virtual IOReturn AmdAtomFwServices::getPspFirmwareInfo(AtomPspFirmwareInfo &) const: ASSERT(nullptr != m_pspDirectory)
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AMDRadeonX6000_AmdAsicInfo::refresh()> [7:0:0][GPUCAP] refresh() --- Family: 142, Device: 0x15d8, revNo: 0, pciRevNo: c9, emuRevNo: 65.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AMDRadeonX6000_AmdAsicInfo::refresh()> [7:0:0][GPUCAP] refresh() --- Mem Size: FB: 2048 MB, Aper: 256 MB, Reg Aper: 512 KB.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AMDRadeonX6000_AmdAsicInfo::refresh()> [7:0:0][GPUCAP] refresh() --- Mem Config: Width: 64, Type: DDR4.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AMDRadeonX6000_AmdAsicInfo::refresh()> [7:0:0][GPUCAP] refresh() --- FB Base: 0xf400000000, Top: 0xf47fffffff, Offset: 0x1af000000.
(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AMDRadeonX6000_AmdAsicInfo::refresh()> [7:0:0][GPUCAP] refresh() --- Branding - family: "Radeon"; device: "Navi10"; model: "Radeon Navi10".
  

(AMDRadeonX6000Framebuffer) <AMDRadeonX6000Framebuffer`AmdAtomObjectInfo_V1_4::populateConnectorEntry(atom_display_object_path_v2*, AtomConnectorEntry&) const> ATOM: IOReturn AmdAtomObjectInfo_V1_4::populateConnectorEntry(atom_display_object_path_v2 *, AtomConnectorEntry &) const: ASSERT(0 != object->device_tag)

the last line is where it fails - no info from bios !!

 

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