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vit9696

Shiki — protected video playback support on recent hardware

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This is a kext correcting certain issues at userspace level. At this moment it is only interesting for Ivy owners and newer.
 
Homepage | Historical background

It is likely reasonable to collect some stats with hardware reports (which ones worked ok, which ones failed). Please use the following format: CPU Model, GPU Model, IGPU Model (including ig-platform-id), OS X version. 

P. S. Read the FAQ before asking any questions.

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Tested the kext on the following setups:

post-638272-0-03132700-1463838478_thumb.jpg

 

It works even if I connect my TV-Set via DP-to-HDMI-Adapter to the HP Laptop... :)It is running on both machines...

post-638272-0-61333600-1463838380_thumb.jpg

post-638272-0-22859900-1463838388_thumb.jpg

post-638272-0-68804100-1463838396_thumb.jpg

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Can't say I really understand this kext, but for the first time iTunes plays trailers, I used to have audio only.

 

Z97 with haswell cpu, Intel 4600 enabled without connectors (04120004) and gtx660 connected with dvi to monitor.

 

Thanks!

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hi guys

 

forgive me for my ignorance but where is the kext?

 

I downloaded the master .zip but i don't see any kext in the folders.

 

Thanks for your support and sorry again

 

Never mind....

 

Maybe i am not yet awaken

 

Sorry

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hi guys

 

forgive me for my ignorance but where is the kext?

 

I downloaded the master .zip but i don't see any kext in the folders.

 

Thanks for your support and sorry again

 

Never mind....

 

Maybe i am not yet awaken

 

Sorry

 

post-1069282-0-66405700-1463851068_thumb.png

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hi guys

 

forgive me for my ignorance but where is the kext?

 

I downloaded the master .zip but i don't see any kext in the folders.

 

Thanks for your support and sorry again

 

Never mind....

 

Maybe i am not yet awaken

 

Sorry

here https://github.com/vit9696/Shiki/releases

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can you lower down the build to support 10.8 please

Hi, I had already replied but the forum ate my message unfortunately. Supporting 10.8 is not as easy as just setting the compatibility mode to 12.x and building with a correct SDK.

Last time I updated Shiki I spent quite some time trying to get it run on 10.8.5, however, this would require using a different method, i.e. spending a reasonable amount of time I cannot afford at the moment. Do you absolutely need 10.8 support?

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Hi

well... 10.8 was the first build to support full 64-bit operating system and therefore should still be included in any form of development. IMO :)

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Hi

well... 10.8 was the first build to support full 64-bit operating system and therefore should still be included in any form of development. IMO :)

Well, in this case I guess there is no reason for it. Nobody uses it anyway. I could imagine 10.6 support (because it was the last 32-bit OS X), but not 10.8 which unlike 10.9 gets no security updates these days. You could manually patch the files of 10.8 if you really need to play DRM content on it (unlike 10.9+ code signature is not verified there).

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Hello vit9696,

 

If you see this, thanks for your awesome work! I appreciate what you and all the other users have done to contribute to this project. I do have one small question, born of my own ignorance. I use the nVidia webdrivers since I have a Maxwell card, and in your FAQ it's stated "NVIDIA drivers do not properly add these values necessary for VDA decoding for Maxwell GPUs in their Web drivers. You could add them with a plist-only kext. The correct values for VP4 GPUs are:"

 
Since I am a bit unfamiliar with creating kexts, I do have to ask what that might entail. If someone else might know how to do this I'd also greatly appreciate it. My questions would be what should go into the Info.plist in the supposed custom kext, and what to call the kext. I'd also need some guidance on how to make the kext apply its values to my Maxwell, ie linking it. Is that in the deviceid? I tried adding the IOVARendererID and IOVARendererSubID values with an <integer> string to my existing NVDAGM100HalWeb.kext info.plist and that just causes a KP during the bootup.
 
Granted, I only tried that because I didn't know that would cause a crash.
 
Thanks in advance to anyone with the know-how to do this or could point me the right direction creating a plist-only kext that affects my Maxwell card.

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I tried with my Asus X550LDV with the Intel HD4400 and Nvidia 820m, which i disabled in DSDT.

Without shiki, I get audio on iTunes trailer, when I install Shiki, and the play a trailer from iTunes, Mac OS X freezes and I have to force shutdown. Hope you keep improving the kext and working on it. Thanks.


I have a intel core i7 - 42xx (Haswell) and using Mac OS X 10.11.6

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"Azul GPUs (e.g. HD 4400, HD 4600) when used with a connector-full platform-id without a discrete GPU cause a system freeze due to not working HDCP playback. The issue is unrelated to Shiki, and happens regardless of iTunes and QuickTime."

 

How can i start to reverse engineer it?? what would be the first step?

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When using my GTX 780, both default drivers as well as web drivers work without any problem. When I switching to my GTX 960 (while using web drivers) it stops working because of the hardware decoding fails. I downloaded the iMac.kext and filled in the values mentioned in the FAQ (for both VP3 and VP4, without any space) but it keeps dysfunctional. Neither HD4600 decoding nor nVidia decoding works when the GTX 960 is plugged in.

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GTX 780 gpu does not provide any hardware accelerated decoding itself due to unimplemented hardware decoding. Neither do any GPUs newer than GT 2xx as far as I know. That's why a lot of recommendations on the net recommending to use forceNV/forceATI/forceIntel are mad, and these people are ignorant to FAQ, which explicitly states:

No override preferences are used;

You should enable both Intel HD4600 and GTX 780, with HD4600 powered with a connector-free ig-platform-id (<04 00 12 04>) as a secondary GPU. You might also need iMac.kext to allow forwarding intel hardware decoding to nvidia (easily checked by value presence in IOReg). Your GPU is definitely VP4, so you might not even need any modifications.

Check "Shiki-based solution for non-freezing Intel and/or any discrete GPU" FAQ section all in all :)

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You should enable both Intel HD4600 and GTX 780, [...] so you might not even need any modifications.

 

That's totally correct, decoding is performed by the Intel HD 4600, my question is why it works when my GTX 780 is plugged in while it doesn't work when I use my GTX 960. I do not try to override any setting, so using the old Kepler works OOB while Maxwell does not at all (using iMac.kext only throws different errors).

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Oops, looks like I was too busy yesterday and somehow managed to completely misinterpret your message. Sorry.

That's strange, mhm. The keys are certainly needed for Maxwell GPUs:

IOVARendererID → <08 00 04 01>

IOVARendererSubID → <03 00 00 00>

 

And iMac.kext did work for a couple of people last time they tried. Did you check them via IOReg after installing the kext?

To get hardware decoding work you need proper GFX0 / IGPU naming too.

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My bad, I got it working now. Naming of IGPU was correct but it as it seems Xcode .plist editor screwed the data field up. I edited it again using Plist Editor Pro and now it works pretty well with the GTX 960 and web drivers.

 

I know it's a bit off-topic, but do you know if Apple plans to support HEVC hardware decoding? The current Skylake (partial/8bit) and upcoming Kaby Lake (full/10bit) CPUs have support for it.

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I know it's a bit off-topic, but do you know if Apple plans to support HEVC hardware decoding? The current Skylake (partial/8bit) and upcoming Kaby Lake (full/10bit) CPUs have support for it.

 

The answer is obvious :)

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      cd ~/Desktop/TSCAdjustReset/ Now compile the source distribution with Xcode by using the following terminal command:
      xcodebuild After successful compilation, you will find the TSCAdjustRest.kext in ~/Desktop/TSCAdjustReset/build/Release/
        Please note that the TSCAdjustRest.kext by default is configured for a 8-core CPU (16 threads) like the i7-7900K. To adopt the kext for Broadwell-E and Haswell-E processors with more or less cores than 8 cores, apply the following approach:   a.) Right-click with the mouse on the TSCAdjustRest.kext file and select "Show Packet Contents".   b.) Double-click with the mouse on /contents/ . After a right-click on the "Info.plist" file, select "Open with /Other". Select the TextEdit.app and edit the "Info.plist" file.   c.) Use the "find"-function of TextEdit.app and search for the term "IOCPUNumber"   d.) Note that the adequate IOCPUNumber for your particular CPU is the number of its threads -1, by always keeping in mind that the number of it's threads is always 2x the number of it's cores.   Thus, in case of the 10 core i7-6950X, the IOCPUNumber is 19 (20 threads - 1). <key>IOCPUNumber</key> <integer>19</integer>   and following the same methodology, the correct IOCPUNumber for the 6-core i7-6800K is 11 (12 threads -1) <key>IOCPUNumber</key> <integer>11</integer>   e.) After adopting the IOCPUNumber for your particular Broadwell-E/EP, Haswell-E/EP processor, save the info.plist file and copy the modified VoodooTSCSync.kext to the /EFI/CLOVER/kexts/Other/ - directories of both USB Flash Drive Installer and System Disk!  
      5.) Like under macOS 10.13 High Sierra also with macOS 10.14 Mojave, Apple forces all users to use the new Apple file system APFS in case of a Clean Install.     In case that you want to remain with the HFS+ file system, use @Brumbear's Unsolid.kext in the /EFI/Clover/kexts/Other/ directory.   Note that there is no way to convert an APFS disk back to HFS+ without the loss of all data, but one can easily reformat an APFS formatted disk to HFS+ under OSX by using either Apple's Disk Utility App or "diskutil" commands. All you need to do is to previously unmount the APFS volume before erasing it with a journaled HFS+ file system and a GRUB Partition Table (GTP). If you want to maintain the disk's content, perform a backup before erasing the disk with a HFS+ format.   The application of Apple's Disk utility is straight forward. The  "diskutil" equivalent is detailed below:   In the Terminal app, type: diskutil list In the output which you can read by scrolling back, you will find all internal disks named /dev/disk0, /dev/disk1, depending upon how many physical disks are present in your system.
        Make a note of the disk identifier for the disk you intend to format (you can eliminate risk by removing all disks but the intended target).   In the Terminal app, type: diskutil unmount /dev/diskX where diskX is a place holder for the disk to be unmounted.
        Now delete the APFS container of diskX: diskutil apfs deleteContainer /dev/diskX Subsequently, you can erase the entire disk with HFS+ and a GPT by typing the following terminal command:
      diskutil partitionDisk /dev/diskX 1 GPT jhfs+ "iMacPro" R where /dev/diskX is again a place holder for disk to be erased and iMacPro would be the label for the single partition created. The remaining 1 GPT jhfs+ and R arguments tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and using the entire disk, respectively.
        Alternatively one can also use the following terminal command: diskutil partitionDisk /dev/diskX GPT JHFS+ iMacPro 0b where /dev/diskX is again a place holder for disk to be erased and iMacPro is again the label for the disk partition created. The GPT HFFS+ and 0b arguments again tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and covering the entire disk, respectively.
        In the Terminal app, type now: diskutil mount /dev/diskX where diskX is again a place holder for the disk to be remounted.
        Note, that by means of the "diskutil approach", brand new unformatted or not compatibly formatted system NVMe, SSD and HDD system drives can be also directly formatted within the macOS Clean Install procedure. When presented with the initial install screen where you are presented options to Restore From Backup or Install, select Terminal from the Utilities menu bar item;   The "diskutil" terminal approach is also able to convert a HFS+ macOS Mojave System Disk to APFS. To do so enter the following terminal command: diskutil apfs convert /dev/diskX where diskX is again a place holder for the HFS+ disk to be converted to APFS. The same procedure again can also be directly performed by means of Apple's Disk Utility.
        Important recommendation: If you opt for an APFS System Disk implementation, try to also implement all other disks of your system with APFS file format. On systems with APFS disks and non-APFS disks, the boot duration will increase, as apsf.efi will perform a fsck check of non-AFPS disks (like HFS+ or Fat32) during boot. However, dual boot APFS Systems with an NTFS Windows System Disk are not effected by the apsf.efi issue, as OSX does not know how to properly deal with NTFS.  
      6.) For the proper function of Lilu.kext and Lilu plugins like AppleALC.kext, NvidiaGraphicsFixup.kext, Whatevergreen.kext etc. one also needs to add boot flag "-lilubetaall" to the config.plist during the 10.14 Mojave Betas.
       
      7.) In order to successfully boot your X99 macOS 10.14 Mojave System system, carefully verify that your config.plist contains in Section "KextsToPatch" of Section "Kernel and Kext Patches" of Clover Configurator the 10.14 IOPCIFamily Kext Patch kindly provided by @PMHeart.           D.) iMac macOS 10.14 Mojave System Setup   Below, one finds a detailed description for the Installation/Update of/to macOS Mojave 10.14 DP1 (18A293u). This also includes the EFI-Folder Preparation (D.1), the macOS Mojave 10.14 DP1 (18A293u) Installer Package creation (D.2), the macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer Creation (D.3) and the macOS Mojave 10.14 DP1 (18A293u) Clean Install. One also finds instructions for a direct iMac Pro conversion of a functional Broadwell-E/EP, Haswell-E/EP X99 system with a SMBIOS System Definition different from iMacPro1,1 and standard macOS build implementation (D.5) of any former macOS distribution. D.6 finally provides details to the future iMac Pro macOS Mojave Update Procedure.   D.1) iMac Pro EFI-Folder Preparation    In order to successfully boot a macOS USB Flash Drive Installer or System Disk on a Hackintosh system, both drives must be equipped with an EFI-Folder in their EFI partitions. In this Section we will prepare a fully equipped EFI-Folder with SMBIOS iMacPro1,1 System definition.   1.) Download and unzip EFI-X99-10.14-DP1-Release-iMacPro1,1-160618  and copy the therein contained EFI-Folder to your Desktop.   2.) Open the config.plist in /EFI/Clover/ with the latest version of Clover Configurator (>/= v.4.60.0), proceed to the "SMBIOS" Section and complete the SMBIOS iMacPro1,1 Serial Number, Board Serial Number and SMUUID entries. These details are mandatory to successfully run iMessage and FaceTime on your iMac Pro System. Note that all other iMacPro1,1 SMBIOS Details  are already implemented in the config.plist of EFI-X99-10.14-DP1-Release-iMacPro1,1-160618.   Press several times the "Generate New" Button next to serial number text field.   Open a terminal, enter repeatedly the command "uuidgen", and copy the output value to the SMUUID field in the "SMBIOS" Section of the Clover Configurator.   Depending on your system configuration (Broadwell-E/EP or Haswell-E/EP) change or adopt the following settings if necessary     a.) Users of mainboards with locked MSR Register (disabled MSR OSX Kernel write access) have to add the xcpm_core_scope_msrs © Pike R. Alpha Kernel patch in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator and also to check KernelPm in addition.   b.) "FakeCPUID" in "Kernel and Kext Patches" Section of Clover Configurator:   Broadwell-E/EP FakeCPUID: "0x040674"    Haswell-E/EP standard FakeCPUID: "0x0306F2"     All Broadwell-E/EP and Haswell-E/EP users have to enable the Broadwell-E performance Kernel patch for macOS Mojave 10.14 of @PMheart in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator, to overcome persistent OC and performance flaw issues.   c.) Broadwell-E performance Kernel patch Find: C1E30848 63D389D0 48C1EA20 B9990100 000F3048 FF057348 73004883 C4085B5D C30F1F40 00 Replace: B800FF00 004863D3 89D048C1 EA20B999 0100000F 3048FF05 73487300 4883C408 5B5DC390 90   To successfully boot my Broadwell-E X99 System and to obtain full XCPM-performance I also need to include the following Kernel patches:   d.) xcpm_pkg_scope_msrs © Pike R. Alpha (kindly provided by @PMHeart) Find: BE070000 0031D2E8 91FCFFFF Replace: BE070000 0031D290 90909090   e.) _xcpm_SMT_scope_msrs 2 © Pike R. Alpha (kindly provided by @PMHeart) Find: BE0B0000 0031D2E8 66FCFFFF Replace: BE0B0000 0031D290 90909090   f.) Enable "PluginType" in your config.plist under SSDT/Generate Options/ in Section ACPI of Clover Configurator for a fully working XCPM implementation. Note that by this, Pike Alpha's former ssdt.aml XCPM implementation becomes totally obsolete.     g.) Aslo verify once more in concordance with Error Protection C.6) and C.7) that your config.plist contains boot flag "-lilubetaall" and the 10.14 IOPCIFamily kext patch!     Finally save the modified config.plist.   3.) Copy the appropriate TSCAdjustRest.kext, which you modified in error prevention C.4), to the /EFI/CLOVER/kexts/Other/ directory of the EFI-Folder.   You know have a fully equipped EFI-Folder for subsequent implementations as detailed below.   D.2) iMac Pro macOS Mojave 10.14 DP1 (18A293u) Installer Package Creation    To derive the macOS Mojave 10.14 DP1 (18A293u) Full-Package Installer just download and execute macOSDeveloperBetaAccessUtility.dmg and complete the subsequent steps you are asked for.    D.3) iMac Pro macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer Creation    Follow the individual steps detailed below to successfully create a bootable iMac Pro macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer.   1.) Format a USB Flash Drive of your choice (source, named USB) with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on your iMac Pro macOS USB Flash Drive Installer.   2.) With the macOS Mojave 10.14 DP1 (18A293u) Installer Package in your /Application Folder,  connect your USB Flash Drive (named USB) and run the following terminal command: sudo /Applications/Install\ macOS\ 10.14\ Beta.app/Contents/Resources/createinstallmedia --volume /Volumes/USB --nointeraction Alternatively, one can create the iMac Pro macOS USB Flash Drive Installer also by means of the Install Disk Creator.app.
        3.) If your macOS USB Flash Drive Installer is not bootable you can additionally perform the following terminal commands: cd /Volumes/YOUR_USB_VOLUME mkdir .IABootFiles cd .IABootFiles cp /Volumes/YOUR_USB_VOLUME/System/Library/CoreServices/boot.efi . "YOUR_USB_VOLUME" is a place holder in the above commands for the name of your real USB Flash Drive.
        With the terminal command: ls boot.efi you can subsequently verify that boot.efi is there where it should be.
        4.) For successfully booting your iMac Pro macOS USB Flash Drive Installer, the latter must however also contain a valid EFI- Folder with an SMBIOS iMacPro1,1 system definition. Thus, copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition of your macOS USB Flash Drive Installer.   You now have a fully functional and bootable macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer.     D.4) iMac Pro macOS Mojave 10.14 DP1 (18A293u) Clean Install on Broadwell-E/EP, Haswell-E/EP, X99   Follow the individual steps detailed below to successfully setup macOS Mojave 10.14 DP1 (18A293u)  on a virgin system drive of your choice (NVMe, SSD or HDD).   1.) In order to perform a clean install of macOS Mojave 10.14 DP1 (18A293u), prepare a virgin NVMe, SDD or HDD destination drive for the iMac Pro macOS installation by formatting the drive with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on the drive.   2.) Copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition.   3.) Now connect the Destination Drive to your Hackintosh System and boot the latter with the plugged macOS Mojave 10.14 DP1 (18A293u) USB Flash Drive Installer, your created in Section D.2)   4.) While booting your system, press the F8 button to enter the BIOS boot menu. Select to boot from your macOS USB Flash Drive Installer.   5.) Subsequently, click on the USB Flash Drive Installer Icon in the clover boot menu to boot the respective macOS Installer partition on your macOS USB Flash Drive Installer   6.) After successful boot, pass the individual steps of the macOS 10.14 Mojave installation menu and finally select the destination drive of your macOS 10.14 Mojave  Installation, which should be logically the system disk you successfully configured above. In the next step, the Installer will create a macOS Mojave 10.14 Installer Partition on the system disk and subsequently reboot your system.   7.) During system reboot, just press again the F8 button to enter the BIOS boot menu. Select again to boot from your USB Flash Drive. In contrary to 6.), click this time on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS Mojave 10.14 Installer Partition on your system disk.   8.) After successful boot, you will enter now the macOS Mojave 10.14 Installer Screen with a progress bar starting at about 34 minutes.   9.) After another reboot, press again the F8 button to enter the BIOS boot menu. Select to boot with your System Disk EFI-folder. Click on the "MacOS Mojave" icon on the clover boot screen to boot the new macOS Mojave  partition of your system disk.   10.) After successful boot you have to perform the iCloud registration to have your first iMac Pro macOS Mojave 10.14 DP1 (18A293u) build.    Proceed with Section D.6) - iMac Pro macOS High Sierra Build Updates (if necessary) or E.) - Post Installation Process.     D.5) Direct iMac Pro conversions of a functional Broadwell-E/EP, Haswell-E/EP, X99 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation    1.) Replace the EFI-Folder of your System Disk by the EFI-Folder you created in Section D.1)   2.) Copy /System/Library/CoreServices/PlatformSupport.plist to your Desktop, add BoardID "Mac-7BA5B2D9E42DDD94" under SupportedBoardIDs by means of Xcode as suggested by user Griven from the German Hackintosh-Forum and copy back the modified PlatformSupport.plist to System/Library/CoreServices/.   3.) If not already in your /Applications folder after performing Section D.2), copy the iMac Pro macOS Installer Package ("Install macOS 10.14 Beta.app") to your /Applications folder.   4.) Double click on the "Install macOS 10.14 Beta.app" in the /Applications Folder to start the macOS Mojave 10.14 DP1 (18A293u) installation.    5.) After reboot, click on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS Mojave 10.14 Installer Partition on your system disk.   6.) After successful boot, you will enter now the macOS Mojave 10.14 Installer Screen with a progress bar starting at 43 minutes.   7.) After another reboot, click on the "MacOS Mojave" icon in the clover boot screen to boot the updated macOS Mojave 10.14 on your system disk.   8.) After successful boot you have to register at iCloud at the end of the macOS installation, and you will now have your first iMac Pro macOS Mojave 10.14 DP1 (18A293u) build.   Proceed with Section D.6) - iMac Pro macOS 10.14 Mojave Update Procedure (if necessary) or Section E.) - Post Installation Process.   D.6) iMac Pro macOS 10.14 Mojave Update Procedure   If you already used my 10.13 iMacPro X99 guide to setup a 10.13 iMac Pro macOS build, you simply have to update your EFI-Folder and directly perform the update to macOS 10.14 Mojave from System Disk by else following steps 4.) to 8.) of D.5) above. This way you also will also be able to perform any future update of macOS 10.14 Mojave.   Let me conclude with a general recommendation:  In case of macOS beta builds one should clone the macOS System Drive with Carbon Copy Cloner (CCC) to a test drive and to update to the Betas on the latter.    
      E.) Post Installation Process   E.1) XNU CPU Power Management (XCPM) Configuration   The EFI folder of EFI-X99-10.14-DP1-Release-iMacPro1,1-160618, attached towards the end of this post, already contains a fully functional XCPM configuration for the i7-6950X Broadwell-E CPU, which just needs to be adopted for other CPU configurations (Broadwell-E/EP different from i7-6950X, Haswell-E/EP).   Before adapting the XCPM configuration, verify the following BIOS settings:   Advanced\CPU Configuration\CPU Power Management Configuration\ Enhanced Intel SpeedStep Technology (EIST): Disabled Turbo mode: Enabled CPU C-State: Enabled Enhanced C1 State: Enabled CPU C3 Report: Enabled CPU C6 Report: Enabled Package C State Limit: C6(non Retention) state  
      Subsequently, follow the individual steps below.   1.) Open the config.plist of your 10.14 system disk and revise the  "Kernel and Kext Patches" Section.     a.) Users of mainboards with locked MSR Register (disabled MSR OSX Kernel write access) have to add the xcpm_core_scope_msrs © Pike R. Alpha Kernel patch in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator and also to check KernelPm in addition.   b.) Verify "FakeCPUID" in "Kernel and Kext Patches" Section of Clover Configurator:   Broadwell-E/EP FakeCPUID: "0x040674"       Haswell-E/EP standard FakeCPUID: "0x0306F2"    All Broadwell-E/EP and Haswell-E/EP users have to enable the Broadwell-E performance Kernel patch for macOS Mojave 10.14 of @PMheart in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator, to overcome persistent OC and performance flaw issues.   c.) Broadwell-E performance Kernel patch Find: C1E30848 63D389D0 48C1EA20 B9990100 000F3048 FF057348 73004883 C4085B5D C30F1F40 00 Replace: B800FF00 004863D3 89D048C1 EA20B999 0100000F 3048FF05 73487300 4883C408 5B5DC390 90   To successfully boot my Broadwell-E X99 System and to obtain full XCPM-performance I also need to include the following Kernel patches:   d.) xcpm_pkg_scope_msrs © Pike R. Alpha (kindly provided by @PMHeart) Find: BE070000 0031D2E8 91FCFFFF Replace: BE070000 0031D290 90909090   e.) _xcpm_SMT_scope_msrs 2 © Pike R. Alpha (kindly provided by @PMHeart) Find: BE0B0000 0031D2E8 66FCFFFF Replace: BE0B0000 0031D290 90909090   f.) Enable "PluginType" in your config.plist under SSDT/Generate Options/ in Section ACPI of Clover Configurator for a fully working XCPM implementation. Note that by this, Pike Alpha's former ssdt.aml XCPM implementation becomes totally obsolete.   All other former XCPM kernel patches have become obsolete also with 10.14   There is also no need for injecting any additional frequency vector.   2.) Reboot after applying any changes.   To verify your XCPM configuration, perform the following steps:   1.) Verify with the terminal command "sysctl machdep.xcpm.mode" if the XCPM mode is active. If so, "sysctl machdep.xcpm.mode" should return "1".   2.) Verify that in the IORegistryExplorer you have the following entry under CP00@0: Property:         Type:         Value: plugin-type       Number        0x1  
      3.) Verify with the terminal command kextstat|grep -y x86plat  
      that the "X86PlatformPlugin.kext" is loaded. If the command returns something like 112    1 0xffffff7f822bc000 0x17000    0x17000    com.apple.driver.X86PlatformPlugin (1.0.0) FD88AF70-3E2C-3935-99E4-C48669EC274B <111 19 18 13 11 7 6 5 4 3 1> 146    1 0xffffff7f822d3000 0x7000     0x7000     com.apple.driver.X86PlatformShim (1.0.0) DCEA94A4-3547-3129-A888-E9D5C77B275E <112 111 13 7 4 3> you are fine.
        4.) Verify with the terminal command [code]kextstat|grep -y appleintelcpu[/code] that you got rid of the Apple Intel CPU power management. If the result is empty you are fine.
        5.) To verify that the Frequency-Vectors are loaded, use the following terminal command: sysctl -n machdep.xcpm.vectors_loaded_count  
      If everything is ok, the command returns "1".   6.) To obtain further information on your XCPM Power Management configuration, download Piker Alpha’s AppleIntelInfo.kext from Github. To compile the source code, you need to primarily install Xcode (Appstore) and Xcode Command Line Tools! This guideline might be helpful for the  successfully installation of the latter.   Now enter the following terminal commands: cd ~/Downloads/AppleIntelInfo-master xcodebuild cd build/Release chmod -R 755 AppleIntelInfo.kext sudo chown -R root:wheel AppleIntelInfo.kext  
      Load the AppleIntelInfo.kext with "kextload" and "cat" the info-results with the following terminal commands: sudo kextload AppleIntelInfo.kext sudo cat /tmp/AppleIntelInfo.dat  
      The cat command should reveal something like the following result: AppleIntelInfo.kext v2.5 Copyright © 2012-2017 Pike R. Alpha. All rights reserved. Settings: ------------------------------------------ logMSRs..................................: 1 logIGPU..................................: 0 logCStates...............................: 1 logIPGStyle..............................: 1 InitialTSC...............................: 0x11d3a1760ecb2 (10453 MHz) MWAIT C-States...........................: 8480 Processor Brandstring....................: Intel(R) Core(TM) i7-6950X CPU @ 3.00GHz Processor Signature..................... : 0x406F1 ------------------------------------------  - Family............................... : 6  - Stepping............................. : 1  - Model................................ : 0x4F (79) Model Specific Registers (MSRs) ------------------------------------------ MSR_CORE_THREAD_COUNT............(0x35)  : 0x0 ------------------------------------------  - Core Count........................... : 10  - Thread Count......................... : 20 MSR_PLATFORM_INFO................(0xCE)  : 0x20080C3BF3811E00 ------------------------------------------  - Maximum Non-Turbo Ratio.............. : 0x1E (3000 MHz)  - Ratio Limit for Turbo Mode........... : 1 (programmable)  - TDP Limit for Turbo Mode............. : 1 (programmable)  - Low Power Mode Support............... : 1 (LPM supported)  - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)  - Maximum Efficiency Ratio............. : 12  - Minimum Operating Ratio.............. : 8 MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x1E000005 ------------------------------------------  - I/O MWAIT Redirection Enable......... : 0 (not enabled)  - CFG Lock............................. : 0 (MSR not locked)  - C3 State Auto Demotion............... : 1 (enabled)  - C1 State Auto Demotion............... : 1 (enabled)  - C3 State Undemotion.................. : 1 (enabled)  - C1 State Undemotion.................. : 1 (enabled)  - Package C-State Auto Demotion........ : 0 (disabled/unsupported)  - Package C-State Undemotion........... : 0 (disabled/unsupported) MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x10414 ------------------------------------------  - LVL_2 Base Address................... : 0x414  - C-state Range........................ : 1 (C-States not included, I/O MWAIT redirection not enabled) IA32_MPERF.......................(0xE7)  : 0xACF485063 IA32_APERF.......................(0xE8)  : 0xB96AC7BB7 MSR_0x150........................(0x150) : 0x0 MSR_FLEX_RATIO...................(0x194) : 0xE0000 ------------------------------------------ MSR_IA32_PERF_STATUS.............(0x198) : 0x204900001E00 ------------------------------------------  - Current Performance State Value...... : 0x1E00 (3000 MHz) MSR_IA32_PERF_CONTROL............(0x199) : 0x2A00 ------------------------------------------  - Target performance State Value....... : 0x2A00 (4200 MHz)  - Intel Dynamic Acceleration........... : 0 (IDA engaged) IA32_CLOCK_MODULATION............(0x19A) : 0x0 IA32_THERM_INTERRUPT.............(0x19B) : 0x0 IA32_THERM_STATUS................(0x19C) : 0x883D0000 ------------------------------------------  - Thermal Status....................... : 0  - Thermal Log.......................... : 0  - PROCHOT # or FORCEPR# event.......... : 0  - PROCHOT # or FORCEPR# log............ : 0  - Critical Temperature Status.......... : 0  - Critical Temperature log............. : 0  - Thermal Threshold #1 Status.......... : 0  - Thermal Threshold #1 log............. : 0  - Thermal Threshold #2 Status.......... : 0  - Thermal Threshold #2 log............. : 0  - Power Limitation Status.............. : 0  - Power Limitation log................. : 0  - Current Limit Status................. : 0  - Current Limit log.................... : 0  - Cross Domain Limit Status............ : 0  - Cross Domain Limit log............... : 0  - Digital Readout...................... : 61  - Resolution in Degrees Celsius........ : 1  - Reading Valid........................ : 1 (valid) MSR_THERM2_CTL...................(0x19D) : 0x0 IA32_MISC_ENABLES................(0x1A0) : 0x850089 ------------------------------------------  - Fast-Strings......................... : 1 (enabled)  - FOPCODE compatibility mode Enable.... : 0  - Automatic Thermal Control Circuit.... : 1 (enabled)  - Split-lock Disable................... : 0  - Performance Monitoring............... : 1 (available)  - Bus Lock On Cache Line Splits Disable : 0  - Hardware prefetch Disable............ : 0  - Processor Event Based Sampling....... : 0 (PEBS supported)  - GV1/2 legacy Enable.................. : 0  - Enhanced Intel SpeedStep Technology.. : 1 (enabled)  - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)  - Adjacent sector prefetch Disable..... : 0  - CFG Lock............................. : 0 (MSR not locked)  - xTPR Message Disable................. : 1 (disabled) MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x640A00 ------------------------------------------  - Turbo Attenuation Units.............. : 0  - Temperature Target................... : 100  - TCC Activation Offset................ : 0 MSR_MISC_PWR_MGMT................(0x1AA) : 0x402000 ------------------------------------------  - EIST Hardware Coordination........... : 0 (hardware coordination enabled)  - Energy/Performance Bias support...... : 1  - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)  - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores) MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x2A2A2A2A2A2A2A2A ------------------------------------------  - Maximum Ratio Limit for C01.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C02.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C03.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C04.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C05.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C06.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C07.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C08.......... : 2A (4200 MHz) MSR_TURBO_RATIO_LIMIT1...........(0x1AE) : 0x2222222222222A2A ------------------------------------------  - Maximum Ratio Limit for C09.......... : 2A (4200 MHz)  - Maximum Ratio Limit for C10.......... : 2A (4200 MHz) IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x5 ------------------------------------------  - Power Policy Preference...............: 5 (balanced performance and energy saving) MSR_POWER_CTL....................(0x1FC) : 0x2904005B ------------------------------------------  - Bi-Directional Processor Hot..........: 1 (enabled)  - C1E Enable............................: 1 (enabled) MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03 ------------------------------------------  - Power Units.......................... : 3 (1/8 Watt)  - Energy Status Units.................. : 14 (61 micro-Joules)  - Time Units .......................... : 10 (976.6 micro-Seconds) MSR_PKG_POWER_LIMIT..............(0x610) : 0x7FFF80015FFF8 ------------------------------------------  - Package Power Limit #1............... : 4095 Watt  - Enable Power Limit #1................ : 1 (enabled)  - Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)  - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)  - Package Power Limit #2............... : 4095 Watt  - Enable Power Limit #2................ : 1 (enabled)  - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)  - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)  - Lock................................. : 0 (MSR not locked) MSR_PKG_ENERGY_STATUS............(0x611) : 0xC06AC ------------------------------------------  - Total Energy Consumed................ : 48 Joules (Watt = Joules / seconds) MSR_PKGC3_IRTL...................(0x60a) : 0x0 MSR_PKGC6_IRTL...................(0x60b) : 0x0 MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x298ED1EE0 MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0xD638F0 MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x298ED1EE0 MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0xD638F0 MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x44911A9AC IA32_TSC_DEADLINE................(0x6E0) : 0x11D3A1BDB3826 CPU Ratio Info: ------------------------------------------ Base Clock Frequency (BLCK)............. : 100 MHz Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz) Maximum non-Turbo Ratio/Frequency........: 30 (3000 MHz) Maximum Turbo Ratio/Frequency............: 42 (4200 MHz) P-State ratio * 100 = Frequency in MHz ------------------------------------------ CPU P-States [ (12) 27 30 ] CPU C3-Cores [ 1 2 4 6 8 10 12 14 16 18 ] CPU C6-Cores [ 0 2 4 6 8 10 12 14 16 18 ] CPU P-States [ 12 17 27 (30) ] CPU C3-Cores [ 1 2 3 4 6 7 8 10 11 12 14 15 16 18 19 ] CPU C6-Cores [ 0 2 4 6 8 9 10 12 14 16 17 18 ] CPU P-States [ (12) 17 27 30 31 ] CPU C3-Cores [ 0 1 2 3 4 6 7 8 9 10 11 12 14 15 16 18 19 ] CPU P-States [ (12) 14 17 27 30 31 ] CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 ] CPU C6-Cores [ 0 2 4 6 8 9 10 12 14 15 16 17 18 ] CPU P-States [ (12) 14 17 20 27 30 31 ] CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ] CPU C6-Cores [ 0 1 2 4 6 7 8 9 10 12 14 15 16 17 18 ] CPU P-States [ (12) 14 16 17 20 27 30 31 ] CPU P-States [ (12) 14 16 17 18 20 27 30 31 ] CPU P-States [ (12) 14 16 17 18 20 27 30 31 32 ] CPU P-States [ (12) 14 16 17 18 20 22 27 30 31 32 ] CPU C6-Cores [ 0 1 2 3 4 6 7 8 9 10 12 14 15 16 17 18 ] CPU P-States [ (12) 13 14 16 17 18 20 22 27 30 31 32 ] CPU C6-Cores [ 0 1 2 3 4 6 7 8 9 10 12 13 14 15 16 17 18 19 ] CPU P-States [ (12) 13 14 16 17 18 20 22 23 27 30 31 32 ] CPU P-States [ 12 13 14 (15) 16 17 18 20 22 23 27 30 31 32 ] CPU P-States [ (12) 13 14 15 16 17 18 20 22 23 25 27 30 31 32 ] CPU P-States [ (12) 13 14 15 16 17 18 20 21 22 23 25 27 30 31 32 ] CPU C6-Cores [ 0 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ] CPU P-States [ 12 13 14 15 16 17 18 20 21 22 23 (24) 25 27 30 31 32 ] CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 30 31 32 ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 29 (30) 31 32 ] CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 36 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 36 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 41 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 41 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 38 41 (42) ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 38 39 41 (42) ] CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 ] CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 ] CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 (42) ]  
      To unload the AppleIntelInfo.kext, enter the terminal command: sudo kextunload AppleIntelInfo.kext  
      E.2) Graphics Configuration
       
      Most ATI GPUs, e.g. RX Vega 64, RX Vega Frontier, RX 580, RX 560 are natively implemented. However, it is commonly recommended not to use RX 560 and RX 580 GPUs due to the lacking iGPU implementation when using SMBIOS iMacPro1,1. Remaining HDMI/DP port errors, hot plug errors and flaws with multi-monitor or 5K display configurations when using ATI Vega GPUs can be fixed by means of VegaGraphicsFixup.kext, kindly provided by @jyavenard. Important comment for all Vega users with 4K monitors though:  when connecting e.g. the Vega Frontier with e.g. the LG 38UC99-W (WUHD, 3840 pix x 1600 pix) via one of the Display Ports (DPs), the screen resolution is fine under both Windows 10 and macOS High Sierra but is totally at odd during boot (VGA like boot screen resolution). @DSM2 reported similar issues with his true 4K display and with both the ASUS Prime X299 Deluxe and the Gigabyte Designare EX. Thus the VEGA DP 4K boot screen resolution issue is neither related with the fact that the LG 38UC99-W is a ultra-wide (3840x1600) and not a true UHD (3840x2160) monitor nor related to any likely apparent issue with the ASUS Prime X299 Deluxe firmware. It is definitely a Vega firmware problem in combination with 4K displays, as the DP 4K boot screen resolution issue is totally absent with my Nvidia GPU and the problem also does not only affect the ASUS Splash Screen but also spreads over the entire boot process until the login screen is reached (Windows and macOS). Splash Screen, Apple logo or verbose boot messages are not stretched but rather have VGA like resolution. Any fix of the AMD vBIOS would be highly appreciated. It is more than disappointing to witness such issues with 1000$ GPUs... Fortunately, the 4K boot screen issue is restricted to the Vega DP ports and likely due to the fact that the LG 38UC99-W only supports DP 1.2. Solution: Connect your Vega and your 4K display via the HDMI port. Although, in the latter case the monitor frequency seems to be limited to 30 Hz, compared with the 60 Hz or 75 Hz under macOS Mojave obtained within a DP connection.
       
      Also Nvidia Kepler Graphics Cards are natively implemented. 
       
      All Users with Nvidia Maxwell and Pascal Graphics Cards Users still have to wait for the official release of 10.14 Web Drivers. Over the last weeks, I was actively requesting Web Driver development for macOS 10.14 Betas from Nvidia. I really hope that Nvidia will not leave us again without Web Driver support until the official release of Mojave by September 2018. In the meanwhile, we have to live with e.g. patched Web Driver xxx.35.106 for macOS High Sierra 10.13.5 after a simple patching procedure detailed below, although the latter Web Driver is not really suited for 10.14 and just works with strong limitations. 
       
      How to patch an Nvidia WebDriver:   Download the Nvidia WebDriver-Payload Repackager from InsanelyMac. Credits to @Chris111 and @Pavo.    The patch procedure is simple and fully described in the implemented Readme.txt and will reveal a Repackaged-WebDriver.pkg, which can be used for installing the patched Nvidia Web Driver xxx.35.106 under macOS Mojave 10.14 DP1 (18A293u).   Nvidia Web Driver Installation and Black Screen Prevention:   Apparently with SMBIOS iMacPro1,1, the Nvidia Black Screen Prevention has become obsolete. Thanks to @fabiosun for this finding. Thus, NvidiaGraphicsFixup.kext, subverting AppleMobileFileIntegrity banning the driver can be theoretically removed from the /EFI/CLOVER/kexts/Other/ directory of your macOS Flash Drive Installer and 10.13 System Disk. However, the most actual releases of NvidiaGraphicsFixup.kext v.1.2.7 and Lilu.kext v1.2.3 apparently help in fixing the Nvidia HDAU implementation and sporadic black screen issues while wake from sleep. Thus, the latter kext combination might still represent potential workarounds for few likely remaining system issues.      a.) Install the patched Nvidia 10.13 Web Driver Package.   b.) Now perform the following additional steps:   i.) Copy /L/E/NVDAStartupWeb.kext to your Desktop.   ii.) Right-click on NVDAStartupWeb.kext and select show package content.   iii.) Change to "Contents" and edit the "Info.plist" with Xcode.   iv.) Go to IOKitPersonalities -> NVDAStartup -> change "NVDARequiredOS" from "17F77" to "18A293u", the corresponding build number of MacOS Mojave 10.14 DP1.   v.) Save the "Info.plist" file and copy the modified "NVDAStartupWeb.kext" to /L/E/ with root permission.   vi.) Open a terminal and enter the following commands: sudo chmod -R 755 /Library/Extensions/NVDAStartupWeb.kext sudo chown -R root:wheel /Library/Extensions/NVDAStartupWeb.kext sudo touch /System/Library/Extensions && sudo kextcache -u / sudo touch /Library/Extensions && sudo kextcache -u /  
      vii.) Reboot.
        viii.) The patched Web Driver might not be active yet. Therefore, open the Nvidia Driver Manager and select "Nvidia Web Driver".   ix.) Now reboot as requested and you will have a fully functional patched Web Driver for MacOS Mojave 10.14 DP1 (18A293u).  
       
      E.3) Audio Configuration
       
      EFI-X99-10.14-DP1-Release-iMacPro1,1-160618 contains an already fully functional AppleALC audio configuration. The latter consist of:
       
      1.) codeccommander.kext,  AppleALC.kext v1.2.7 and Lilu.kext v1.2.3 in "/EFI/CLOVER/kexts/Other/
       
      2.) Boot flags "-alcbeta", "alcid=5", "alcaaplid=5", and "-lilubetaall" in the config.plist under "Custom Flags" in Section "Boot" of Clover configurator. 
       
       
       
      3.)  Note that ALZA -> HDEF ACPI patch needs to be added to the config.plist in Section "ACPI" of Clover Configurator, in case one does not use the adopted system SSDT discussed in Section 9.2).    
      Comment:                Find:           Replace: ALZA -> HDEF     414c5a41        48444546  
      4.) Audio ID Injection "5" in the config.plist under Audio/Inject in Section "Devices" of Clover Configurator. 
          This audio configuration provides a correct analogue onboard audio chipset system implementation.    The correct digital HDMI/DP HDAU PCI device implementation will be detailed in Section E.9) in line with the HDEF and GPU PCI device implementation.   Thanks to @nmano for helping me with the initial AppleALC audio setup for 10.14 Mojave.   
      E.4) USB Configuration    With AppleIntelPCHPMC, Apple should properly implement all external and internal XHC USB 3.0 (USB 3.1 Gen 1 Type-A) and USB 2.0 (USB 2.0 Gen 1 Type-A) ports.  All external and internal USB 3.1 (USB 3.1 Gen 2 Type-A and Type-C) ports are natively implemented on different controllers than XHC.   All ASUS A99-A II users, not content with the XHC USB implementation,  can download, unzip and use my board-specific XHC USB Kext KGP-ASUS-X99-A-II-iMacPro-XHCI.kext.zip in /EFI/Clover/kexts/Other/. All users of mainboards different from the ASUS X99-A II, can create their own board specific XHC USB kext by following my XHC USB Kext Creation guide line in the other forum.    Note that in addition one needs to implement the XHC USB port limit patch in the config.plist under "KextsToPatch"  in Section "Kernel and Kext Patches" of Clover Configurator, as else not all available XHC USB ports will be implemented. Name*          Find*[Hex]             Replace* [Hex]         Comment com.apple.driver.usb.AppleUSBXHCI   83FB0F0F 83090500 00   83FB0F90 90909090 90   USB Port Limit Patch ©PMHeart Many thanks to @PMheart from InsanelyMac for providing the respective 10.14 XHC USB port limit patch detailed above.
       
       
      E.5) M.2/NVMe Configuration
       
      In contrary to macOS Sierra 10.12, and like already in case of macOS High Sierra 10.13, also macOS 10.14 Mojave provides native support of non-4Kn NVMe SSDs, like my Samsung EVO 960 M.2/NVMe. All patches applied under macOS Sierra 10.12 are obsolete. The native support of non-4Kn NVMe SSDs enables the unique opportunity to directly perform a clean-install of macOS High Sierra 10.13 on M.2 NVMEs like the Samsung EVO 960.   The only current drawback consists in the external drive implementation of NVMEs. This minor issue should be easily solved by adding the actual External NVME Icon KextToPatch entry to the config.plist by means of the Clover Configurator. [code] Name*            Find* [HEX]           Replace* [HEX]        Comment IONVMeFamily     4885c074 07808b20     4885c090 90808b20     External NVME Icon Patch[/code] Not however that within the actual 10.14 Mojave distribution, this approach does not seem to work anymore, despite the KextToPatch entry detailed above. If you still have your NVMe implemented in form of an external drive you have to perform the following workaround, detailed below.
        1.) Disable the not working External NVME Icon KextToPatch entry.   2.) Open the IORegistryExplorer, in the upright search field type nvme and take not of values in the left column, i.e. indicated as v.1, v.2 and v.3 and marked by red rectangles in the figure below. As you can see by following these entries, your nvme device shows up in PCI0@0 > BR1B@1,1 > H000@0     3.) Download and unzip the SSDT-NVMe-extern-icon-patch.aml.zip, and open the SSDT-NVMe-extern-icon-patch.aml with MaciASL-DSDT.app, both attached towards the end of this guide. For deviating system configurations, replace the values highlighted in blue color in the figure below with those of your IOReg, marked by red rectangles and indicated by v.1, v.2 and v.3 in the figure of my IOReg above.     4.) Save and copy the modified SSDT-NVMe-extern-icon-patch.aml to the /EFI/CLOVER/ACPI/patched/ folder of your system drive.   5.) Reboot   Now your NVMe drive should correctly show up as internal.  
       
      E.6) SSDT/NVMe TRIM Support 
        Macs only enable TRIM for Apple-provided solid-state drives they come with. If you upgrade a Mac with an aftermarket SSD/NVMe, the Mac won’t use TRIM with it. The same applies for SSDs/NVMes used by a Hackintosh. When an operating system uses TRIM with a solid-state drive, it sends a signal to the SSD/NVMe every time you delete a file. The SSD/NVMe knows that the file is deleted and it can erase the file’s data from its flash storage. With flash memory, it’s faster to write to empty memory — to write to full memory, the memory must first be erased and then written to. This causes your SSD/NVMe to slow down over time unless TRIM is enabled. TRIM ensures the physical NAND memory locations containing deleted files are erased before you need to write to them. The SSD/NVMe can then manage its available storage more intelligently.   Note that the config.plist in the EFI-folder of EFI-X99-10.14-DP1-Release-iMacPro1,1-160618 attached towards the end of this guide, contains an SSD/NVMe "TRIM Enabler" KextsToPatch entry, which can be found in the " Kernel and Kext Patches" Section of the Clover Configurator.     Name*                   Find*[HEX]                  Replace*[HEX]               Comment IOAHCIBlockStorage      4150504c 45205353 4400      00000000 00000000 0000      Trim Enabler  
      With this KextToPatch entry, SSD/NVMe TRIM should be  fully enabled on your 10.13 System. See your Apple's System Report.  
      E.7) Thunderbolt EX 3 PCIe Add-On Implementation 
       
       
      For the successful implementation of the Thunderbolt EX3 PCIe Add-On Adapter, a fully working Dual Boot System with an UEFI Windows Implementation is unfortunately absolutely mandatory. You will not be able to configure your Thunderbolt EX3 PCIe Add-On Adapter in the mainboard BIOS, until the Adapter has been successfully recognised and initialised by the UEFI Windows System. Fortunately legal and official License Keys for the actual Windows 10 Pro distribution can be purchased with a little bit of temporal effort on Google for an actual price of 20 $ or even below! Thus, the installation of a dual boot system with Windows will require some additional temporal user effort but will not noticeably further affect the users's budget.   Please note that I especially emphasize the term UEFI, when speaking about the parallel Windows implementation. Don't use or perform a Legacy Implementation of Windows! In order to properly implement your Windows partition later-on in the Clover Bootloader and to comply with the actual Mainbaord-BIOS settings requirements, it is absolutely mandatory to run or perform an UEFI Windows implementation!   So if not already implemented, how to achieve a fully working UEFI Windows Implementation and Dual boot System with Windows?   1.) Important Note! For the implementation of the UEFI Windows Distribution disconnect all usually plugged macOSDrives from your rig! The Windows installer will implement a Windows Boot Loader! If you have any macOS Drive connected during installation, the latter Windows Boot Loader might overwrite and destroy your current Clover Boot Loader. This is the last thing you want! Thus for the windows installation just connect the destination drive for the installation and the Windows USB Flash Drive Installer your will create in the subsequent step below!   2.) This Tutorial explains in all necessary detail how to download an actual Windows 10 Creator distribution,  and how tosubsequently create a bootable USB Flash Drive Installer for a subsequent UEFI Windows 10 installation by means RUFUS! Don't put emphasis on alternative optional methods and always take care that you just follow the instructions for a successful subsequent UEFI Windows Installation!   3.) This Tutorial explains in all necessary detail how to properly perform the actual Windows 10 Pro Creator UEFIInstallation, subsequent to the a bootable Windows USB Flash Drive Installer realisation detailed in 2.) above.   4.) This Tutorial explains in all necessary detail, how to migrate/clone/backup your Windows 10 UEFI System Disk afterinstallation for future maintenance and safety.   5.) After successfully performing the UEFI Windows 10 Pro Creator Implementation, you can reconnect your macOS driveto your rig. The newly created UEFI Windows 10 Pro Creator Partition will automatically appear as a further boot option in both BIOS Boot Option Menu (F8) and Clover Boot Menu! No additional or further actions or measurements have to be taken!   6.) Once your Windows 10 Pro Creator Partition is fully operational, install all mainboard drivers and programs implemented on the DVD attached to your mainboard.    7.) Now switch of your rig and start with the installation of the Thunderbolt EX3 PCIe Add-On Adapter   a.) I recommend to install the adapter in third PCIe Slot from the bottom which is PCIEX_3   b.) For full TB hot plug functionality skip or remove the THB_C cable between the TBEX 3 and the respective mainboard connector.   8.) Reboot into windows and install the ASUS ThunderboltEX 3 DVD.   9.) Reboot and enter the Mainboard BIOS (F2)   Go to /Advanced/ Thunderbolt(TM) Configuration/ and apply the following BIOS Settings detailed below:     10.) Shut down your rig, connect the Thunderbolt Device with the Thunderbolt EX3 Adaptor and boot   11.) You are done!  Your Thunderbolt EX3 PCIe Adapter and connected devices should be now fully implemented and functional.   12.) We will add TB XHC USB and TB Hot Plug functionality by means of the SSDT-TB3-iMacPro-KGP.aml.zip implemented and described in Section E.9.3) of this guide.   E.8) Gigabit and 10-Gbit Ethernet Implementations    Section E.8.1) and and E.8.2.) below, describe in all necessary detail how to gain full Gbit and 10-Gbit LAN functionality on X99 systems.  
      E.8.1) ASUS X99-A onboard Gbit functionality   
       
      The Intel I218-V2 Gigabit on-board LAN controller of the ASUS X99-A II is implemented by means of IntelMausiEthernet.kext (already part of my EFI-Folder distributions).
       
      E.8.2) 10-Gbit Lan Implementations  
       
      E.8.2.1) ASUS XG-C100C Aquantia AQC 10-Gbit NIC   
       
      Starting with 10.13.2, there is native support for Aquantia based 10GBit network cards, which are implemented by means of a Apple Vanilla kext called "AppleEthernetAquantiaAqtion.kext", which is further part of "IONetworkingFamily.kext/Contents/PlugIns/" placed in  /System/Library/Extensions/ (credits to @mikeboss). First success with the ASUS XG-C100C under MacOS 10.13.3 has been reported by @d5aqoep. @Mieze finally came up with a AppleEthernetAquantiaAqtion KextPatch for the use of the ASUS XG-C100C also under 10.13.4 and and later macOS versions.   For further information and discussion see  . 
      How to successfully implement the ASUS XG-C100C AQC107 PCIe x4 10GBit Ethernet Adapter:   1.) A temporal macOS High Sierra 10.13.3 (17D2047 in case of the iMac Pro) installation is absolutely mandatory at first place. Only within the latter macOS High Sierra build, the ASUS XG-C100C will receive the proper AQC107 Apple firmware to be recognised and fully implemented by OSX. The firmware update will be performed during system boot. Several boot intents might be necessary until the firmware update finally succeeds. Only subsequently, the ASUS XG-C100C will be natively implemented in macOS High Sierra 10.13.3 and fully functional.   2.) To finally use the ASUS XG-C100C with macOS builds >10.13.4, one has to implement the following AppleEthernetAquantiaAqtion KextPatch provided by [USER=389154]@Mieze[/USER]:     Name*                            Find*[HEX]         Replace*[HEX]      Comment AppleEthernetAquantiaAqtion      0F84C003 0000      90909090 9090      Aquantia patch ©Mieze     3.) The proper XGBE ASUS XG-C100C PCI SSDT implementation is detailed in Section E.9.2)   4.) Note that after the firmware update under macOS High Sierra 10.13.3, the ASUS XG-C100C will refuse the official Windows Lan drivers provided by ASUS and will only work with Apple's customised Aquantia64.zip boot camp drivers attached below.   E.8.2.2) Intel X540-T1 10-Gbit NIC      Thanks to some Ubuntu EEPROM modding, I also achieved the successful implementation of the Intel X540-T1 single port 10GB LAN PCIe Adapter by means of the Small-Tree 10GB macOS 10.13 driver.   Important additional notes to the EEPROM modding guideline linked above can be assessed in Section E.8.2.2) of my iMac Pro Skylake-XX299 macOS 10.14 Mojave Build and Desktop guide.   The proper Intel X540-T1 PCI SSDT implementation is detailed in Section E.9.2)   E.8.2.3) Small-Tree P2EI0G-2T 10-GBit NIC     
      The Small-Tree P2EI0G-2T 2-Port 10GB LAN PCIe Adapter constitutes now the actual base line in my iMac Pro X299 10Gbit LAN configuration. It works OoB with the Small-Tree 10GB macOS 10.13 driver.   The proper Small-Tree P2EI0G-2T PCI SSDT implementation is detailed in Section E.9.2)   E.8.2.4) NetGear ProSave XS508M 8-port 10-Gbit Switch     
      As already mentioned above, the NetGear ProSave XS508M 8-port 10GBit switch constitutes the turntable of my 10-GBit Ethernet Network. It further connects with a QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port.
       
      E.8.2.5) QNAP TS-431X2 Quad-core 4-Bay NAS
       
      The QNAP TS-431X2 Quad-core 4-Bay NAS tower finally harbours 4x 12 TB Seagate IronWolf drives in RAID 0 configuration (as I rather opt for read/write speed than redundancy).
       
      E.8.2.5) 10-Gbit Ethernet Optimization
       
      1.) Use SMB 3.0 instead of AFS for your Ethernet communication. 2.) Enable Jumbo Frames on your NAS and macOS network settings. 3.) The service order in your macOS network settings should have your 10-Gbit NIC at first position. 4.) You can turn off the SMB packet signing of the client and server in a secure network.   Incoming SMB   Enter the following terminal commands: sudo -s
 echo "[default]" >> /etc/nsmb.conf 
echo "signing_required=no" >> /etc/nsmb.conf 
exit  
      Outgoing SMB:   Enter the following terminal commands: smbutil statshares -a sudo defaults write /Library/Preferences/SystemConfiguration/com.apple.smb.server SigningRequired 0  
       
      E.9) ASUS X99-A II PCI Device Implementation
       
      In order to properly implement all PCI device drivers on his/her system and build, one needs adequate ACPI DSDT Replacements and a sophisticated SSDT. Both requirements have been originally successfully implemented for the ASUS Prime X299 Deluxe by our gorgeous @apfelnico with partial contributions of @TheOfficialGypsy. Many thanks for the extensive efforts and extremely fruitful and brilliant work! Subsequently, I adopted the ACPI DSDT Replacement Patches and SSDT in concordance with SMBIOS iMacPro1,1 for both the ASUS Prime X299 Deluxe and the ASUS X99-A II. The actual ASUS X99-A II ACPI DSDT Replacements are part of the config.plist contained in EFI-X99-10.14-DP1-Release-iMacPro1,1-160618. The SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml for the ASUS X99-A II, further developed with @apfelnico and @nmano, are attached at the bottom of this originating post/guide.   Note that the ACPI DSDT Replacements, SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml can be build and PCIe slot population dependend and have to be verified and likely adopted or modified for all mainboards different from the ASUS X99-A II and builds or PCIe slot populations different from the one that constitutes the baseline of this guide.   For the ASUS X99-A II I will use in the following the PCIe Slot nomenclature depicted below:  

       
      The verification and likely adaptation/modification can be performed by the help of IORegistryExplorer v1.2.
       
      Important Note: It is strongly recommend to perform a stepwise PCI Device implementation by means of a minimalistic starter SSDT-X99-iMacPro.aml, which just contains the Definition Block and Device Implementation for one single specific device. Once this PCI device has been successfully implemented, other PCI Device definitions can be added to the SSDT-X99-iMacPro.aml. In case that subsequently the implementation of a specific PCI Device would be erroneous and fail, also all other already successfully implemented PCI devices would disappear from Section "PCI" of Apple's System report and the entire "PCI" Device implementation would fail. Thus a stepwise PCI device implementation/adaptation is highly recommended and sometimes deemed necessary!
       
      Also keep always in mind to modify/adopt the ACPI replacements in your config.plist in parallel when ever necessary!   Note once more that the ACPI DSDT Replacements, SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml detailed below require SMBIOS iMacPro1,1.   E.9.1) ACPI DSDT Replacement Implementation  
      Note once more that all required ACPI DSDT Replacements are already implemented in the config.plist in the /EFI/CLOVER/ directory of the EFI-Folder contained in EFI-X99-10.14-DP1-Release-iMacPro1,1-160618 or are directly part of the SSDT-X99-iMacPro.aml and SSDT-X99-TB3-iMacPro-KGP.aml. In the config.plist, the ACPI DSDT Replacements are disabled by default, thus we will now open the config.plist in the /EFI/CLOVER/ directory of your 10.13 System Disk EFI-Folder with Clover Configurator and stepwise adopt (if necessary) and enable the different required DSDT replacement patches in Clover Configurator Section "ACPI" under "DSDT patches", by also discussing their respective function and impact.   a.) OSI -> XOSI and EC0_ -> EC__ or H_EC  -> EC__ are DSDT replacement patches to achieve consistency with a real Mac variable naming.   i.) The XOSI functionality is required as explained by @RehabMan. Thus please enable the OSI -> XOSI DSDT Replacement patch.   ii.) On the ASUS X99-A II and ASUS X99 Deluxe II we have EC0 and H_EC controllers, which have to be renamed to 'EC' for proper USB power management. Thus enable both EC0_ -> EC__  and H_EC  -> EC__ DSDT Replacement Patches. Comment:             Find*[Hex]      Replace [Hex] OSI -> XOSI          5f4f5349        584f5349 EC0_ -> EC__         4543305f        45435f5f H_EC  -> EC__        485f4543        45435f5f  
      b.) The HEC1 -> IMEI and IDER->MEID DSDT Replacement patches are Intel Management Engine Interface related and are vital as MacOS requires the variable names "IMEI" and "MEID" to load the 'AppleIntelMEIDriver'. The latter functionality solves the 'iTunes/Apple Store Content Access Problem' which is discussed here. Please enable now both DSDT Replacement patches independent from your mainboard. Comment:             Find*[Hex]       Replace [Hex] HECI -> IMEI         48454331         494d4549 IDER->MEID           49444552         4d454944  
      c.) The LPC0 -> LPCB DSDT Replacement Patch is AppleLPC and SMBus related and is applied for consistency with the variable naming on a real Mac.   Please enable now this DSDT replacement patch independent from your mainboard. Comment:             Find*[Hex]         Replace [Hex] LPC0 -> LPCB         4c504330           4c504342  
      d.) FPU_->MATH, TMR_->TIMR, PIC_->IPIC are all DSDT Replacement Patches for consistency with the variable naming on a real Mac. The variables are however functionless on either X99 systems or real Macs.   Please enable now all three DSDT Replacement Patches independent from your mainboard. Comment:             Find*[Hex]        Replace [Hex] FPU_ -> MATH         4650555f          4d415448 TMR_ -> TIMR         544d525f          54494d52 PIC_ -> IPIC         5049435f          49504943  
      e.) The DSM -> XDSM DSDT replacement patch will be vital for loading the SSDT-ASUS-X99-A-II.aml, as all DSM methods used in the original DSDT do have a not compatible structure totally different from the real Mac environment. Without any fix, all DSM methods would be simply ignored. Note that one single device can have only one DSM method, which can assign additional properties to the respective device. Thus please enable the latter DSDT replacement patch completely independent from your mainboard! Comment:             Find*[Hex]         Replace [Hex] _DSM -> XDSM         5f44534d            5844534d  
      f.) The 48 CPxx -> PRxx replacements are i7-6950X specific and result in a proper CPU core reordering as well as in a iMac Pro specific CPU core variable naming.   All i7-6950X users can now enable all 48 CPxx -> PRxx replacements. All users of CPUs different from the i7-6950X have to adopt/modify the 48 CPxx -> PRxx replacements in concordance with their original IOREG CPU core values. Comment:             Find*[Hex]        Replace [Hex] CP00 -> PR00         43503030          50523030 CP01 -> PR01         43503031          50523031 CP02 -> PR02         43503032          50523032 CP03 -> PR03         43503033          50523033 CP04 -> PR04         43503034          50523034 CP05 -> PR05         43503035          50523035 CP06 -> PR06         43503036          50523036 CP07 -> PR07         43503037          50523037 CP08 -> PR08         43503038          50523038 CP09 -> PR09         43503039          50523039 CP0A -> PR10         43503041          50523130 CP0B -> PR11         43503042          50523131 CP0C -> PR12         43503043          50523132 CP0D -> PR13         43503044          50523133 CP0E -> PR14         43503045          50523134 CP0F -> PR15         43503046          50523135 CP10 -> PR16         43503130          50523136 CP11 -> PR17         43503131          50523137 CP12 -> PR18         43503132          50523138 CP13 -> PR19         43503133          50523139 CP14 -> PR20         43503134          50523230 CP15 -> PR21         43503135          50523231 CP16 -> PR22         43503136          50523232 CP17 -> PR23         43503137          50523233 CP18 -> PR24         43503138          50523234 CP19 -> PR25         43503139          50523235 CP1A -> PR26         43503141          50523236 CP1B -> PR27         43503142          50523237 CP1C -> PR28         43503143          50523238 CP1D -> PR29         43503144          50523239 CP1E -> PR30         43503145          50523330 CP1F -> PR31         43503146          50523331 CP20 -> PR32         43503230          50523332 CP21 -> PR33         43503231          50523333 CP22 -> PR34         43503232          50523334 CP23 -> PR35         43503233          50523335 CP24 -> PR36         43503234          50523336 CP25 -> PR37         43503235          50523337 CP26 -> PR38         43503236          50523338 CP27 -> PR39         43503237          50523339 CP28 -> PR40         43503238          50523430 CP29 -> PR41         43503239          50523431 CP2A -> PR42         43503241          50523432 CP2B -> PR43         43503242          50523433 CP2C -> PR44         43503243          50523434 CP2D -> PR45         43503244          50523435 CP2E -> PR46         43503245          50523436 CP2F -> PR47         43503246          50523437  
      Resulting CPU Core Implementation  

       
      E.9.2) SSDT-ASUS-X99-A-II.aml PCI Device Implementation 
       

       
      For the proper PCI device driver implementation (detailed in the Figure above), which is mostly directly related with the PCI device functionality, we now have to revise and likely adopt or modify the attached SSDT-X99-iMacPro.aml to our specific build, system configuration and PCIe slot population with the help of the IORegistryExplorer.   Note that for each device, the SSDT-ASUS-X99-A-II.aml contains a DefinitionBlock entry and the underlying PCI device implementation. In case of necessary modifications/adaptations, don't forget to also modify/adapt the respective DefinitionBlock entries in concordance with your IOREG entries. The entire SSDT structure is module like. Each module can be independently added, changed or removed in dependence of your specific build, needs and requirements. A stepwise implementation of the individual PCI devices is recommended!   E.9.2.1) HDEF - onboard Audio Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0, DeviceObj)    // (from opcode) External (_SB_.PCI0.ALZA, DeviceObj)    // (from opcode)  
      PCI Device Implementation:   Scope (\_SB.PCI0) { Scope (ALZA) { Name (_STA, Zero) // _STA: Status } Device (HDEF) { Name (_ADR, 0x001B0000) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x16) { "alc-layout-id", Buffer (0x04) { 0x05, 0x00, 0x00, 0x00 }, "MaximumBootBeepVolume", Buffer (One) { 0xEF }, "MaximumBootBeepVolumeAlt", Buffer (One) { 0xF1 }, "multiEQDevicePresence", Buffer (0x04) { 0x0C, 0x00, 0x01, 0x00 }, "AAPL,slot-name", Buffer (0x09) { "Built In" }, "model", Buffer (0x17) { "ASUS X99-A II HD Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-1" }, "built-in", Buffer (0x05) { "0x00" }, "device_type", Buffer (0x14) { "HD Audio Controller" }, "name", Buffer (0x22) { "Realtek ALC 1150 Audio Controller" }, "PinConfigurations", Buffer (Zero) {} }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } }  
        The HDEF PCI device implementation is valid for the ASUS X99-A II and likely for all other mainboards with the Realtek ALC 1150 Audio Controller chipset. It is a build in device and does not have any slot specific dependency. Note the ALZA -> HDEF ACPI Replacement within the SSDT! Thanks to @nmano for providing the correct alc-layout-id for macOS 10.14 Mojave.    E.9.2.2) GFX0, HDAU - Nvidia Graphics Card and HDMI/DP Audio PCI implementation 
       
      DefintionBlock entry:
      External (_SB_.PCI0.BR3A, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.H001, DeviceObj)    // (from opcode)  
        PCI Device Implementation: Scope (_SB.PCI0.BR3C)     {         Device (GFX0)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x14)                     {                         "built-in",                         Buffer (One)                         {                              0x00                                           },                         "device-id",                         Buffer (0x04)                         {                              0x06, 0x1B, 0x00, 0x00                         },                         "hda-gfx",                         Buffer (0x0A)                         {                             "onboard-2"                         },                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-1"                         },                         "@0,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@1,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@2,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@3,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@4,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         },                         "@5,connector-type",                         Buffer (0x04)                         {                              0x00, 0x08, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }         Device (HDAU)         {             Name (_ADR, One)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0C)                     {                         "built-in",                         Buffer (One)                         {                              0x00                                           },                         "device-id",                         Buffer (0x04)                         {                              0xEF, 0x10, 0x00, 0x00                         },                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-1"                         },                         "device_type",                         Buffer (0x16)                         {                             "Multimedia Controller"                         },                         "name",                         Buffer (0x1D)                         {                             "NVIDIA High Definition Audio"                         },                         "hda-gfx",                         Buffer (0x0A)                         {                             "onboard-2"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }     Name (_SB.PCI0.BR3C.H000._STA, Zero)  // _STA: Status     Name (_SB.PCI0.BR3C.H001._STA, Zero)  // _STA: Status     Name (_SB.PCI0.BR3C.D07C._STA, Zero)  // _STA: Status  
      The actual GFX0 and HDAU PCI device implementation is valid for SMBIOS iMacPro1,1 (GFX0) and any Nvidia Graphics Card implemented in PCIe Slot 1.   It is a build and PCIe slot population dependent device implementation. Nvidia Graphics Card users with more than one graphics card, or with an Nvidia graphics card in a PCIe slot different from PCIe Slot 0, will have to adopt the respective PCI0, BR3A, H000, H001, D07C, GFX1 device path entries following their respective IOREG entries. Note the H000 -> H001, H001 ->D07C and D07C -> GFX0 ACPI replacements within the SSDT!   Also note that with 10.13.4, Apple changed the com.apple.driver.AppleHDAController implementation. To make the NVIDIA HDAU PCI device driver work for e.g. a GeForce GTX 1080, one needs to add the following KextToPatch entry in Section "Kernel and kext Patches" of Clover Configurator, as already implemented in the config.plist contained in EFI-X99-10.14-DP1-Release-iMacPro1,1-160618: Name*                                 Find* [HEX]         Replace* [HEX]        Comment com.apple.driver.AppleHDAController   DE100B0E            DE10EF10              FredWst DP/HDMI patch  
      Credits to @FreedWst and thanks to @fabiosun for pointing me to this solution. The KextToPatch entry might defer for Nvidia GPUs different from the Geforce GTX 1080.   Users of NvidiaGraphicsfixup.kext v1.2.6 and above might be able to drop this KextToPatch entry, as the latter kext already properly implements the Nvidia HDAU PCI driver.   Below one finds an example of @apfelnico for a GFX and HDAU PCI implementation of 1x Radeon Vega Frontier in PCIe Slot 1:   DefintionBlock entry: External (_SB_.PCI0.BR3A, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H001, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.BR3A) { Scope (H000) { Name (_STA, Zero) // _STA: Status } Scope (H001) { Name (_STA, Zero) // _STA: Status } Scope (D07C) { Name (_STA, Zero) // _STA: Status } Device (PEGP) { Name (_ADR, Zero) // _ADR: Address Device (EGP0) { Name (_ADR, Zero) // _ADR: Address Device (GFX0) { Name (_ADR, Zero) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x18) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "model", Buffer (0x16) { "Vega Frontier Edition" }, "name", Buffer (0x08) { "ATY_GPU" }, "@0,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@1,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@2,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@3,connector-type", Buffer (0x04) { 0x00, 0x08, 0x00, 0x00 }, "@0,name", Buffer (0x0D) { "ATY,Kamarang" }, "@1,name", Buffer (0x0D) { "ATY,Kamarang" }, "@2,name", Buffer (0x0D) { "ATY,Kamarang" }, "@3,name", Buffer (0x0D) { "ATY,Kamarang" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (HDAU) { Name (_ADR, One) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0A) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "name", Buffer (0x1F) { "Vega Frontier Edition HD-Audio" }, "model", Buffer (0x1F) { "Vega Frontier Edition HD-Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } } } }  
      as well as one example of @apfelnico for the GFX and HDAU PCI implementation of 1x Radeon Vega 64 in PCIe Slot 1, pimped to 1442 Mhz:
       
      DefintionBlock entry: External (_SB_.PCI0.BR3A, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.H001, DeviceObj) // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.BR3A) { Scope (H000) { Name (_STA, Zero) // _STA: Status } Scope (H001) { Name (_STA, Zero) // _STA: Status } Scope (D07C) { Name (_STA, Zero) // _STA: Status } Device (PEGP) { Name (_ADR, Zero) // _ADR: Address Device (EGP0) { Name (_ADR, Zero) // _ADR: Address Device (GFX0) { Name (_ADR, Zero) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x20) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "model", Buffer (0x12) { "Radeon RX Vega 64" }, "name", Buffer (0x08) { "ATY_GPU" }, "@0,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@1,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@2,connector-type", Buffer (0x04) { 0x00, 0x04, 0x00, 0x00 }, "@3,connector-type", Buffer (0x04) { 0x00, 0x08, 0x00, 0x00 }, "@0,name", Buffer (0x0D) { "ATY,Kamarang" }, "@1,name", Buffer (0x0D) { "ATY,Kamarang" }, "@2,name", Buffer (0x0D) { "ATY,Kamarang" }, "@3,name", Buffer (0x0D) { "ATY,Kamarang" }, "PP_PhmSoftPowerPlayTable", Buffer (One) { /* 0000 */ 0xB6, 0x02, 0x08, 0x01, 0x00, 0x5C, 0x00, 0xE1, /* 0008 */ 0x06, 0x00, 0x00, 0xEE, 0x2B, 0x00, 0x00, 0x1B, /* 0010 */ 0x00, 0x48, 0x00, 0x00, 0x00, 0x80, 0xA9, 0x03, /* 0018 */ 0x00, 0xF0, 0x49, 0x02, 0x00, 0x8E, 0x00, 0x08, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0028 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, /* 0030 */ 0x5C, 0x00, 0x4F, 0x02, 0x46, 0x02, 0x94, 0x00, /* 0038 */ 0x9E, 0x01, 0xBE, 0x00, 0x28, 0x01, 0x7A, 0x00, /* 0040 */ 0x8C, 0x00, 0xBC, 0x01, 0x00, 0x00, 0x00, 0x00, /* 0048 */ 0x72, 0x02, 0x00, 0x00, 0x90, 0x00, 0xA8, 0x02, /* 0050 */ 0x6D, 0x01, 0x43, 0x01, 0x97, 0x01, 0xF0, 0x49, /* 0058 */ 0x02, 0x00, 0x71, 0x02, 0x02, 0x02, 0x00, 0x00, /* 0060 */ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, /* 0068 */ 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x07, 0x00, /* 0070 */ 0x03, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0078 */ 0x00, 0x00, 0x01, 0x08, 0x84, 0x03, 0x84, 0x03, /* 0080 */ 0xB6, 0x03, 0xE8, 0x03, 0x1A, 0x04, 0x4C, 0x04, /* 0088 */ 0x60, 0x04, 0x7E, 0x04, 0x01, 0x01, 0x33, 0x04, /* 0090 */ 0x01, 0x01, 0x84, 0x03, 0x00, 0x08, 0x60, 0xEA, /* 0098 */ 0x00, 0x00, 0x00, 0x40, 0x19, 0x01, 0x00, 0x01, /* 00A0 */ 0x80, 0x38, 0x01, 0x00, 0x02, 0xDC, 0x4A, 0x01, /* 00A8 */ 0x00, 0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0x00, /* 00B0 */ 0x77, 0x01, 0x00, 0x05, 0x90, 0x91, 0x01, 0x00, /* 00B8 */ 0x06, 0x50, 0xBD, 0x01, 0x00, 0x07, 0x01, 0x08, /* 00C0 */ 0xD0, 0x4C, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00, /* 00C8 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x8D, 0x01, /* 00D0 */ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00D8 */ 0x00, 0x00, 0xDC, 0xC7, 0x01, 0x00, 0x02, 0x00, /* 00E0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, /* 00E8 */ 0xFC, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* 00F0 */ 0x00, 0x00, 0x00, 0x00, 0xD8, 0x1B, 0x02, 0x00, /* 00F8 */ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0100 */ 0x00, 0xF4, 0x40, 0x02, 0x00, 0x05, 0x00, 0x00, /* 0108 */ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1C, 0x64, /* 0110 */ 0x02, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x01, /* 0118 */ 0x00, 0x00, 0x00, 0x68, 0x81, 0x02, 0x00, 0x07, /* 0120 */ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* 0128 */ 0x00, 0x05, 0x60, 0xEA, 0x00, 0x00, 0x00, 0x40, /* 0130 */ 0x19, 0x01, 0x00, 0x00, 0x80, 0x38, 0x01, 0x00, /* 0138 */ 0x00, 0xDC, 0x4A, 0x01, 0x00, 0x00, 0x90, 0x5F, /* 0140 */ 0x01, 0x00, 0x00, 0x00, 0x08, 0x28, 0x6E, 0x00, /* 0148 */ 0x00, 0x00, 0x2C, 0xC9, 0x00, 0x00, 0x01, 0xF8, /* 0150 */ 0x0B, 0x01, 0x00, 0x02, 0x80, 0x38, 0x01, 0x00, /* 0158 */ 0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0xF4, 0x91, /* 0160 */ 0x01, 0x00, 0x05, 0xD0, 0xB0, 0x01, 0x00, 0x06, /* 0168 */ 0x38, 0xC1, 0x01, 0x00, 0x07, 0x00, 0x08, 0x6C, /* 0170 */ 0x39, 0x00, 0x00, 0x00, 0x24, 0x5E, 0x00, 0x00, /* 0178 */ 0x01, 0xFC, 0x85, 0x00, 0x00, 0x02, 0xAC, 0xBC, /* 0180 */ 0x00, 0x00, 0x03, 0x34, 0xD0, 0x00, 0x00, 0x04, /* 0188 */ 0x68, 0x6E, 0x01, 0x00, 0x05, 0x08, 0x97, 0x01, /* 0190 */ 0x00, 0x06, 0xB0, 0xAD, 0x01, 0x00, 0x07, 0x00, /* 0198 */ 0x01, 0x68, 0x3C, 0x01, 0x00, 0x00, 0x01, 0x04, /* 01A0 */ 0x3C, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, /* 01A8 */ 0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x38, /* 01B0 */ 0x01, 0x00, 0x02, 0x00, 0x00, 0x34, 0x98, 0x01, /* 01B8 */ 0x00, 0x04, 0x00, 0x00, 0x01, 0x08, 0x00, 0x98, /* 01C0 */ 0x85, 0x00, 0x00, 0x40, 0xB5, 0x00, 0x00, 0x60, /* 01C8 */ 0xEA, 0x00, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01, /* 01D0 */ 0x80, 0xBB, 0x00, 0x00, 0x60, 0xEA, 0x00, 0x00, /* 01D8 */ 0x94, 0x0B, 0x01, 0x00, 0x50, 0xC3, 0x00, 0x00, /* 01E0 */ 0x02, 0x00, 0xE1, 0x00, 0x00, 0x94, 0x0B, 0x01, /* 01E8 */ 0x00, 0x40, 0x19, 0x01, 0x00, 0x50, 0xC3, 0x00, /* 01F0 */ 0x00, 0x03, 0x78, 0xFF, 0x00, 0x00, 0x40, 0x19, /* 01F8 */ 0x01, 0x00, 0x88, 0x26, 0x01, 0x00, 0x50, 0xC3, /* 0200 */ 0x00, 0x00, 0x04, 0x40, 0x19, 0x01, 0x00, 0x80, /* 0208 */ 0x38, 0x01, 0x00, 0x80, 0x38, 0x01, 0x00, 0x50, /* 0210 */ 0xC3, 0x00, 0x00, 0x05, 0x80, 0x38, 0x01, 0x00, /* 0218 */ 0xDC, 0x4A, 0x01, 0x00, 0xDC, 0x4A, 0x01, 0x00, /* 0220 */ 0x50, 0xC3, 0x00, 0x00, 0x06, 0x00, 0x77, 0x01, /* 0228 */ 0x00, 0x00, 0x77, 0x01, 0x00, 0x90, 0x5F, 0x01, /* 0230 */ 0x00, 0x50, 0xC3, 0x00, 0x00, 0x07, 0x90, 0x91, /* 0238 */ 0x01, 0x00, 0x90, 0x91, 0x01, 0x00, 0x00, 0x77, /* 0240 */ 0x01, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01, 0x18, /* 0248 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, /* 0250 */ 0x00, 0x00, 0xBC, 0x02, 0x48, 0x26, 0x46, 0x00, /* 0258 */ 0x0A, 0x00, 0x54, 0x03, 0x90, 0x01, 0x90, 0x01, /* 0260 */ 0x90, 0x01, 0x90, 0x01, 0x90, 0x01, 0x90, 0x01, /* 0268 */ 0x90, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, /* 0270 */ 0x04, 0x31, 0x07, 0x90, 0x01, 0x90, 0x01, 0x90, /* 0278 */ 0x01, 0x90, 0x01, 0x00, 0x00, 0x59, 0x00, 0x69, /* 0280 */ 0x00, 0x4A, 0x00, 0x4A, 0x00, 0x5F, 0x00, 0x73, /* 0288 */ 0x00, 0x73, 0x00, 0x64, 0x00, 0x40, 0x00, 0x90, /* 0290 */ 0x92, 0x97, 0x60, 0x96, 0x00, 0x90, 0x55, 0x00, /* 0298 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 02A0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 02A8 */ 0x02, 0x02, 0xD4, 0x30, 0x00, 0x00, 0x02, 0x10, /* 02B0 */ 0x60, 0xEA, 0x00, 0x00, 0x02, 0x10 }, "hda-gfx", Buffer (0x0A) { "onboard-2" }, "PP_DisablePowerContainment", Buffer (One) { 0x01 }, "PP_FuzzyFanControl", Buffer (One) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (HDAU) { Name (_ADR, One) // _ADR: Address Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0A) { "built-in", Buffer (One) { 0x00 }, "AAPL,slot-name", Buffer (0x07) { "Slot-1" }, "name", Buffer (0x14) { "Radeon RX HD-Audio" }, "model", Buffer (0x14) { "Radeon RX HD-Audio" }, "hda-gfx", Buffer (0x0A) { "onboard-2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } } }  
       
        E.9.2.3) XGBE - 10GBit NIC Implementation:   DefintionBlock entry: External (_SB_.PCI0.BR3A, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.H000, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR3A.D07C, DeviceObj)    // (from opcode)  
      ASUS XG-C100C AQC107 PCI Device Implementation: Scope (\_SB.PCI0.BR3A)     {         Scope (H000)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D07C)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                     })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                         },                         "name",                         Buffer (0x33)                         {                             "ASUS XG-C100C Aquantia AQC107 10-Gigabit Ethernet"                         },                         "model",                         Buffer (0x11)                         {                             "Apple AQC107-AFW"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x87, 0x01, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0xB1, 0x07, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x6B, 0x10, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        Intel X540-T1 PCI Device Implementation: Scope (\_SB.PCI0.BR3A)     {         Scope (H000)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D07C)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                        })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                            },                         "name",                         Buffer (0x22)                         {                             "Intel X540-T1 10-Gigabit Ethernet"                         },                         "model",                         Buffer (0x22)                         {                             "Intel X540-T1 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
        Small-Tree P2EI0G-2T PCI Device Implementation: Scope (\_SB.PCI0.BR3A)     {         Scope (H000)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D07C)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XGBE)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                        })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                            },                         "name",                         Buffer (0x30)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 1"                         },                         "model",                         Buffer (0x29)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }         Device (XGBF)         {             Name (_ADR, One)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                        })                 }                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-6"                         },                         "built-in",                         Buffer (One)                         {                              0x00                            },                         "name",                         Buffer (0x30)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 2"                         },                         "model",                         Buffer (0x29)                         {                             "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0x0A, 0x00, 0x00, 0x00                         },                         "device-id",                         Buffer (0x04)                         {                              0x28, 0x15, 0x00, 0x00                         },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x86, 0x80, 0x00, 0x00                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      The 10-Gigabit NIC XGBE PCI implementation is mainly of cosmetic nature and valid for the NIC in Slot-6. For each PCIe Adapter and for different slot populations the XGBE PCI device implementation needs to be adopted/modified (see details above). This also states for the respective ACPI path entries "PCI0", "BR3A" and respective H000 -> D07C and D07C -> XGBE ACPI Replacements (in compliance with the iMac Pro 10GB ACPI variable nomenclature), directly performed within the SSDT-299-iMacPro.aml. Those not employing any 10-GBit NIC in their system, can simply remove the corresponding SSDT PCI device implementation.   E.9.2.4) ETH0 - onboard LAN Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0, DeviceObj)    // (from opcode) External (_SB_.PCI0.GLAN, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0)     {         Scope (GLAN)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ETH0)         {             Name (_ADR, 0x00190000)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x10)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                            },                         "name",                         Buffer (0x2A)                         {                             "Intel i218-V PCI Express Gigabit Ethernet"                         },                         "model",                         Buffer (0x21)                         {                             "Intel i218-V Ethernet Controller"                         },                         "location",                         Buffer (0x02)                         {                             "1"                         },                         "subsystem-id",                         Buffer (0x04)                         {                              0xC4, 0x85, 0x00, 0x00                          },                         "device-id",                         Buffer (0x04)                         {                              0xA1, 0x15, 0x00, 0x00                          },                         "subsystem-vendor-id",                         Buffer (0x04)                         {                              0x43, 0x10, 0x00, 0x00                          }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }         }     }  
      Note that the ETH0 Intel i218-V Ethernet onboard LAN controller PCI implementation is of pure cosmetic nature and valid for the ASUS X99-A II or X99 mainboards with the same LAN Controller configuration. Owners of different X99 mainboards have to verify and adopt/modify the ACPI path and the PCI device implementations by means of their IOREG entries. Note the GLAN -> ETH0 ACPI replacement directly performed within the SSDT.   E.9.2.5) SAT1 - Intel AHCI SATA Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.SAT1, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.SAT1) { Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0C) { "AAPL,slot-name", Buffer (0x09) { "Built In" }, "built-in", Buffer (One) { 0x00 }, "name", Buffer (0x1B) { "Intel SATA AHCI Controller" }, "model", Buffer (0x27) { "Intel X99-A II Chipset SATA Controller" }, "device_type", Buffer (0x15) { "AHCI SATA Controller" }, "device-id", Buffer (0x04) { 0x02, 0x8D, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } }  
      The SAT1 onboard Intel AHCI SATA controller PCI device implementation is valid for the ASUS X99-A II and for all other X99 mainboards with the same AHCI SATA controller chipset.   E.9.2.6) EVSS - Intel X99 sSata Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.EVSS, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (_SB.PCI0.EVSS) { Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x0E) { "AAPL,slot-name", Buffer (0x09) { "Built In" }, "built-in", Buffer (0x05) { "0x00" }, "name", Buffer (0x1B) { "Intel X99 sSata Controller" }, "model", Buffer (0x28) { "Intel X99-A II Chipset sSATA Controller" }, "compatible", Buffer (0x0D) { "pci8086,8d62" }, "device_type", Buffer (0x10) { "AHCI Controller" }, "device-id", Buffer (0x04) { 0x62, 0x8D, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, Zero }) }  
      The EVSS onboard Intel X99 sSATA controller PCI device implementation is valid for the ASUS X99-A II and for all other X99 mainboards with the same X99 sSATA controller chipset. Verify and adopt/modify if necessary device path "PCI0.SAT1" and PCI device implementations by means of IOREG.   E.9.2.7)  NVMe Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.BR1B, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR1B.D075, DeviceObj)    // (from opcode) External (_SB_.PCI0.BR1B.D081, DeviceObj)    // (from opcode)  
        PCI Device Implementation: Scope (_SB.PCI0.BR1B)     {         Scope (D075)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D081)         {             Name (_STA, Zero)  // _STA: Status         }         Device (ANS2)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 Store (Package (0x0C)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                             },                         "device-id",                         Buffer (0x04)                         {                              0x04, 0xA8, 0x00, 0x00                           },                         "device_type",                         Buffer (0x17)                         {                             "MVM Express Controller"                         },                         "name",                         Buffer (0x16)                         {                             "Apple NVMe Controller"                         },                         "model",                         Buffer (0x13)                         {                             "Apple NVMe AP1024M"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }  
      The current ANS2 Apple NVMe Controller PCI implementation is of purely cosmetic nature and is valid for the ASUS X99-A II. Note  ACPI Replacements D075 -> D081 and D081 -> ANS2 directly within the SSDT, in concordance with the respective SMBIOS iMacPro1,1 variable naming!   E.9.2.8) - USBX:   PCI Device Implementation: Device (_SB.USBX)     {         Name (_ADR, Zero)  // _ADR: Address         Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method         {             If (LNot (Arg2))             {                 Return (Buffer (One)                 {                      0x03                                     })             }             Return (Package (0x08)             {                 "kUSBSleepPortCurrentLimit",                 0x0834,                 "kUSBSleepPowerSupply",                 0x13EC,                 "kUSBWakePortCurrentLimit",                 0x0834,                 "kUSBWakePowerSupply",                 0x13EC             })         }     }  
      When using the XHCI device name for USB (see the XHCI PCI Device Implementation below), one observes a bunch of USB Power Errors when booting the system. The USBX PCI device implementation fixes this errors.
          E.9.2.9) XHCI - onboard Extended Host Controller Interface (XHCI) PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.XHCI, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (\_SB.PCI0.XHCI) { Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Store (Package (0x1B) { "AAPL,slot-name", Buffer (0x09) { "Built In" }, "built-in", Buffer (One) { 0x00 }, "device-id", Buffer (0x04) { 0x31, 0x8D, 0x00, 0x00 }, "name", Buffer (0x34) { "Intel XHC USB Controller" }, "model", Buffer (0x2F) { "Intel X99-A II Chipset XHC USB Host Controller" }, "AAPL,current-available", 0x0834, "AAPL,current-extra", 0x0A8C, "AAPL,current-in-sleep", 0x0A8C, "AAPL,max-port-current-in-sleep", 0x0834, "AAPL,device-internal", Zero, "AAPL,clock-id", Buffer (One) { 0x01 }, "AAPL,root-hub-depth", 0x1A, "AAPL,XHC-clock-id", One, Buffer (One) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } }  
      The XHCI USB3.0 PCI device implementation is valid for the ASUS X99_A II and for all other X99 mainboards with the same XHCI controller chipset. Verify and adopt/modify if necessary device path "PCI0.XHCI" and PCI device implementations by means of IOREG.     E.9.2.10) ASMedia ASM1142 USB 3.1 Controller PCI Implementation   DefintionBlock entry: External (_SB_.PCI0.RP05, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP05.D07D, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP05.D082, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (_SB.PCI0.RP05)     {         Scope (D07D)         {             Name (_STA, Zero)  // _STA: Status         }         Scope (D082)         {             Name (_STA, Zero)  // _STA: Status         }         Device (XHC3)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (One)                     {                          0x03                                         })                 }                 Store (Package (0x0A)                     {                         "AAPL,slot-name",                         Buffer (0x09)                         {                             "Built In"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                             },                         "device-id",                         Buffer (0x04)                         {                              0x42, 0x12, 0x00, 0x00                           },                         "name",                         Buffer (0x1B)                         {                             "ASMedia USB 3.1 Controller"                         },                         "model",                         Buffer (0x28)                         {                             "ASMedia ASM1142 USB 3.1 Type-A & Type-C"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }  
        The ASMedia ASM1142 USB 3.1 onboard Intel AHCI SATA controller PCI device implementation is valid for the ASUS X99-A II and for all other X99 mainboards with the same XHC USB3.1 controller ASMedia ASM1142 chipset configuration. Note the D07D -> D082 and D082 -> XHC3 ACPI replacements directly within the SSDT!   E.9.2.11) ARPT - OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI Implementation:   DefintionBlock entry: External (_SB_.PCI0.RP07, DeviceObj)    // (from opcode) External (_SB_.PCI0.RP07.ARPT, DeviceObj)    // (from opcode)  
      PCI Device Implementation: Scope (_SB.PCI0.RP07)     {         Device (ARPT)         {             Name (_ADR, Zero)  // _ADR: Address             Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method             {                 If (LEqual (Arg2, Zero))                 {                     Return (Buffer (0x04)                     {                          0x03                                         })                 }                 Store (Package (0x0C)                     {                         "AAPL,slot-name",                         Buffer (0x07)                         {                             "Slot-5"                         },                         "built-in",                         Buffer (One)                         {                              0x00                                             },                         "device_type",                         Buffer (0x13)                         {                             "AirPort Controller"                         },                         "model",                         Buffer (0x4A)                         {                             "OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 Controller"                         },                         "compatible",                         Buffer (0x0D)                         {                             "pci14e4,43a0"                         },                         "name",                         Buffer (0x10)                         {                             "AirPort Extreme"                         }                     }, Local0)                 DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))                 Return (Local0)             }             Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake             {                 0x6D,                 Zero             })         }     }  
        The ARPT OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI device implementation is of pure cosmetic nature and only valid for users of the latter WIFI/Bluetooth PCIe Adapter in PCIe Slot 5. Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 5 have to adapt/modify the respective device path. Users of the Asus X99-A II onboard Bluetooth chipset controller or with a completely different WIFI/Bluetooth configuration have to adopt the entire Airport PCI implementation by means of IOREG.   E.9.2.12) DTGP Method: Method (DTGP, 5, NotSerialized)     {         If (LEqual (Arg0, ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))         {             If (LEqual (Arg1, One))             {                 If (LEqual (Arg2, Zero))                 {                     Store (Buffer (One)                         {                              0x03                         }, Arg4)                     Return (One)                 }                 If (LEqual (Arg2, One))                 {                     Return (One)                 }             }         }         Store (Buffer (One)             {                  0x00             }, Arg4)         Return (Zero)     }  
      The DTG Method Implementation is required for SSDT functionality and has not to be modified or adopted in any case.     E.9.2.13) - Debugging Sleep Issues   For debugging sleep issues as proposed by Pike Alpha, one can add SSDT-SLEEP.aml to /EFI/CLOVER/ACPI/patched and follow Pike's comment and advices provided at https://pikeralpha.wordpress.com/2017/01/12/debugging-sleep-issues/     E.9.3) SSDT-X99-TB3-iMacPro-KGP.aml PCI Device Implementation    
      The current Thunderbolt PCI device implementation SSDT-X99-TB3-iMacPro-KGP.aml has been kept as close as possible to the SSDT-9.aml of @TheOffcialGypsy's iMac Pro dumb. It also contains implementations mainly developed by @apfelnico, @nmano, @Mork vom Ork, @Matthew82, @maleorderbridge, @TheRacerMaster.    It is valid for both, the ASUS TBEX 3 and Gigabyte Alpine Ridge and allows for TB and XHC USB sleep/wake functionality with the THB_C cable plugged to the thunderbolt onboard header of the ASUS Prime X299 Deluxe. While XHC USB hot plug seems to work fine within this configuration, TB hot plug seems to require the removal of the THB_C cable. Thank's to @crismac2013 and @LeleTuratti for their findings!   >>> https://youtu.be/Jakp5dCoFvY <<<   Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 4 have to adapt/modify the respective BR2A,BR2X, H000, D07F and UPSB ACPI Replacements, directly performed within the SSDT.   DefintionBlock entry: External (_SB_.PCI0, DeviceObj) // (from opcode) External (_SB_.PCI0.BR2A, DeviceObj) // (from opcode) External (_SB_.PCI0.BR2A.H000, DeviceObj) // (from opcode) External (_SB_.PWRB, DeviceObj) // (from opcode) External (AG12, UnknownObj) // (from opcode) External (AG22, UnknownObj) // (from opcode) External (BR2A, DeviceObj) // (from opcode) External (BR2A.H000, DeviceObj) // (from opcode) External (DTGP, MethodObj) // 5 Arguments (from opcode) External (IO80, UnknownObj) // (from opcode) External (PG12, UnknownObj) // (from opcode) External (PG22, UnknownObj) // (from opcode) External (PICM, UnknownObj) // (from opcode) External (PWRB, DeviceObj) // (from opcode)  
      PCI Device Implementation: OperationRegion (GNVS, SystemMemory, 0x4FEE6918, 0x0403) Field (GNVS, AnyAcc, Lock, Preserve) { OSYS, 16 } Method (OSDW, 0, NotSerialized) { If (LEqual (OSYS, 0x2710)) { Return (One) } Else { Return (Zero) } } Method (PINI, 0, NotSerialized) { Store (0x07DC, OSYS) If (XOSI ("Darwin")) { Store (0x2710, OSYS) } ElseIf (XOSI ("Linux")) { Store (0x03E8, OSYS) } ElseIf (XOSI ("Windows 2009")) { Store (0x07D9, OSYS) } ElseIf (XOSI ("Windows 2012")) { Store (0x07DC, OSYS) } Else { Store (0x07DC, OSYS) } } Method (XOSI, 1, NotSerialized) { Store (Package (0x0E) { "Darwin", "Linux", "Windows", "Windows 2001", "Windows 2001 SP2", "Windows 2001.1", "Windows 2001.1 SP1", "Windows 2006", "Windows 2006 SP1", "Windows 2006.1", "Windows 2009", "Windows 2012", "Windows 2013", "Windows 2015" }, Local0) Return (LNotEqual (Ones, Match (Local0, MEQ, Arg0, MTR, Zero, Zero))) } Scope (\_SB.PCI0) { Scope (BR2A) { Name (_STA, Zero) // _STA: Status } Device (BR2X) { Name (_ADR, 0x00020000) // _ADR: Address OperationRegion (MCTL, SystemMemory, 0xE0000188, 0x04) Field (MCTL, ByteAcc, NoLock, Preserve) { , 3, HGPE, 1, , 7, , 8, , 8 } Method (_INI, 0, NotSerialized) // _INI: Initialize { Store (One, HGPE) } Name (_HPP, Package (0x04) // _HPP: Hot Plug Parameters { 0x08, 0x40, One, Zero }) Name (SHPC, 0x40) Name (SPDS, 0x40) Name (MRLS, Zero) Name (CCOM, 0x10) Name (SPDC, 0x08) Name (MRLC, 0x04) Name (SPFD, 0x02) Name (SABP, One) Name (SPOF, 0x10) Name (SPON, 0x0F) Name (ALMK, 0x1C) Name (ALON, One) Name (ALBL, 0x02) Name (ALOF, 0x03) Name (PLMK, 0x13) Name (PLON, 0x04) Name (PLBL, 0x08) Name (PLOF, 0x0C) Name (HPEV, 0x0F) OperationRegion (PPA4, PCI_Config, Zero, 0x0100) Field (PPA4, ByteAcc, NoLock, Preserve) { Offset (0xA0), , 4, LDIS, 1, Offset (0xA2), Offset (0xA4), ATBP, 1, , 1, MRSP, 1, ATIP, 1, PWIP, 1, HPSR, 1, HPCP, 1, , 12, PSNM, 13, ABIE, 1, PFIE, 1, MSIE, 1, PDIE, 1, CCIE, 1, HPIE, 1, SCTL, 5, Offset (0xAA), SSTS, 7, Offset (0xAB), Offset (0xB0), Offset (0xB2), PMES, 1, PMEP, 1, Offset (0xB4) } Method (ATID, 0, NotSerialized) { Return (And (SCTL, 0x03)) } Method (PWID, 0, NotSerialized) { Return (ShiftRight (And (SCTL, 0x0C), 0x02)) } Method (PWCC, 0, NotSerialized) { Return (ShiftRight (And (SCTL, 0x10), 0x04)) } Method (ABPS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, One, SSTS) } Return (And (SSTS, One)) } Method (PFDS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x02, SSTS) } Return (ShiftRight (And (SSTS, 0x02), One)) } Method (MSCS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x04, SSTS) } Return (ShiftRight (And (SSTS, 0x04), 0x02)) } Method (PDCS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x08, SSTS) } Return (ShiftRight (And (SSTS, 0x08), 0x03)) } Method (CMCS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x10, SSTS) } Return (ShiftRight (And (SSTS, 0x10), 0x04)) } Method (MSSC, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x20, SSTS) } Return (ShiftRight (And (SSTS, 0x20), 0x05)) } Method (PRDS, 1, NotSerialized) { If (LEqual (Arg0, One)) { Or (SSTS, 0x40, SSTS) } Return (ShiftRight (And (SSTS, 0x40), 0x06)) } Method (OSHP, 0, NotSerialized) { Store (SSTS, SSTS) Store (Zero, HGPE) } Method (HPCC, 1, NotSerialized) { Store (SCTL, Local0) Store (Zero, Local1) If (LNotEqual (Arg0, Local0)) { Store (Arg0, SCTL) While (LAnd (LNot (CMCS (Zero)), LNotEqual (0x64, Local1))) { Store (0xFB, IO80) Sleep (0x02) Add (Local1, 0x02, Local1) } CMCS (One) } } Method (ATCM, 1, NotSerialized) { Store (SCTL, Local0) And (Local0, ALMK, Local0) If (LEqual (Arg0, One)) { Or (Local0, ALON, Local0) } If (LEqual (Arg0, 0x02)) { Or (Local0, ALBL, Local0) } If (LEqual (Arg0, 0x03)) { Or (Local0, ALOF, Local0) } HPCC (Local0) } Method (PWCM, 1, NotSerialized) { Store (SCTL, Local0) And (Local0, PLMK, Local0) If (LEqual (Arg0, One)) { Or (Local0, PLON, Local0) } If (LEqual (Arg0, 0x02)) { Or (Local0, PLBL, Local0) } If (LEqual (Arg0, 0x03)) { Or (Local0, PLOF, Local0) } HPCC (Local0) } Method (PWSL, 1, NotSerialized) { Store (SCTL, Local0) If (Arg0) { And (Local0, SPON, Local0) } Else { Or (Local0, SPOF, Local0) } HPCC (Local0) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { Name (_T_1, Zero) // _T_x: Emitted by ASL Compiler Name (_T_0, Zero) // _T_x: Emitted by ASL Compiler While (One) { Store (And (Arg0, 0xFF), _T_0) If (LEqual (_T_0, 0x03)) { While (One) { Store (ToInteger (Arg1), _T_1) If (LNotEqual (Match (Package (0x04) { 0x80, 0x81, 0x82, 0x83 }, MEQ, _T_1, MTR, Zero, Zero), Ones)) { If (LNot (PWCC ())) { PWCM (One) Store (One, ABIE) } } Break } } Break } } Method (EJ0L, 1, NotSerialized) { Store (0xFF, IO80) Store (SCTL, Local0) If (LNotEqual (ATID (), One)) { And (Local0, ALMK, Local0) Or (Local0, ALBL, Local0) } HPCC (Local0) Store (SCTL, Local0) Or (Local0, SPOF, Local0) HPCC (Local0) Store (SCTL, Local0) Or (Local0, PLOF, Local0) HPCC (Local0) Store (SCTL, Local0) Or (Local0, ALOF, Local0) HPCC (Local0) } Method (PMEH, 1, NotSerialized) { If (And (HPEV, SSTS)) { If (ABPS (Zero)) { ABPS (One) Sleep (0xC8) } } Return (0xFF) } Method (HPEH, 1, NotSerialized) { If (LNot (HPCP)) { Return (0xFF) } Store (0xFE, IO80) Sleep (0x64) Store (Zero, CCIE) If (And (HPEV, SSTS)) { Store (0xFD, IO80) Sleep (0x0A) Store (PPXH (Zero), Local0) Return (Local0) } Else { Return (0xFF) } Store (0xFC, IO80) Sleep (0x0A) } Method (PPXH, 1, NotSerialized) { Sleep (0xC8) If (ABPS (Zero)) { If (LNot (PRDS (Zero))) { Store (One, LDIS) PWSL (Zero) PWCM (0x03) If (LEqual (MSSC (Zero), MRLS)) { ATCM (0x02) } Else { ATCM (0x03) } ABPS (One) Sleep (0xC8) Return (0xFF) } Store (Zero, ABIE) ABPS (One) Sleep (0xC8) If (PWCC ()) { ATCM (0x02) Sleep (0x0258) Store (0x0258, Local0) ABPS (One) While (LNot (ABPS (Zero))) { Sleep (0xC8) Add (Local0, 0xC8, Local0) If (LEqual (0x1388, Local0)) { Store (One, ABIE) ATCM (0x03) PWCM (0x02) Sleep (0x0258) Store (Zero, LDIS) PWSL (One) Sleep (0x01F4) If (LNot (PFDS (Zero))) { PWCM (One) Store (Zero, Local1) Store (One, ABIE) } Else { PWSL (Zero) PWCM (0x03) ATCM (One) Store (One, LDIS) Store (0x03, Local1) Store (One, ABIE) } ABPS (One) Sleep (0xC8) Return (Local1) } } Return (0xFF) } Else { ATCM (0x02) Sleep (0x0258) Store (0x0258, Local0) ABPS (One) Sleep (0xC8) While (LNot (ABPS (Zero))) { Sleep (0xC8) Add (Local0, 0xC8, Local0) If (LEqual (0x1388, Local0)) { ABPS (One) ATCM (0x03) PWCM (0x02) Sleep (0xC8) Store (One, ABIE) Store (One, LDIS) PWCM (0x03) Return (0x03) } } PWCM (One) ABPS (One) Sleep (0xC8) Store (One, ABIE) Return (0xFF) } } If (PFDS (Zero)) { PFDS (One) PWSL (Zero) PWCM (0x03) ATCM (One) Store (One, LDIS) Return (0x03) } If (PDCS (Zero)) { PDCS (One) If (LNot (PRDS (Zero))) { PWSL (Zero) PWCM (0x03) If (LEqual (MSSC (Zero), MRLS)) { ATCM (0x02) } Else { ATCM (0x03) } Store (One, LDIS) Return (0xFF) } Else { Store (Zero, LDIS) ABPS (One) Sleep (0xC8) Store (One, ABIE) Sleep (0xC8) Return (Local1) } } Return (0xFF) } Method (SNUM, 0, Serialized) { Store (PSNM, Local0) Return (Local0) } Method (_SUN, 0, NotSerialized) // _SUN: Slot User Number { Return (SNUM ()) } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (AG12) } Return (PG12) } Device (UPSB) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (One) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (One) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LNot (Arg2)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x02) { "PCIHotplugCapable", One }) } Device (NHI0) { Name (_ADR, Zero) // _ADR: Address Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Store (Package (0x13) { "AAPL,slot-name", Buffer (0x07) { "Slot-4" }, "built-in", Buffer (One) { 0x00 }, "device_type", Buffer (0x19) { "Thunderbolt 3 Controller" }, "model", Buffer (0x20) { "Intel DSL6540 Thunderbolt 3 NHI" }, "name", Buffer (0x25) { "Intel DSL6540 Thunderbolt Controller" }, "pathcr", Buffer (One) { /* 0000 */ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00, /* 0010 */ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00, /* 0020 */ 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x0E, 0x00, /* 0028 */ 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0030 */ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0038 */ 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x01, 0x00, /* 0040 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0048 */ 0x00, 0x00, 0x07, 0x00, 0x02, 0x00, 0x01, 0x00 }, "ThunderboltDROM", Buffer (One) { /* 0000 */ 0x6D, 0x01, 0xC5, 0x49, 0xD5, 0x3E, 0x21, 0x01, /* 0008 */ 0x00, 0x04, 0xCE, 0x8D, 0x61, 0x01, 0x5E, 0x00, /* 0010 */ 0x01, 0x00, 0x0C, 0x00, 0x01, 0x00, 0x08, 0x81, /* 0018 */ 0x81, 0x02, 0x81, 0x00, 0x00, 0x00, 0x08, 0x82, /* 0020 */ 0x91, 0x01, 0x81, 0x00, 0x00, 0x00, 0x08, 0x83, /* 0028 */ 0x81, 0x04, 0x81, 0x01, 0x00, 0x00, 0x08, 0x84, /* 0030 */ 0x91, 0x03, 0x81, 0x01, 0x00, 0x00, 0x08, 0x85, /* 0038 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x86, /* 0040 */ 0x20, 0x03, 0x87, 0x80, 0x02, 0xC8, 0x05, 0x89, /* 0048 */ 0x50, 0x00, 0x00, 0x05, 0x8A, 0x50, 0x00, 0x00, /* 0050 */ 0x02, 0xCB, 0x0D, 0x01, 0x41, 0x70, 0x70, 0x6C, /* 0058 */ 0x65, 0x20, 0x49, 0x6E, 0x63, 0x2E, 0x00, 0x0C, /* 0060 */ 0x02, 0x4D, 0x61, 0x63, 0x69, 0x6E, 0x74, 0x6F, /* 0068 */ 0x73, 0x68, 0x00 }, "ThunderboltConfig", Buffer (One) { /* 0000 */ 0x01, 0x02, 0xFF, 0xFF, 0x04, 0x00, 0x03, 0x01, /* 0008 */ 0x01, 0x00, 0x04, 0x00, 0x05, 0x01, 0x02, 0x00, /* 0010 */ 0x03, 0x00, 0x03, 0x01, 0x01, 0x00, 0x01, 0x00, /* 0018 */ 0x03, 0x01, 0x02, 0x00, 0x04, 0x00, 0x03, 0x00 }, "power-save", One, Buffer (One) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Return (Zero) } } Device (DSB1) { Name (_ADR, 0x00010000) // _ADR: Address Name (_SUN, 0x04) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB2) { Name (_ADR, 0x00020000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LNot (Arg2)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x02) { "PCIHotplugCapable", Zero }) } Device (XHC5) { Name (_ADR, Zero) // _ADR: Address Name (SDPC, Zero) OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x10) { "AAPL,slot-name", Buffer (0x07) { "Slot-4" }, "built-in", Buffer (One) { 0x00 }, "model", Buffer (0x16) { "Intel DSL6540 USB 3.1" }, "name", Buffer (0x1D) { "Intel DSL6540 XHC Controller" }, "device-id", Buffer (0x04) { 0xB6, 0x15, 0x00, 0x00 }, "USBBusNumber", Zero, "AAPL,XHCI-clock-id", One, "UsbCompanionControllerPresent", One }) } Name (HS, Package (0x01) { "XHC1" }) Name (FS, Package (0x01) { "XHC1" }) Name (LS, Package (0x01) { "XHC1" }) Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake { Return (Package (0x02) { 0x6D, Zero }) } Device (RHUB) { Name (_ADR, Zero) // _ADR: Address Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (SSP1) { Name (_ADR, One) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) Name (HS, Package (0x02) { "XHC1", 0x05 }) Name (FS, Package (0x02) { "XHC1", 0x05 }) Name (LS, Package (0x02) { "XHC1", 0x05 }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x08) { "UsbCPortNumber", 0x03, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8, "UsbCompanionPortPresent", One }) } } Device (SSP2) { Name (_ADR, 0x02) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) Name (HS, Package (0x02) { "XHC1", 0x06 }) Name (FS, Package (0x02) { "XHC1", 0x06 }) Name (LS, Package (0x02) { "XHC1", 0x06 }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x08) { "UsbCPortNumber", 0x04, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8, "UsbCompanionPortPresent", One }) } } Device (HS01) { Name (_ADR, 0x03) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) } Device (HS02) { Name (_ADR, 0x04) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { Buffer (0x10) { /* 0000 */ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0008 */ 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address Name (_SUN, 0x02) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (LNot (Arg2)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x02) { "PCI-Thunderbolt", One }) } } } }  
      Thanks to @nmano we now also have an additional SSDT, i.e SSDT-TB3-L02-BR2X.aml, which fixes further TB ACPI dependencies and which should be implemented in /EFI/Clover/ACPI/patches. This SSDT will permanently loads the TB NHI0 and XHC USB PCI drivers, even in case that no TB devices are connected. Apparently it also resolves some TB sleep/wake issues.   SSDT-TB3-L02-BR2X.aml can be substituted by a simple Clover DSDT patch to be included in the config plist:   Comment: BR2A BR2X THB patch ©N.Mano Find: 42523241 48303030 60865C2F 045F5342 5F504349 30425232 41483030 3160865C 2F045F53 425F5043 49304252 32414830 30326086 5C2F045F 53425F50 43493042 52324148 30303360 865C2F04 5F53425F 50434930 42523241 48303034 60865C2F 045F5342 5F504349 30425232 41483030 3560865C 2F045F53 425F5043 49304252 32414830 30366086 5C Replace: 42523258 55505342 60865C2F 055F5342 5F504349 30425232 58555053 42445342 3060865C 2F055F53 425F5043 49304252 32585550 53424453 42316086 5C2F055F 53425F50 43493042 52325855 50534244 53423260 865C2F05 5F53425F 50434930 42523258 55505342 44534233 60865C2F 055F5342 5F504349 30425232 58555053 42445342 3460862A 5C  
        E.10) iMac Pro Boot Splash Screen Cosmetics    Based on the ideas and instructions of @Matthew82, I achieved an iMacPro ASUS Boot Splash Screen     by means of the following procedure:   1.) Installation of the BREW distribution:   a.) Open a terminal and change to "bash" shell. bash  
      b.) Now enter the following "bash" terminal command and follow the standard BREW installation instructions: /usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)"  
      2.) After the successful installation of the BREW distribution, we have to implement the QT5 distribution, again by using a "bash" terminal shell. Enter the following "bash" terminal commands: brew install qt5 brew link qt5 --force  
      3.) After successfully implementing BREW and QT5 and if not already performed in Section B.1), we can now download the most actual CodeRush UEFIPatch distribution from Github to our home directory with the following terminal command: git clone https://github.com/LongSoft/UEFITool  
      4.) Now compile the UEFI Tool distribution with the following terminal commands: cd /UEFITools/ qmake uefitool.pro make  
      5.) Download and unzip iMacPro.raw to your Desktop.   6.) Now launch by UEFITool by clicking on the newly compiled UEFITool.app in the UEFITools Folder in your home directory.   a.) Select "File" -> "Open image file" and load your patched or unpatched BIOS Firmware distribution.   Select "Search.." in the UEFITool "Edit" Menu and perform a "GUID" search of "7BB28B99-61BB-11D5-9A5D-0090273FC14D" with "Header only"...     You will receive a message "GUID pattern "7BB28B99-61BB-11D5-9A5D-0090273FC14D" found as .... in 7BB28B99-....". Double click on that message and search for the "Raw section" accompanying the "7BB28B99-...." entry, which indeed is the Boot Image, which you can easily verify by extracting the raw section body (right-click on "Raw section" and select "Extract body") to your Desktop and by subsequently opening the extracted raw-file directly with Apple's "Preview.app" (right-click an the raw file and select "Open with.." -> Preview.app).   b.) To exchange the default original ASUS Boot Logo image file stored in "Raw Section" by the iMacPro.raw image file that you previously downloaded to your Desktop,  right-click again on "Raw section", select this time "Replace body"  and select the iMacPro.raw image file on your Desktop.     Note that the actual image dimension of iMacPro.raw (2131pix x 1457pix) was adopted for its use on my 38" LG 38UC99. For monitors with reduce screen resolution, iMacPro.raw might have to be adopted to an image dimension that suites your particular screen resolution, before its upload to "Raw section". If the Boot Logo image dimension is too big for your Monitor's screen resolution, you might just end up with a black screen during the BIOS initialisation at boot.   To do so, select in the Preview.app Menu -> "Tools" -> "Adjust Size". Change the image dimension and save the modified image with "File" -> "Export". In the "Export menu" press "Save", after selecting "JPEG" under "Format" , after choosing "Desktop" as the place to store the image, and after entering the new file name, which has to end with ".jpg".   Double-check by right-clicking on the resulting jpg image file and selecting "Get Info" that its file size does no exceed 200KB by far. If the latter would be the case, you would not be able to save the modified BIOS Firware file subsequently.   Finally just rename your new "XXXX.jpg" file to "XXXX.raw....   I guess, that by following the procedure detailed above, it is obvious that iMacPro.raw also can be substituted by any other image of your personal choice. Just be aware that it's background colour should be black (ecstatic reason for a its nice integration within the else black ASUS BIOS Boot Screen)   c.)  After replacing "Raw Section" with iMacPro.raw or the XXX.raw image of your choice, save your modified BIOS Firmware File with the Option "File" -> "Save Image File..."   d.) Copy your modified BIOS Firmware file to a USB3.0 Flash Drive, formatted with FAT32.   e.) Reboot, enter the Mainboard BIOS and save your BIOS settings to the USB Flash Drive   f.) Flash your mainboard BIOS with the modified BIOS Firmware   g.) Renter the Mainboard BIOS and restore your BIOS settings from the USB Flash Drive   h.) Save your restored BIOS settings with (F7) and (F10), reboot and you are done.   Just don't forget to set BIOS Setting "Boot Logo Display" to "Auto", when using this new approach. Any different setting might result in a black screen during BIOS initialisation.     E.11) iMac Pro Desktop Background Cosmetics    It might be nice to equip your iMac Pro X299 also with the adequate iMac Pro Desktop Background.   1.) Download, unzip and copy imac-pro-wallpaper.jpg.zip to your Dektop   2.) Right-click with the mouse on your Desktop and select "Change Desktop Background.."   3.) In the left column click on the "+" and add your Desktop Folder   4.) Select imac-pro-wallpaper.jpg to be your new Desktop Background    E.12) iStatMenus Hardware Monitoring   Thanks to extended tweet session between @BJango, @gxsolace and myself, we achieved a major step forward in properly monitoring Skylake-X/X299 Hardware with iStatMenus. iStatMenus now correctly interfaces with the HWSensor and FakeSMC kext distribution provided by @interferenc. It also can be used for Broadwell-E/EP, Haswell-E/EP, X99 system monitoring, with the tiny drawback that for CPUs with less then 18 cores the CPU numeration seems still erroneous. My distributed EFI-Folder already contains all necessary HWSensor and FakeSMC kexts.    The most actual iStatMenus v6.1 distribution can be assessed at https://bjango.com/mac/istatmenus/   The most actual HWSensor and FakeSMC kext distribution of @interferenc can be separately assessed at https://github.com/interferenc/HWSensors.    To compile the the HWSensor and FakeSMC kexts of @interferenc, perform the individual steps detailed below:   1.) git clone https://github.com/interferenc/HWSensors 2.)
      cp HWSensors ~/Desktop/ 3.)
      cd ~/Desktop/HWSensors 4.)
      xcodebuild -project Versioning\ And\ Distribution.xcodeproj/ 5.)
      xcodebuild -project HWMonitor.xcodeproj/ 6.)
      xcodebuild -project HWSensors.xcodeproj -alltargets  
      Subsequently, one finds the all compiled binaries in ~/Desktop/HWSensors/Binaries/.   Note that all compiled kext binaries are once more attached towards the bottom of this originating thread (guide). Just download and unzip HW-Sensors-IF.zip and copy all kexts to /EFI/Clover/kexts/Other/. Note that this pre-compiled binary package already implements a modified GPU Sensor kext of @Kozlek, which should also account for Polaris GPUs.   Many thanks to both @interferenc and @Bjango for their awesome and extensive contributions and brilliant work!   Broadwell-E/EP, Haswell-E/EP, X99 iStatMenus Hardware Sensor Data:     Broadwell-E/EP, Haswell-E/EP CPU Thread Utilisation Graphs:     To change from CPU core to thread utilisation monitoring, uncheck "Hide Hyper-Threading cores" in Section "CPU & GPU" of iStatMenus Preferences.     Temperature unites can be adjusted between Celsius, Fahrenheit and Kelvin in Section "Sensors" of iStatMenus Preferences.       F.) Benchmarking   F.1) i7-6950X CPU Benchmarks             F.2) Gigabyte AORUS GTX 1080 Ti 11GB Xterme Edition OpenGL and Metal Benchmarks   Yet to be implemented to be implemented once a macOS 10.14 Mojave Web Driver has been released.     G.) Summary and Conclusions   Already under macOS 10.12 Sierra and macOS 10.13 High Sierra, Broadwell-E/EP, Haswell-E/EP, X99 systems reached full functionality together with flawless stability. Now with macOS 10.14 Mojave, it might be another opportunity to follow my iMac Pro Build and Desktop Guide to unfold the unbelievable Broadwell-E/EP, Haswell-E/EP, X99 potential!   High-end builds based on Broadwell-E/EP, Haswell-E/EP, X99 technology have found manifold application, not only in science and research at universities or research institutions, engineering facilities, or medical labs, etc... Broadwell-E/EP, Haswell-E/EP, X99 with up to 22 cores (44 threads) and turbo frequencies up to 4.4 GHz have made X99 to a "relatively cheap" but really serious alternative to real iMac Pro's and Mac Pro's. The principal intention of my desktop guides is to demonstrate, that we are able to build and configure fully functional and relatively "low-cost" high-end systems, which go far beyond of what Apple is able to offer at present or will be ever able to offer for some reasonable pricing. Broadwell-E/EP, Haswell-E/EP, X99 Systems that allow the use of all software-packages developed for MacOS, Unix, Linux or even Windows at the same time (e.g. think on Vine, Parallels, or a dual boot system configuration). The flexibility between different mainboards (Asus, Gigabyte, ASRock, MSI, etc.), different Broadwell-E/EP, Haswell-E/EP processors, and different RAM memory configurations (16-128GB) make such systems affordable for anybody (also home office, audio and video editing/production, etc.) and allows their perfect adaptation for each specific purpose, requirement and available budget. It might not be necessary to outline, that current Broadwell-E/EP, Haswell-E/EP, X99 Systems perform absolutely stable on a 24/7/365 basis.   I am a scientist, expert in solar physics, space weather forecast and related telescope/instrument/space-mission development. In the frame of my scientific research, I developed parallelized image reconstruction, spectral line inversion and numerical modeling algorithms/applications, which require tremendous parallelized calculation power, RAM memory and storage capacities to reduce, analyze and interpret extensive and pioneering scientific ground-based or space-born observational data sets. This basically was also the professional motivation for developing innovative iMac Pro macOS Builds iSPOR-S (imaging Spectropolarimetric Parallel Organized Reconstruction Servers running iSPOR-DP, the Imaging Spectropolarimetric Parallel Organized Reconstruction Data Pipeline software package for the GREGOR Fabry-Pérot Interferometer, located at the 1.5m GREGOR Solar Telescope (Europe's largest solar telescope) on Tenerife, Canary Islands, Spain) as well as for the entire related iMac Desktop Guide Development, which naturally shall also be of benefit for others.  Anybody interested can find more details on my personal webpage.  
       
    • By oliveiro
      Hi community !
      Is anybody successful with 10.13.x and multiple GPUs on a desktop hack ?
      My main rig (see in signature) HD4600 + GTX550Ti + GTX560 is working perfectly under 10.11.6 and 10.12.6.
      Very simple to install, Intel IGPU set to active and primary in bios, inject intel and igplatformid in bootloader (enoch or clover), no nividia injection, since Fermi GPUs are natively supported. Smbios set to iMac14.2 for my Haswell CPU, and to avoid AppleGraphicsDeviceControl devices unloading.
      But from 10.13.0 to 10.13.3, system boots fine until login screen where WindowServer crashes with a "no MTLDevice" error (MeTaL device I guess). I could workaround that error by unloading nvidia devices in AppleGraphicsDeviceControl, but that kind of defeats the purpose, since only the IntelHD4600 can then be used.
      10.13.4 brings a little improvement, desktop can be reached, all 3 gpus active (AppleDisplay instances appear in IORegistryExplorer for Intel and Nvidias) but only Intel HDMI output shows desktop correctly, both nvidias (HDMI or DVI output) only show a black desktop where the mouse pointer can be moved normally. Displays can be arranged, orientation and resolution can be changed, as if everything was fine, but it is not.
      Console shows the following repeated messages :
           WindowServer (Skylight) : Unable to composite display surface due to null compositor.
           WindowServer (CoreDisplay) : [ERROR] - Attempting to get capabilities from capabilities with no devices
      Does anybody have an idea on how to avoid or workaround these errors ?
      Thanks !
      O.
      Things I've tried:
      Bios Graphic Devices order changes (breaks everything unless IGPU is primary) nvidia injection in bootloader (fails in enoch, disables secondary nvidia GPU outputs in clover) Smbios changes and/or AppleDeviceControlPolicy plist edits (simply enables or disables nvidia outputs) nvidia official or web drivers (no changes at all, even though webdrivers are properly loaded ; requires nvram emulation with enoch) enoch or clover (no difference except clover boots a bit faster - than enoch with nvram - thanks to proper UEFI boot I guess) lilu intel and/or nvidia and/or coredisplay graphicsfixups (no visible changes but graphics devices names, and thus enables or disables AGPM) use binaries from Sierra 10.12.6 for CoreDisplay and/or Skylight frameworks (never reached desktop) NVIDIAeGPUSupport (no changes)
    • By Angelo_
      HI, i've installed high sierra a while ago and never really used it that much but i got bored of w10 so i've decided to use it as my daily driver for a while and i noticed that usb 3.0 ports don't work with usb 3 devices and only with usb 2.0 devices(capped at the 480mb/s limit of usb 2.0), is there a way to get past that? i couldn't find it in this forum, i don't need the speed that much for right now(even tho i might since i shoot in raw and usb 2.0 is slow for file transfer of big photos or videos i take on holidays or on days off)  but i'd like to at least be able to use the usb 3.0s with my usb 3 devices and hub. 
      Hope that i write this post correctly, english is not my main language.
      ps  i don't need because i'm on lan but does it exist a driver/kext for intel wifi/bluetooth combo integrated in my z87 mpower(centrino 2200) ? bluetooth works already.
    • By Dallastyle
      Hi insanelymac,
      I'm using a Dell All in one Inspiron 5348. It has a Pentium dual core G3240 Haswell clocked at 3.07 ghz in Mac. I've successfully booted and installed Mac Os X el capitan on an external hdd using a fake cpuid (0x0306E0) its ivybride. But my problem is the drivers. The only thing I could remotely do is wifi. I've installed the kexts for my wifi card. What I need is to install intel hd graphics (desktop) kexts and audio drivers (alc668)
      I've tried doing every method. Except for Ddst because I don't understand it whatsoever.Also found this thing called xcpm and was wondering if I can just spoof the graphics ids or something like that. Hopefully you guys can help me and thanks!
    • By YannisKrp
      What is the best Mini-ITX motherboard for my i5-4460 (replaceable Broadcom chip, if it's possible m.2)? I'm planning to make a Mini-ITX hackintosh inside a Streacom F1C. Is the F1C Evo taller than the F1C and is there any way i can fit a GPU inside it (PCIe raiser etc.)?
       
      Thanks in advance.
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