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DSDT for Asus P8P67-M PRO

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Well, I can boot without NullCPUPowerManagement and have a few P states defined. It clocks down to 1.7GHz and the temp drops accordingly.

 

Sleep and NPM still need more work though.

Awesome. Great news. What did you do?

 

p.s. My ssdt_usb.dsl need a bit of work as dgsga ran into an issue - booting stops a few lines into the process. I hope to be able to locate and fix this problem a.s.a.p.

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Awesome. Great news. What did you do?

 

p.s. My ssdt_usb.dsl need a bit of work as dgsga ran into an issue - booting stops a few lines into the process. I hope to be able to locate and fix this problem a.s.a.p.

 

 

I did a lot of things and I am afraid I did not take adequate notes. Starting over with a fresh install this weekend so that I can pin down what was actually necessary and what was simply incidental. I unfortunately have a busy weekend, so maybe you can get your build booting as you can probably make more of it then I can.

 

I think your DSDT is the most important piece so far. With my own DSDT+my own SSDT (edited with the normal X58 edits from d00d's thread) I can boot without disabling NPM, but get no changes in clock or voltage. WIth your DSDT+SSDTs, I see it downclock to 1.6GHz, 1.7GHz, and then 3.4GHz. Nothing in between. Voltage is either .7 or the full 1.3.

 

Also, the 10.6.6 MBP +10.6.7 MBP update result in a panic a few lines in, but my 10.6.3->10.6.7 combo update is the working booting volume. Perhaps this means I am just sidestepping what we really should get working thorough.

 

With your DSDT+your two SSDTs I was able to boot without a disabler and see voltage/clock changes (with MSR Tools); however, I also started adding newer versions of each kext that I thought might help with AppleIntelCPUPowerManagement stalling out. So I am not positive which kexts need to be with your DSDT. I assume newer and more of them is probably the best.

 

Sorry, like I said, this is all a mess still.

 

Additionally, there is someone on the Tony Mac forums that was able to do this as well, but has not posted any information. He actually reports that AppleIntelCPUPowerManagement+client were both successfully loaded. Mine don't load, even though HPET and LPC do, they just don't cause a crash.

 

I sent a PM, but no response.

 

Also, I am still using AnVal. I had to download the latest Xcode in order to try to use RevoBoot and haven't bothered rebooting my main computer yet and making it yet.

 

I am using the P8p67 as well.

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I'm getting a sandybridge system, specifically the P8P67 (Rev 3.) Vanilla, and I was wondering if anyone's had any luck with this DSDT? I suspect it will work fine, as the boards are nearly identical, but I was curious in advance :(

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With your DSDT+your two SSDTs I was able to boot without a disabler and see voltage/clock changes (with MSR Tools); however, I also started adding newer versions of each kext that I thought might help with AppleIntelCPUPowerManagement stalling out. So I am not positive which kexts need to be with your DSDT. I assume newer and more of them is probably the best.

 

Sorry, like I said, this is all a mess still.

 

Additionally, there is someone on the Tony Mac forums that was able to do this as well, but has not posted any information. He actually reports that AppleIntelCPUPowerManagement+client were both successfully loaded. Mine don't load, even though HPET and LPC do, they just don't cause a crash.

 

I sent a PM, but no response.

 

Also, I am still using AnVal. I had to download the latest Xcode in order to try to use RevoBoot and haven't bothered rebooting my main computer yet and making it yet.

 

I run into the same issue,

com.apple.kextcache[314]	kxld[com.apple.driver.AppleIntelCPUPowerManagement]: The following symbols are unresolved for this kext:
com.apple.kextcache[314]	kxld[com.apple.driver.AppleIntelCPUPowerManagement]: 	_lapic_start

 

LPC isn't loading, but I haven't downloaded the updated SB kext's from the 10.6.7 update, so I will try that. I'm using AnVal as well, I haven't tried RevoBoot yet, but I will use RevoBuilder later to ease the process. Your DSDT seems to work fine for my board after a couple changes, and the SSDT is being loaded (after a couple changes for the i5-2500k), but it seems to not want to load CPUPM using MacPro5,1

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One of the moderators is currently testing the latest DSDT/SSDT mods with his 2500K and I will attach the files when he confirmed that they are working for him.

 

I also located a bug in RevoBoot that triggered a hang early in the boot process, and this patch will be pushed into the github repository later today (scrax need to do some testing with it).

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One of the moderators is currently testing the latest DSDT/SSDT mods with his 2500K and I will attach the files when he confirmed that they are working for him.

 

I also located a bug in RevoBoot that triggered a hang early in the boot process, and this patch will be pushed into the github repository later today (scrax need to do some testing with it).

 

Sounds great, in the meantime I will wait on RevoBoot and install it later and try to fix getting Vanilla sound to work with the DSDT + Info.plist + Vanilla kext's.

 

For RevoBoot, would you mind posting what settings you use for the header (.h) files? Or would using RevoBuilder take care of most of it fine for SB?

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Hi :)

I didn't have time to test my new dsdt and ssdt_pr (i5-2500K) without Null and also with a MacPro mac model identifier instead of MacBook Pro.

I'll make some test next week and post here the results.

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Good day,

 

I'm testing a P8P67 with i5-2500K right now, so far pretty much every function in your DSDT matches the addresses in my factory DSDT.

 

ssdt_usb seems identical to my board, but I'm a bit concerned about the different PCI/E lanes, needs investigating.

 

Currently editing my specific p-states, is there a reason for zeroing out the other values under package (0x06)?

 

 

EDIT: not sure which combination of static injection I need to specify, is there a way to tell the /DSDT.aml and /SSDT_PR.aml were loaded? Or are they always loaded after the static injection?

 

The PerformanceStateArray is now filled with the right values and I'm using the kexts from MBP2011, but still AppleIntelCPUPM KPs on me.

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Good day,

 

I'm testing a P8P67 with i5-2500K right now, so far pretty much every function in your DSDT matches the addresses in my factory DSDT.

 

ssdt_usb seems identical to my board, but I'm a bit concerned about the different PCI/E lanes, needs investigating.

 

Currently editing my specific p-states, is there a reason for zeroing out the other values under package (0x06)?

 

 

EDIT: not sure which combination of static injection I need to specify, is there a way to tell the /DSDT.aml and /SSDT_PR.aml were loaded? Or are they always loaded after the static injection?

 

The PerformanceStateArray is now filled with the right values and I'm using the kexts from MBP2011, but still AppleIntelCPUPM KPs on me.

 

From what she said it won't work without using the NullCPUPM kext. I have a P8P67 (vanilla rev3), is that what you have?

 

I tried to change hers to match my board, but still no luck with audio or details showing up in the system profiler, is there any chance you could share your DSDT? Or are you still using hers?

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From what she said it won't work without using the NullCPUPM kext. I have a P8P67 (vanilla rev3), is that what you have?

 

I tried to change hers to match my board, but still no luck with audio or details showing up in the system profiler, is there any chance you could share your DSDT? Or are you still using hers?

 

I've got the same board, BIOS version 1401. I did my install using tonymac's [url="http://www.insanelymac.com/forum/topic/279450-why-insanelymac-does-not-support-tonymacx86/"]#####[/url]/[url="http://www.insanelymac.com/forum/topic/279450-why-insanelymac-does-not-support-tonymacx86/"]#####[/url] approach and it worked very well to get the system running.

 

I did manage to get sound working with a special enabler for that chip, but not via DSDT. I have an additional CMI8738 sound-card, so I actually deactivated the whole thing.

 

Regarding the DSDT, I'm still experimenting and pretty much using hers at the moment, just added my specific P-states in SSDT_PR.

 

I'm on and off using RevoBoot or Chameleon, but I'm not able to pinpoint why exactly IntelCPUPM is crashing.

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I will add the file I talked about – for the i5-2500(K) – this evening.

 

Sorry. Didn't make it due to having a stupid eye infection. Anyway. Here it is. This one includes the _PSS object data aja P-States for your CPU. All that you will have to do, for now, is to remove the extra 4 processor block declarations (only keep CPU0-CPU3 and remove the others).

 

Have fun.

ssdt_pr.dsl.zip

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I will add the file I talked about – for the i5-2500(K) – this evening.

 

Sorry. Didn't make it due to having a stupid eye infection. Anyway. Here it is. This one includes the _PSS object data aja P-States for your CPU. All that you will have to do, for now, is to remove the extra 4 processor block declarations (only keep CPU0-CPU3 and remove the others).

 

Have fun.

 

Cheers!

 

Hope your infection gets better soon, thanks for posting regardless.

 

The PSS data for my i5-2005K looks like this (extracted in Gentoo), not sure if those numbers need to be converted to work in OSX (another multiplier base maybe)?

 

PSS: 0x3B00, 0x3A00, 0x3900, 0x3800, 0x3700, 0x3600, 0x3500, 0x3400, 0x3300, 0x3200, 0x3100, 0x3000, 0x2F00, 0x2E00, 0x2D00, 0x1000

 

In my current configuration those are also populated in PerformanceStateArray without any DSDT (not sure if Chameleon passes them along or a BIOS config did it as they were not present a couple of days ago).

 

Using a legacy kernel I can see temperatures drop 3-4°C indicating some sort of throttling while IntelCPUPM loads fine.

 

Using your DSDT/SSDT the kernel still panics on IntelCPUPM.

 

Still no happy panda, then. Ideas on what I could try next?

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Using a legacy kernel I can see temperatures drop 3-4°C indicating some sort of throttling while IntelCPUPM loads fine.

 

Using your DSDT/SSDT the kernel still panics on IntelCPUPM.

Legacy kernel? Doesn't that just block AppleCPUPowermanagement.kext from getting loaded?

 

I am using the vanilla 10.6.7 kernel of a MacBookPro8,3 and I think (hope really) to have found something interesting (we're working on it) that could potentially lead to vanilla Intel SpeedStep support for our Sandy Bridge CPU's

 

However. Since this is easter weekend, and still very nice whether... don't wait for it as I am goggled up for a plunge in our pool :(

 

Happy Easter!

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Legacy kernel? Doesn't that just block AppleCPUPowermanagement.kext from getting loaded?

Spot on! Too much coffee yesterday... it just blocks it, yes.

 

I am using the vanilla 10.6.7 kernel of a MacBookPro8,3 and I think (hope really) to have found something interesting (we're working on it) that could potentially lead to vanilla Intel SpeedStep support for our Sandy Bridge CPU's

 

However. Since this is easter weekend, and still very nice whether... don't wait for it as I am goggled up for a plunge in our pool :)

 

Happy Easter!

 

Great, looking forward to it! Need to get some real work done anyways :(

 

Have a nice weekend!

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Here are the first new findings:

 

1.) We have to fill in the Frequency and Power fields ourself now, because it no longer gets done for us. Unlike before with other models.

 

2.) Some of the data in our _PSS object, the one from our BIOS, has some serious errors in it. We have to correct the errors.

 

3.) We have to add Name (APSN, 0x04) in the CPU0 scope to keep ACPI_SMC_PlatformPlugin happy. The value 0x04 in the Adaptive Power State Number simply means that we have 4 Turbo Speeds above the normal CPU speed. We found this value in all new MacBookPro 8 series. There it was 6, 9 or 11 and matched with the Intel datasheets of the installed CPU.

 

4.) The number of P-States in the _PSS object in the new MacBookPro 8 series does not match up with the data found in the PerformanceStateArray (checked with ioreg / IORegistryExplorer).

 

5.) The new MacBookPro 8 series have 22 or 26 P-States (depends on model) and like I said; the number of P-States in the ACPI tables are less than the 22 and 26 I see in ioreg / IORegistryExplorer.

 

6.) The Turbo States in the new MacBookPro 8 series use the same amount of power as the normal CPU top speed.

 

7.) Here are the PerformanceStateArray's of the new MacBookPro 8[1/2/3] series:

 

post-669976-1303740791_thumb.png

post-669976-1303740799_thumb.png

post-669976-1303741045_thumb.png

 

Now look at the CPU specifications of the used models:

MBP8,1 = i5-2415M CPU @ 2.30 GHz (Max Turbo Frequency 2.9 GHz / APSN = 6)

MBP8,2 = i7-2635QM CPU @ 2.00 GHz (Max Turbo Frequency 2.9 GHz / APSN = 9)

MBP8,3 = i7-2720QM CPU @ 2.20 GHz (Max Turbo Frequency 3.3 GHz / APSN = 11)

 

That should tell you enough for now :D

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Here are the first new findings:

 

5.) The new MacBookPro 8 series have 22 or 26 P-States (depends on model) and like I said; the number of P-States in the ACPI tables are less than the 22 and 26 I see in ioreg / IORegistryExplorer.

 

I suspect the additional P-States are predefined Turbo States, makes sense to have the regular 16 P-States + APSN = 22 on the i5.

 

For MBP8,2 we start at a lower frequency while having the same freq_max, ergo more additional States to cover the range.

 

 

Looking at the PerformanceStateArray (PSA) we see a direct correlation between base frequency and multiplier.

 

For the MBP8,3 for example we see 0x21 = 33 correlating to a freq_max of 3,3 GHz.

 

In my current PSA the max value of 16 states is 0x3b = 59 which doesn't look right in this context...

 

 

Should be interesting to see if supplying 16 states and setting APSN=0x00 would still work.

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Yup. And here is an example. This is the original P-State object of a MBP8,3 (copied from SSDT-5.dsl aka Cpu0Ist) with 'only' 16 P-States but the PerformanceStateArray has 26:

Name (_PSS, Package (0x10)
{
   Package (0x06) { 0x00000899, 0x0000AFC8, 0x0000000A, 0x0000000A, 0x00002100, 0x00002100 }, 
   Package (0x06) { 0x00000898, 0x0000AFC8, 0x0000000A, 0x0000000A, 0x00001600, 0x00001600 }, 
   Package (0x06) { 0x00000834, 0x0000A518, 0x0000000A, 0x0000000A, 0x00001500, 0x00001500 }, 
   Package (0x06) { 0x000007D0, 0x00009A9D, 0x0000000A, 0x0000000A, 0x00001400, 0x00001400 }, 
   Package (0x06) { 0x0000076C, 0x0000920B, 0x0000000A, 0x0000000A, 0x00001300, 0x00001300 }, 
   Package (0x06) { 0x00000708, 0x000087F6, 0x0000000A, 0x0000000A, 0x00001200, 0x00001200 }, 
   Package (0x06) { 0x000006A4, 0x00007FBF, 0x0000000A, 0x0000000A, 0x00001100, 0x00001100 }, 
   Package (0x06) { 0x00000640, 0x00007613, 0x0000000A, 0x0000000A, 0x00001000, 0x00001000 }, 
   Package (0x06) { 0x000005DC, 0x00006E34, 0x0000000A, 0x0000000A, 0x00000F00, 0x00000F00 }, 
   Package (0x06) { 0x00000578, 0x000064E4, 0x0000000A, 0x0000000A, 0x00000E00, 0x00000E00 }, 
   Package (0x06) { 0x00000514, 0x00005D5C, 0x0000000A, 0x0000000A, 0x00000D00, 0x00000D00 }, 
   Package (0x06) { 0x000004B0, 0x0000546D, 0x0000000A, 0x0000000A, 0x00000C00, 0x00000C00 }, 
   Package (0x06) { 0x0000044C, 0x00004D3F, 0x0000000A, 0x0000000A, 0x00000B00, 0x00000B00 }, 
   Package (0x06) { 0x000003E8, 0x000044AE, 0x0000000A, 0x0000000A, 0x00000A00, 0x00000A00 }, 
   Package (0x06) { 0x00000384, 0x00003C4D, 0x0000000A, 0x0000000A, 0x00000900, 0x00000900 }, 
   Package (0x06) { 0x00000320, 0x0000359B, 0x0000000A, 0x0000000A, 0x00000800, 0x00000800 }
})

Again APSN is set to 11 (0x0b) for this model, and that is exactly where the normal CPU speed is located in the array. Now ask your self this question: If non of the kexts is adding to the table, what does? I think this one solves that puzzle:

        Name (TSSF, 0x00)
       Mutex (TSMO, 0x00)
       Method (_TSS, 0, NotSerialized)
       {
           If (LAnd (LNot (TSSF), CondRefOf (_PSS)))
           {
               Acquire (TSMO, 0xFFFF)
               If (LAnd (LNot (TSSF), CondRefOf (_PSS)))
               {
                   Name (LFMI, 0x00)
                   Store (SizeOf (_PSS), LFMI)
                   Decrement (LFMI)
                   Name (LFMP, 0x00)
                   Store (DerefOf (Index (DerefOf (Index (_PSS, LFMI)), 0x01)), 
                       LFMP)
                   Store (0x00, Local0)
                   If (And (CFGD, 0x00080000))
                   {
                       Store (RefOf (TSMF), Local1)
                       Store (SizeOf (TSMF), Local2)
                   }
                   Else
                   {
                       Store (RefOf (TSMC), Local1)
                       Store (SizeOf (TSMC), Local2)
                   }

                   While (LLess (Local0, Local2))
                   {
                       Store (Divide (Multiply (LFMP, Subtract (Local2, Local0)), Local2, 
                           ), Local4)
                       Store (Local4, Index (DerefOf (Index (DerefOf (Local1), Local0)), 0x01
                           ))
                       Increment (Local0)
                   }

                   Store (Ones, TSSF)
               }

               Release (TSMO)
           }

           If (And (CFGD, 0x00080000))
           {
               Return (TSMF)
           }
           Else
           {
               Return (TSMC)
           }
       }

At least that's the only place in the ACPI files where _PSS is being used. No idea what it does however!

 

Note: I also have the other ACPI tables, of the MBP8,1 and 8,2 but it is too much work to change the data.

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Comparing PSA and _PSS the sudden jump from 0x16 to 0x21 is very strange, it seems the last p-state defines the freq_max and this mysterious function is filling in the ones between.

 

Again, comparing this to my current p-states, I have continuous values with no max value.

 

Using that function would be great, as we only need to supply one extra p-state (read: replace p[15]). Still, how would we fabricate that last one?

 

 

EDIT: According to the ACPI specs: Throttling Supported States (_TSS) – returns supported throttling state information (p. 321), it's definitely the right spot!

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Yeah. I need to have another look tomorrow. Right after school. Need to get some sleep now (is 2AM already) so good night for now...

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OK, using the current information I crafted a new PSS for my i5-2500K:

Name (PSS, Package (0x10)
{
/*  Core Frequency (MHz), Power (milliwats), Latency (ms), Bus Latency (ms), Control, Status */
           Package (0x06) { /* 3301 MHz */ 0xCE5, Zero, 10, 10, /* 37 */ 0x2500, 0x2500 },
           Package (0x06) { /* 3300 MHz */ 0xCE4, Zero, 10, 10, /* 33 */ 0x2100, 0x2100 }, 
           Package (0x06) { /* 3200 MHz */ 0xC80, Zero, 10, 10, /* 32 */ 0x2000, 0x2000 }, 
           Package (0x06) { /* 3100 MHz */ 0xC1C, Zero, 10, 10, /* 31 */ 0x1F00, 0x1F00 }, 
           Package (0x06) { /* 3000 MHz */ 0xBB8, Zero, 10, 10, /* 30 */ 0x1E00, 0x1E00 }, 
           Package (0x06) { /* 2900 MHz */ 0xB54, Zero, 10, 10, /* 29 */ 0x1D00, 0x1D00 }, 
           Package (0x06) { /* 2800 MHz */ 0xAF0, Zero, 10, 10, /* 28 */ 0x1C00, 0x1C00 }, 
           Package (0x06) { /* 2700 MHz */ 0xA8C, Zero, 10, 10, /* 27 */ 0x1B00, 0x1B00 }, 
           Package (0x06) { /* 2600 MHz */ 0xA28, Zero, 10, 10, /* 26 */ 0x1A00, 0x1A00 }, 
           Package (0x06) { /* 2500 MHz */ 0x9C4, Zero, 10, 10, /* 25 */ 0x1900, 0x1900 }, 
           Package (0x06) { /* 2400 MHz */ 0x960, Zero, 10, 10, /* 24 */ 0x1800, 0x1800 }, 
           Package (0x06) { /* 2300 MHz */ 0x8FC, Zero, 10, 10, /* 23 */ 0x1700, 0x1700 },
           Package (0x06) { /* 2200 MHz */ 0x898, Zero, 10, 10, /* 22 */ 0x1600, 0x1600 }, 
           Package (0x06) { /* 2100 MHz */ 0x834, Zero, 10, 10, /* 21 */ 0x1500, 0x1500 }, 
           Package (0x06) { /* 2000 MHz */ 0x7D0, Zero, 10, 10, /* 20 */ 0x1400, 0x1400 }, 
           Package (0x06) { /* 1600 MHz */ 0x640, Zero, 10, 10, /* 16 */ 0x1000, 0x1000 }
})

 

1) The first state defines the TurboMode

 

2) APSN is the difference (0x25 - 0x21 = 0x04) of normal and turbo control bit

 

3) MagicFunction or SMCPlatform replaces the TurboMode p-state with scaled frequencies of #APSN

 

For example, looking at the PerformanceStateArray of MBP8,3 we see the top most frequencies of 0xCE4 = 3300 and 0xC80 = 3200. The TurboMode state 0x899 = 2201 was replaced.

 

4) Power in mW is missing, how do I get those?

 

For the MBP8,3 0xAFC8 = 45000mW = 45W TDP, so it should be max 95W for my model, but how do those values get scaled? No info in the intel docs as far as I can see.

 

5) We need to fill the values in MCST again?

 

6) Observation: AICPUPM is crashing even if EIST & TM is disabled, is it loading for any one else?

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It turns out that the reason your method for Audio not working, as well as the proper displaying of the Sata controller was because of this line in your Info.plist,

			<key>IONameMatch</key>
		<array>
			<string>pci8086,1c03</string>
		</array>

 

My board (Asus P8P67 Rev 3 Vanilla) has a cheaper? AHCI controller and is identified by device ID 1c02, though the address appears to be the same @1F,2 - so adding another string for it works. Thanks a lot for your work DHP!

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Good find! Do you have additional PCI-cards installed for any chance?

 

My Atheros WLAN-adapter doesn't work with Sam's DSDT at the moment, and I suspected AHCI already.

 

Do you have a PEX and BR device showing up in IOReg? Without the DSDT I have those and WLAN is working via AtherosFix (plist injection), with I only see pci_bridge.

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Good find! Do you have additional PCI-cards installed for any chance?

 

My Atheros WLAN-adapter doesn't work with Sam's DSDT at the moment, and I suspected AHCI already.

 

Do you have a PEX and BR device showing up in IOReg? Without the DSDT I have those and WLAN is working via AtherosFix (plist injection), with I only see pci_bridge.

 

I don't have any of those devices, because in Sam's DSDT they're called rp*, I'm not sure what BR is. I diff'd her original factory AML and my original AML, and there were some discrepancies with some of the devices and I made the corrections, but I could've overlooked some. I also made some changes where she said the holy grail of sleep, but that still didn't correct sleep for me.

 

I still have the LAN issue as well, the DSDT devices are setup correct (I think), and Chameleon is injecting the device properties, but I get this error,

4/26/11 1:47:25 PM	kernel	AppleRTL8169Ethernet: Unknown hardware version ID (2c000000)

, so I assume the driver doesn't support 8111E like our boards have? Not sure about this one.

 

I attached my factory dsdt and my modified one.

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I still have the LAN issue as well, the DSDT devices are setup correct (I think), and Chameleon is injecting the device properties, but I get this error, so I assume the driver doesn't support 8111E like our boards have? Not sure about this one.

 

For LAN I'm using http://lnx2mac.blogspot.com/p/realtekrtl81xx-osx-driver.html - working very well, not sure if our chip would work vanilla.

 

EDIT2: OK, so SAT0@1F,2 <pci8086,1c02> is working beautifully and AppleAHCI gets recognized.

We only need to change the matching in the plist, not in the DSDT.

 

For reference, here is my lspci:

00:00.0 Host bridge: Intel Corporation Device 0100 (rev 09)
00:01.0 PCI bridge: Intel Corporation Device 0101 (rev 09)
00:16.0 Communication controller: Intel Corporation Cougar Point HECI Controller #1 (rev 04)
00:1a.0 USB Controller: Intel Corporation Cougar Point USB Enhanced Host Controller #2 (rev 05)
00:1c.0 PCI bridge: Intel Corporation Cougar Point PCI Express Root Port 1 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Cougar Point PCI Express Root Port 2 (rev b5)
00:1c.2 PCI bridge: Intel Corporation Cougar Point PCI Express Root Port 3 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Cougar Point PCI Express Root Port 4 (rev b5)
00:1c.4 PCI bridge: Intel Corporation Cougar Point PCI Express Root Port 5 (rev b5)
00:1c.5 PCI bridge: Intel Corporation Cougar Point PCI Express Root Port 6 (rev b5)
00:1c.6 PCI bridge: Intel Corporation 82801 PCI Bridge (rev b5)
00:1c.7 PCI bridge: Intel Corporation Cougar Point PCI Express Root Port 8 (rev b5)
00:1d.0 USB Controller: Intel Corporation Cougar Point USB Enhanced Host Controller #1 (rev 05)
00:1f.0 ISA bridge: Intel Corporation Device 1c46 (rev 05)
00:1f.2 SATA controller: Intel Corporation Cougar Point 6 port SATA AHCI Controller (rev 05)
00:1f.3 SMBus: Intel Corporation Cougar Point SMBus Controller (rev 05)
01:00.0 VGA compatible controller: nVidia Corporation G92 [GeForce GTS 250] (rev a2)
03:00.0 USB Controller: NEC Corporation Device 0194 (rev 04)
06:00.0 USB Controller: NEC Corporation Device 0194 (rev 04)
07:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 06)
08:00.0 PCI bridge: Device 1b21:1080 (rev 01)
09:00.0 Ethernet controller: Atheros Communications Inc. Atheros AR5001X+ Wireless Network Adapter (rev 01)
09:01.0 Multimedia audio controller: C-Media Electronics Inc CM8738 (rev 10)
0a:00.0 SATA controller: Device 1b4b:9172 (rev 11)

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