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GA-EX58 and GA-X58A DSDT native power management modifications

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Booting in 32 bit sometimes I got a KP after wake when starting some non Apple applications.

Now I'm booting in 64 bit and don't have that problem anymore.

still have this problem even with 64 bit:(

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still have this problem even with 64 bit:(
Are you still using F9e?

You might want to try F9m.

I also updated the i7 920 and Xeon W3520 DSDT.aml and dsdt.dsl attached to post 1 to be derived from this version.

Some corrections were made to the CStates of the CPU section of the instructions and DSDT attachments as of F9m, and this solves the issue of 32 bit boot and KP after wake when starting some non Apple applications.

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Are you still using F9e?

You might want to try F9m.

I also updated the i7 920 and Xeon W3520 DSDT.aml and dsdt.dsl attached to post 1 to be derived from this version.

Some corrections were made to the CStates of the CPU section of the instructions and DSDT attachments as of F9m, and this solves the issue of 32 bit boot and KP after wake when starting some non Apple applications.

Does using DVID and the modified MacPro4_1.plist still prevent waking from S3 on F9m? And do I have to change to C2RC4 to get it to work? Currently I have PC-EFI 10.5.

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Does using DVID and the modified MacPro4_1.plist still prevent waking from S3 on F9m? And do I have to change to C2RC4 to get it to work? Currently I have PC-EFI 10.5.
Yes, in my experience using DVID and the modified MacPro4_1.plist still prevents waking from S3 with F9m, even with a DSDT derived from F9m and with correct CStates.

I haven't tried this with C2RC3 and netkas's 10.5 boot though, I use C2RC4.

Another factor may be HPET Mode, I use 32-bit mode with both 32 and 64 bit boot.

There has been one KP after wake with 64 bit boot over a period of eight days, so my next step will be to try 64-bit mode for HPET if that wasn't just an anomaly.

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I asked a few pages back but didn't seem to get a reply. Can someone point me in the right direction to some kind of guide for getting SATA hotplugging working. Thanks!

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I asked a few pages back but didn't seem to get a reply. Can someone point me in the right direction to some kind of guide for getting SATA hotplugging working. Thanks!
I don't know of a way to make this work with the Intel ports, and I don't use the JMicron ones, perhaps someone else has done this and can comment.

The drive in the external SATA enclosure that I have is only seen after reboot, perhaps because Apple hardware doesn't have eSATA ports, and therefore the capability isn't coded for.

However, once the drive is seen it can be unmounted from the Finder, and remounted from Disk Utility.

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Added to post 1:

 

16. (added 20091223) Thanks to mm67 for a modification that enables shutdown, so that EvOreboot.kext or similar isn't needed;

http://www.insanelymac.com/forum/index.php...2518&st=743 (start with post 744)

 

A kext would still be needed if you want restart functionality, unless you use Duvel300's patched boot;

http://www.insanelymac.com/forum/index.php...2518&st=870 (start with post 871)

 

Add the following before `OperationRegion (\AGPS, SystemIO, 0x0438, 0x04)'.

   OperationRegion (PMRS, SystemIO, 0x0430, 0x01)
   Field (PMRS, ByteAcc, NoLock, Preserve)
   {
       , 4,
       SLPE, 1
   }

Also, in `Method (\_PTS, 1, NotSerialized)' change the following.

 

original:

       If (LEqual (Arg0, 0x05))
       {
           Store (0x99, SMIP)
       }

modified:

       If (LEqual (Arg0, 0x05))
       {
           Store (Zero, SLPE)
           Sleep (0x10)
       }

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Playing alot with F9e & F9m bios, Sleep working again.

Steps that i follow :

1. Flashing older F9e Bios

2. Using older & newer dsdt.aml (from dood's 1st post), sleep wasn't working.

3. Flashing newer bios again (F9m)

4. Using newer dsdt.aml and after some reboots, sleep wasn't working ....

5. Pressing CLEAR CMOS button 2-3 times ---> Sleep is working .

 

Some times, when BCLK is greater than 185 Mhz, turbo ratios 1112 are not enabled. Sleep still working ...

 

But if Intel Turbo .. is disabled, turbo ratios are always enabled and sleep still working (without any KP since morning)

if Intel turbo boost is enabled, sleep still working ... anyway ....

 

Actually i think that Clear Cmos button is the magic button in the whole story.

/E/E folder contains : Alc889a, Evoreboot, fakesmc, JmicronAta

Cham V2 Rc4, modified MacPro4.1plist, DooD's dsdt for i7 950, 64bit

 

EDIT :

 

Ambient Temp ~20 C, Idle Temp 27-32 C,

Running Mprime for ~10 mins, Stress Temp <80 C.

 

These are my current Bios Values :

BCLK 180 - 195

X23 or X24

All power management values enabled,

Qpi Clock X36,

Uncore Clock Ratio X16

Isochronous support Enabled,

Cpu Clock Drive 700mV

PCI-E clock Drive 700mV

Load Line Calibration Enabled

DVID +0.15625 V

Pc Health Status Bios Vcore ~ 1.396 V

All other Values AUTO (I think :) )

 

GeekBench 64bit 14000 - 14600

 

 

DooD, Thanks Again for your great work !

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Playing alot with F9e & F9m bios, Sleep working again.

Steps that i follow :

1. Flashing older F9e Bios

2. Using older & newer dsdt.aml (from dood's 1st post), sleep wasn't working.

3. Flashing newer bios again (F9m)

4. Using newer dsdt.aml and after some reboots, sleep wasn't working ....

5. Pressing CLEAR CMOS button 2-3 times ---> Sleep is working .

 

Some times, when BCLK is greater than 185 Mhz, turbo ratios 1112 are not enabled. Sleep still working ...

 

But if Intel Turbo .. is disabled, turbo ratios are always enabled and sleep still working (without any KP since morning)

if Intel turbo boost is enabled, sleep still working ... anyway ....

 

Actually i think that Clear Cmos button is the magic button in the whole story.

/E/E folder contains : Alc889a, Evoreboot, fakesmc, JmicronAta

Cham V2 Rc4, modified MacPro4.1plist, DooD's dsdt for i7 950, 64bit

 

EDIT :

 

Ambient Temp ~20 C, Idle Temp 27-32 C,

Running Mprime for ~10 mins, Stress Temp <80 C.

 

These are my current Bios Values :

BCLK 180 - 195

X23 or X24

All power management values enabled,

Qpi Clock X36,

Uncore Clock Ratio X16

Isochronous support Enabled,

Cpu Clock Drive 700mV

PCI-E clock Drive 700mV

Load Line Calibration Enabled

DVID +0.15625 V

Pc Health Status Bios Vcore ~ 1.396 V

All other Values AUTO (I think :) )

 

GeekBench 64bit 14000 - 14600

 

DooD, Thanks Again for your great work !

You're welcome.

Very good temperatures and geekbench, is that with the not free 64 bit version?

It's good to read that sleep is working for you, do you have any problem waking from sleep using DVID and the modified MacPro4_1.plist?

The turbo behavior isn't right, I'd suggest setting `Keep DMI Data' to Disable when flashing the BIOS, and then start with `Load Optimized Defaults' before setting your over clock.

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Wake from sleep is instant without any KP. Geekbench is free version. I always follow Gigabyte procedures when flashing bios. Overclocking made step by step (5-10 mins from one step to another).

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i have to unplug and replug in my usb bluetooth dongle to get it work again after wake from sleep. I get KP lately when i do it. Does anybody have the same experience or know a workaround?

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Update 3: Using DVID and the modified MacPro4_1.plist prevents waking from S3 if using a device-properties video string in com.apple.Boot.plist.

Using DVID and the modified MacPro4_1.plist with GraphicsEnabler=yes (and PciRoot=1 for C2RC4, which has a default of 0) in com.apple.Boot.plist doesn't prevent waking from S3.

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5. For CPU0 through CPU7, make the following change to pass the CStates to OS X.

This is only needed when clocked over a certain point (148x20 or 2.96 GHz for a i7 920 or Xeon W3520 CPU), as it seems that the Gigabyte BIOS doesn't make the CStates available to the OS above that, even with all energy saving options enabled in the BIOS's Advanced CPU Features section.

If you convert the hexadecimal you will find that the PStates represent the default clock of your CPU, but it won't down clock your CPU if over clocked, and is what the BIOS makes available to the OS at default or over clock.

 

d00d,

 

Amazing guide! Thank you. I'm however stuck on step 5. I have a Core i7 920 C0 stepping so in order not to fry it I tried the following:

 

1) In BIOS, set my clock to 2.66 (133 x 20)

2) In BIOS, Enabled C1E and C3/C6/C7

3) Removed DSDT.aml from /Extra

4) Rebooted

5) Ran DSDTSE 1.43 and extracted SSDT (attached below)

 

My CStates appear to be the same as yours but I don't have 10 PStates. In fact I don't have any. Instead I have 8 TStates. Would you be kind enough to tell me what I'm doing wrong? This is all new territory for me. Any and all help appreciated. Thank you.

Core_i7_920_C0_Stepping_SSDT.txt

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d00d,

 

Amazing guide! Thank you. I'm however stuck on step 5. I have a Core i7 920 C0 stepping so in order not to fry it I tried the following:

 

1) In BIOS, set my clock to 2.66 (133 x 20)

2) In BIOS, Enabled C1E and C3/C6/C7

3) Removed DSDT.aml from /Extra

4) Rebooted

5) Ran DSDTSE 1.43 and extracted SSDT (attached below)

 

My CStates appear to be the same as yours but I don't have 10 PStates. In fact I don't have any. Instead I have 8 TStates. Would you be kind enough to tell me what I'm doing wrong? This is all new territory for me. Any and all help appreciated. Thank you.

Thanks.

EIST also needs to be enabled to see the ten PStates.

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Thanks.

EIST also needs to be enabled to see the ten PStates.

 

Thank you for the quick reply. That was exactly the problem. FYI, my PStates were identical to yours except they were formatted like this:

 

                    Package (0x06)
                   {
                       0x00000A65, 
                       0x0001FBD0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000015, 
                       0x00000015
                   }, 

                   Package (0x06)
                   {
                       0x00000A64, 
                       0x0001FBD0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000014, 
                       0x00000014
                   }, 

                   Package (0x06)
                   {
                       0x000009DF, 
                       0x0001A9C8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000013, 
                       0x00000013
                   }, 

                   Package (0x06)
                   {
                       0x0000095A, 
                       0x000186A0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000012, 
                       0x00000012
                   }, 

                   Package (0x06)
                   {
                       0x000008D5, 
                       0x00014438, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000011, 
                       0x00000011
                   }, 

                   Package (0x06)
                   {
                       0x00000850, 
                       0x000128E0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000010, 
                       0x00000010
                   }, 

                   Package (0x06)
                   {
                       0x000007CB, 
                       0x0000F618, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000F, 
                       0x0000000F
                   }, 

                   Package (0x06)
                   {
                       0x00000746, 
                       0x0000DEA8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000E, 
                       0x0000000E
                   }, 

                   Package (0x06)
                   {
                       0x000006C1, 
                       0x0000B798, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000D, 
                       0x0000000D
                   }, 

                   Package (0x06)
                   {
                       0x0000063C, 
                       0x0000A7F8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000C, 
                       0x0000000C
                   }

It's probably not important but I used mine instead just to be safe. My idle temp is about 10C lower now. I've updated my sig to reflect my current settings. Please keep up the great work.

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Thank you for the quick reply. That was exactly the problem. FYI, my PStates were identical to yours except they were formatted like this:

 

                    Package (0x06)
                   {
                       0x00000A65, 
                       0x0001FBD0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000015, 
                       0x00000015
                   }, 

                   Package (0x06)
                   {
                       0x00000A64, 
                       0x0001FBD0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000014, 
                       0x00000014
                   }, 

                   Package (0x06)
                   {
                       0x000009DF, 
                       0x0001A9C8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000013, 
                       0x00000013
                   }, 

                   Package (0x06)
                   {
                       0x0000095A, 
                       0x000186A0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000012, 
                       0x00000012
                   }, 

                   Package (0x06)
                   {
                       0x000008D5, 
                       0x00014438, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000011, 
                       0x00000011
                   }, 

                   Package (0x06)
                   {
                       0x00000850, 
                       0x000128E0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000010, 
                       0x00000010
                   }, 

                   Package (0x06)
                   {
                       0x000007CB, 
                       0x0000F618, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000F, 
                       0x0000000F
                   }, 

                   Package (0x06)
                   {
                       0x00000746, 
                       0x0000DEA8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000E, 
                       0x0000000E
                   }, 

                   Package (0x06)
                   {
                       0x000006C1, 
                       0x0000B798, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000D, 
                       0x0000000D
                   }, 

                   Package (0x06)
                   {
                       0x0000063C, 
                       0x0000A7F8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000C, 
                       0x0000000C
                   }

It's probably not important but I used mine instead just to be safe. My idle temp is about 10C lower now. I've updated my sig to reflect my current settings. Please keep up the great work.

what's your idle temp now?

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Thank you for the quick reply. That was exactly the problem. FYI, my PStates were identical to yours except they were formatted like this:

 

                    Package (0x06)
                   {
                       0x00000A65, 
                       0x0001FBD0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000015, 
                       0x00000015
                   }, 

                   Package (0x06)
                   {
                       0x00000A64, 
                       0x0001FBD0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000014, 
                       0x00000014
                   }, 

                   Package (0x06)
                   {
                       0x000009DF, 
                       0x0001A9C8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000013, 
                       0x00000013
                   }, 

                   Package (0x06)
                   {
                       0x0000095A, 
                       0x000186A0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000012, 
                       0x00000012
                   }, 

                   Package (0x06)
                   {
                       0x000008D5, 
                       0x00014438, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000011, 
                       0x00000011
                   }, 

                   Package (0x06)
                   {
                       0x00000850, 
                       0x000128E0, 
                       0x0000000A, 
                       0x0000000A, 
                       0x00000010, 
                       0x00000010
                   }, 

                   Package (0x06)
                   {
                       0x000007CB, 
                       0x0000F618, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000F, 
                       0x0000000F
                   }, 

                   Package (0x06)
                   {
                       0x00000746, 
                       0x0000DEA8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000E, 
                       0x0000000E
                   }, 

                   Package (0x06)
                   {
                       0x000006C1, 
                       0x0000B798, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000D, 
                       0x0000000D
                   }, 

                   Package (0x06)
                   {
                       0x0000063C, 
                       0x0000A7F8, 
                       0x0000000A, 
                       0x0000000A, 
                       0x0000000C, 
                       0x0000000C
                   }

It's probably not important but I used mine instead just to be safe. My idle temp is about 10C lower now. I've updated my sig to reflect my current settings. Please keep up the great work.

Thanks.

The PState values in my instructions for editing DSDT.dsl are what the compiler changes them to in DSDT.aml.

So if you use a line like `0x00000A65,' in DSDT.dsl for example, it changes to `0x0A65,' when compiled into DSDT.aml.

Hexadecimal 0x00000A65 is the same as hexadecimal 0x0A65 (decimal 2661);

0x0A65, // 2661 MHz core frequency

0x0001FBD0, // 130000 mW power

0x0A, // 10 us transition latency

0x0A, // 10 us transition latency

0x15, // 21 multiplier

0x15 // 21 multiplier

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LocusOfControl,

 

I am just happy now my idle sleep is working properly even though the timing is not accurate to the setting in Energy Saver. I did a test last night by using Handbrake to rip a movie from DVD. I set up my computer to go to sleep after 15 minutes. I was happy to find that my computer was asleep this morning and the movie did finish. It means now that I can have activities running and not worrying about the Autosleep script from kicking in. Thanks for your help.

 

@ttgolf

 

How is your sleep working? I got idle sleep to work originally after about 1.5 - 2.0 hrs, a bit of fiddling later I had it

sleeping at about 40 min but it sometimes breaks this rule

 

With wake from BT off, idle sleep still working perfectly

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what's your idle temp now?

 

I idle at 37C. I'm only overclocked to 3.33ghz (specs below). My machine is quieter now too. My 3 case fans (Arctic Cooling) are linked to my CPU fan via PWM sharing. I ran MPrime and topped out at 70C.

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There's a solution to make resume after sleep to work properly without requiring user to tick the "Start up automatically after a power failure" checkbox.

 

Guys at the DSDT fixes for Gigabyte boards thread narrowed down the problem to the GEN_PMCON_3 register (spec page 454, see description for bit 0).

 

First you need to define operation region in the Device (PX40):

				OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
			Field (LPC0, ByteAcc, NoLock, Preserve)
			{
				AG3E,   1
			}

For example:

			Device (PX40)
		{
			Name (_ADR, 0x001F0000)
			Method (_DSM, 4, NotSerialized)
			{
				Store (Package (0x02)
					{
						"device-id", 
						Buffer (0x04)
						{
							0x18, 0x3A, 0x00, 0x00
						}
					}, Local0)
				DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
				Return (Local0)
			}

			OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
			Field (LPC0, ByteAcc, NoLock, Preserve)
			{
				AG3E,   1
			}

			/* snip */

And change the Method (_PTS) to look like this:

	Method (_PTS, 1, NotSerialized)
{
	Or (Arg0, 0xF0, Local0)
	Store (Local0, DBG1)
	OSTP()

	If (LEqual (Arg0, 0x05))
	{
		Store (0x99, SMIP)
		Store (One, \_SB.PCI0.PX40.AG3E)
		Store (Zero, SLPE)
		Sleep (0x10)
	}
	Else
	{
		Store (Zero, \_SB.PCI0.PX40.AG3E)
	}
}

After the above changes sleep should work even if the "Start up automatically after a power failure" checkbox is unchecked.

 

EDIT:

I'll attach my dsdt just in case if I {censored}ed up something when porting the _PTS method to the dsdt in the first post.

dsdt.zip

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There's a solution to make resume after sleep to work properly without requiring user to tick the "Start up automatically after a power failure" checkbox.

 

Guys at the DSDT fixes for Gigabyte boards thread narrowed down the problem to the GEN_PMCON_3 register (spec page 454, see description for bit 0).

Thanks, I have that topic open in one of my Firefox tabs, but missed this particular modification.

I'll try it out and include it in the instructions in post 1.

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There's a solution to make resume after sleep to work properly without requiring user to tick the "Start up automatically after a power failure" checkbox.

 

Guys at the DSDT fixes for Gigabyte boards thread narrowed down the problem to the GEN_PMCON_3 register (spec page 454, see description for bit 0).

 

First you need to define operation region in the Device (PX40):

				OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
			Field (LPC0, ByteAcc, NoLock, Preserve)
			{
				AG3E,   1
			}

For example:

			Device (PX40)
		{
			Name (_ADR, 0x001F0000)
			Method (_DSM, 4, NotSerialized)
			{
				Store (Package (0x02)
					{
						"device-id", 
						Buffer (0x04)
						{
							0x18, 0x3A, 0x00, 0x00
						}
					}, Local0)
				DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
				Return (Local0)
			}

			OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
			Field (LPC0, ByteAcc, NoLock, Preserve)
			{
				AG3E,   1
			}

			/* snip */

And change the Method (_PTS) to look like this:

	Method (_PTS, 1, NotSerialized)
{
	Or (Arg0, 0xF0, Local0)
	Store (Local0, DBG1)
	OSTP()

	If (LEqual (Arg0, 0x05))
	{
		Store (0x99, SMIP)
		Store (One, \_SB.PCI0.PX40.AG3E)
		Store (Zero, SLPE)
		Sleep (0x10)
	}
	Else
	{
		Store (Zero, \_SB.PCI0.PX40.AG3E)
	}
}

After the above changes sleep should work even if the "Start up automatically after a power failure" checkbox is unchecked.

 

EDIT:

I'll attach my dsdt just in case if I {censored}ed up something when porting the _PTS method to the dsdt in the first post.

dsdt.zip

 

Is this a generic feature? just looking at one of your earlier posts it looked like you had a non gigabyte board

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Is this a generic feature? just looking at one of your earlier posts it looked like you had a non gigabyte board

 

Well, according to the specification it should work on all ICH9 and ICH10 boards (earlier versions may support it too). I don't know if all manufacturers of ICH[9,10] motherboards comply to spec, but those who do should have this feature consistently working across all their boards.

 

And yes I've had the MSI P35 Platinum board, but just recently I got myself the Gigabyte GA-EX58-UD5.

 

A few details about the DSDT I posted earlier:

  1. It has all OS detection stuff stripped out
  2. It includes almost all modifications from the first post. I haven't changed the _PR scope because my board is not overclocked. You need to enable CStates in the Advanced Processor Features (not sure if I named it right) for AppleIntelCPUPowerManagement to work.
  3. No IDE.
  4. No PIC, only APIC.
  5. No PS/2.

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