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FKA

DSDT - Vanilla Speedstep - Generic Scope (_PR)

1,949 posts in this topic

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Right. Which is what I am trying to do.

 

The guide says to use that in order to get the PStates for the DSDT so that I am able to patch accordingly.

 

Is there a different way now?

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Yes, the method discussed in this topic was made obsolete by the Chameleon boot loader back in July 2010.

You don't need to patch anything (except maybe LPC device ID) just follow the directions given here and make sure you're using a recent version of Chameleon:

http://www.insanelym...howtopic=225766

Don't use any files from that topic, they're too old. The basic information there still applies, except com.apple.Boot.plist is now org.chameleon.Boot.plist. Lots of interesting information in that topic if you care to read it. Including answers to any questions you can come up with about how to proceed.

If necessary, read here for different approaches to patching AppleLPC.kext:

http://www.projectos...findpost&p=2532

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Would following those get me to where I don't need to use speed stepper on appleintelcpupm?

 

That's what I am trying to accomplish.

 

I have LPC show up in my IOREG, and I believe I have all the info from above.

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Looks like I have some reading to do. Thanks!

 

EDIT: Although, one question. I need to patch appleLPC even though its in IOREG or no?

 

I'd rather not read all about that if I don't need to.

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No, otherwise I'd be pounding you with how to not need speedstep. :P I'm reading the other thread so I don't have to look for that since that seems easy.

 

Thanks!

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LOL no problem.

 

What the hell, I have nothing better to do right now:

 

After installing a recent version of Chameleon and making sure everything is working, the first step is to undo any and all modifications done to your DSDT processor scope in your DSDT. The processor scope is referenced in other ACPI tables - if you have made any of the modifications discussed earlier in this topic you will will break these references and native power state switching will not work.

Then add GenerateCStates=y and GeneratePStates=y string/keys to your /Extra/org.Chameleon.Boot.plist.

 

If AppleLPC.kext is already loading on your hardware then that's it. Reboot.

 

On a Wolfdale Core 2 Duo CPU you should now see 8 fields under PerformanceStateArray in ACPI_SMC_Platformplugin in ioregistryexplorer. Those are your P-states. If you see something like AICPMVers=0x1240105 at the top, that means C-states are working. If not, run Console.app and look for C-state error messages in kernel.log.

 

In Energy Saver preferences, you should now see a new option, "start up automatically after a power failure".

 

Try these in Terminal.app:

 

sudo setpci -s 0:1f.0 0xa6.b - outputs 80 if CPU has entered C4 state

sudo setpci -s 0:1f.0 0x0a.w - outputs 06a0 if C4 is supported

 

Note that on some motherboards those commands don't do anything at all, but that doesn't mean that C-states aren't working.

 

You can try dumping your SSDT tables and have Chameleon load those as well. Note that they must be named as outlined in the first post in the other topic.

Before dumping the SSDT tables (Use Everest in Windows, or you can use a Linux Live CD, google for a how-to) make sure all advanced CPU settings (except CPUID Limit) are enabled in the BIOS, ie all supported C-states. Under Power Management, make sure ACPI 2.0 and ACPI APIC are enabled.

Name the tables as shown, place them in /Extra, then add a DropSSDT=y string/key to your /Extra/org.chameleon.Boot.plist.

 

On a Wolfdale Core 2 Duo CPU, instead of 8 P-states (like on an iMac or MacBook) you will now see the same four P-states that you have in Windows.

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I just switched to a more appropriate SMBIOS and was able to boot with the native one.

 

I have generate c and p states, as well as drop ssdt. Supposing that it has the AICPMVers=0x1240102, do I need to do anything?

 

Are the dumping of the SSDT's needed still?

 

Thanks for the help so far!

 

edit- it does say the 0x124012 or whatever the exact numbers are, however I do not see the 8 items under the performance state array.

 

I just reread your post and now see you say that I should still dump the SSDT's.

 

I will do so tomorrow, as I don't have a linux disc with me.

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Don't use DropSSDT=y if you didn't dump your SSDT tables!

 

I told you everything I know, what I wrote up there are the only ways I can think of right now to check that everything is working.

It should work without it, but If you'd like to explore further and see if anything changes try dumping your SSDT tables and set DropSSDT=y.

 

8 P-states is just what I got, if you have a different CPU you might have more or less. There's nothing under PerformanceStateArray?

 

I thought 8 P-states was a bit much, but when loading my SSDT tables I get the normal four for my CPU. Your mileage may vary.

 

Yes, using an appropriate model identifier (ie one that's a good match for your hardware) is very important when it comes to native power management.

 

I don't think anybody knows what the AICPM value means, but everybody seems to agree that when C-states aren't working, it doesn't appear there at all.

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Alright, will change that until I get that opportunity.

 

Thanks a ton.

 

And yeah, I chose a MBP originally since it was almost identical hardware wise, but it has a i5 instead of an i3 so this works better.

 

Thanks again.

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Goodness. I have 14 values under performancestatearray now I booted with dropssdt=no.

 

Do you have a guide on how to extract SSDT with linux?

 

I cannot find anything that seems to work, they all require acpidump, which won't install with apt-get.

 

edit- cosmetic detail- do you know of any way that I can make system profiler show the MBP8,1 or 8,1 instead of iMac, while still using the iMacs PM?

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Check in the DSDT subforum on how to get acpidump, I pinned a topic about it earlier today.

 

About the iMac powermanagement - I'm sure you can find a suitable macbook model identifier that will give you the same thing. Anyway it shouldn't matter much once you have the SSDT tables dumped, then you ought to get the same power states no matter which of the suitable model identifiers you use, and you can go back to using MBP8,1. I guess. I have no hands-on Hackintosh experience with Core i CPUs and model identifiers, and none at all with laptops.

 

I don't know how to make cosmetic modifications, I don't use them.

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Thanks. Last questions then I am done.

 

1- Are SSDT's BIOS rev. dependent?

 

2- I had 14 PerformanceStateArray Values. After adding dropssdt=yes and the 7 extracted SSDTs, I still have 14. Is that normal? Or should it be 7?

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1. Yes definitely, since ACPI tables are part of the BIOS they can be updated as well. If you upgrade your BIOS you should definitely redump your SSDTs and your DSDT.

 

2. As I keep saying, I have no experience with laptops or Core i CPUs. Ideally you should have the same amount of P-states that you have in Windows. Assuming Windows is handling this correctly in the first place.. There is a power management debugging tool available for free from Microsoft that will tell you everything you need to know. Can't recall the name.

 

Extract this bdmesg.zip and use Terminal.app or the "Go" Finder menu to copy bdmesg to /usr/bin. Reboot, then run Terminal and type bdmesg.

 

This should tell you if Chameleon is loading all your SSDT tables properly.

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I'm an idiot. I somehow had reinstalled a patched AppleIntelCPUPM. So none of that helped, except that I now have my SSDT's. However, even with them, I cannot boot without the patched kext. What can I do?

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Try to find out if there are known issues with your particular species of CPU and native power management. Keep in mind that an i3 is not just an i3, there are different steppings and die sizes and so on. Maybe a specific model identifier is required, maybe a specific DSDT patch. Maybe you need a later version of OS X that works better with Core i CPUs.

 

I honestly don't know, I tend to not research a lot about hardware that I don't have.

 

Boot with -v and take a photo of what it looks like when it stops during the boot process. Use the full editor to attach files.

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Hi all!

 

Need help with wake after sleep, my console message is:

 

 

19/03/12 17:58:23,000 kernel: TSC Deadline Timer supported and enabled (This working whitAICPMPatch, with or without DSDT.aml)

 

 

19/03/12 18:02:16,000 kernel: Unsynchronized TSC for cpu 2: 0x00000000ae09b739, delta 0x748076bd (After wake)

19/03/12 18:02:16,000 kernel: Unsynchronized TSC for cpu 1: 0x00000000ae259bdc, delta 0x748076d0

19/03/12 18:02:16,000 kernel: Unsynchronized TSC for cpu 3: 0x00000000ae3e3ba1, delta 0x748076c1

 

My original DSDT.dsl

Original_DSDT.dsl.zip

 

My Original SSDT.dsl

Original_SSDT.dsl.zip

 

My mod DSDT.aml whit SSDT (only work whit AICPMPatch)

Mi_Mod_DSDT_Con_SSDT.aml.zip

 

This is my org.cham

org.chameleon.Boot.plist.zip

 

And my smbios

smbios.plist.zip

 

My specs:

Asrock h67m-itx

I3 2100

Nvidia 9400GT 512

 

Not know what else to try. (sorry for my english)

 

thanks in advance!!!

Original_DSDT.dsl.zip

Original_SSDT.dsl.zip

Mi_Mod_DSDT_Con_SSDT.aml.zip

org.chameleon.Boot.plist.zip

smbios.plist.zip

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There is no voodoo state for 10.9.5,so there is no vid fid for my core 2 quad q9650,too bad.I'm sorry,it works,thank you so much.

 

Q9650 Vanilla speed step 0x0926 0x0821 0x071C 0x0616 4 states, CPU0-3.txt to avoid clover generate P & C states

I got ACPI THRM sensor  panic(cpu 0 caller 0x001A8CD4): Kernel trap at 0x223ab275, type 14=page fault, registers:

problems when I use this patch,so I stop use it.

memory problem

# Insert methods _PSS (4 P-states), _PSD and _CST into CPUs 0-3
#
into method label _PSS parent_label CPU0 remove_entry;
into processor label CPU0 insert
begin
Method (_PSS, 0, NotSerialized)\n
{\n
    Return (Package (0x04)\n
    {\n
        Package (0x06)\n
        {\n
            Zero, \n
            Zero, \n
            0x10, \n
            0x10, \n
            0x0926, // FF = FID, VV = VID\n
            Zero    // P-state 0\n
        }, \n
        Package (0x06)\n
        {\n
            Zero, \n
            Zero, \n
            0x10, \n
            0x10, \n
            0x0821, // FF = FID, VV = VID\n
            One     // P-state 1\n
        }, \n
        Package (0x06)\n
        {\n
            Zero, \n
            Zero, \n
            0x10, \n
            0x10, \n
            0x071C, // FF = FID, VV = VID\n
            0x02    // P-state 2\n
        }, \n
        Package (0x06)\n
        {\n
            Zero, \n
            Zero, \n
            0x10, \n
            0x10, \n
            0x0616, // FF = FID, VV = VID\n
            0x03    // P-state 3\n
        }\n
    })\n
}
end;
into method label _PSD parent_label CPU0 remove_entry;
into processor label CPU0 insert
begin
Method (_PSD, 0, NotSerialized)\n
{\n
    Return (Package (0x05)\n
    {\n
        0x05, \n
        Zero, \n
        Zero, \n
        0xFC, \n
        0x04\n
    })\n
}
end;
into method label _CST parent_label CPU0 remove_entry;
into processor label CPU0 insert
begin
Method (_CST, 0, NotSerialized)\n
{\n
    Return (Package (0x02)\n
    {\n
        One, \n
        Package (0x04)\n
        {\n
            ResourceTemplate ()\n
            {\n
                Register (FFixedHW, \n
                    0x01,               // Bit Width\n
                    0x02,               // Bit Offset\n
                    0x0000000000000000, // Address\n
                    0x01,               // Access Size\n
                    )\n
            }, \n
            One, \n
            0x9D, \n
            0x03E8\n
        }\n
    })\n
}
end;
into method label _PSS parent_label CPU1 remove_entry;
into processor label CPU1 insert
begin
Method (_PSS, 0, NotSerialized)\n
{\n
    Return (^^CPU0._PSS ())\n
}
end;
into method label _PSD parent_label CPU1 remove_entry;
into processor label CPU1 insert
begin
Method (_PSD, 0, NotSerialized)\n
{\n
    Return (^^CPU0._PSD ())\n
}
end;
into method label _CST parent_label CPU1 remove_entry;
into processor label CPU1 insert
begin
Method (_CST, 0, NotSerialized)\n
{\n
    Return (Package (0x04)\n
    {\n
        0x03, \n
        Package (0x04)\n
        {\n
            ResourceTemplate ()\n
            {\n
                Register (FFixedHW, \n
                    0x01,               // Bit Width\n
                    0x02,               // Bit Offset\n
                    0x0000000000000000, // Address\n
                    ,)\n
            }, \n
            One, \n
            Zero, \n
            0x03E8\n
        }, \n
        Package (0x04)\n
        {\n
            ResourceTemplate ()\n
            {\n
                Register (FFixedHW, \n
                    0x08,               // Bit Width\n
                    0x00,               // Bit Offset\n
                    0x0000000000000414, // Address\n
                    ,)\n
            }, \n
            0x02, \n
            One, \n
            0x01F4\n
        }, \n
        Package (0x04)\n
        {\n
            ResourceTemplate ()\n
            {\n
                Register (FFixedHW, \n
                    0x08,               // Bit Width\n
                    0x00,               // Bit Offset\n
                    0x0000000000000415, // Address\n
                    ,)\n
            }, \n
            0x03, \n
            0x55, \n
            0xFA\n
        }\n
    })\n
}
end;
into method label _PSS parent_label CPU2 remove_entry;
into processor label CPU2 insert
begin
Method (_PSS, 0, NotSerialized)\n
{\n
    Return (^^CPU0._PSS ())\n
}
end;
into method label _PSD parent_label CPU2 remove_entry;
into processor label CPU2 insert
begin
Method (_PSD, 0, NotSerialized)\n
{\n
    Return (^^CPU0._PSD ())\n
}
end;
into method label _CST parent_label CPU2 remove_entry;
into processor label CPU2 insert
begin
Method (_CST, 0, NotSerialized)\n
{\n
    Return (^^CPU1._CST ())\n
}
end;
into method label _PSS parent_label CPU3 remove_entry;
into processor label CPU3 insert
begin
Method (_PSS, 0, NotSerialized)\n
{\n
    Return (^^CPU0._PSS ())\n
}
end;
into method label _PSD parent_label CPU3 remove_entry;
into processor label CPU3 insert
begin
Method (_PSD, 0, NotSerialized)\n
{\n
    Return (^^CPU0._PSD ())\n
}
end;
into method label _CST parent_label CPU3 remove_entry;
into processor label CPU3 insert
begin
Method (_CST, 0, NotSerialized)\n
{\n
    Return (^^CPU1._CST ())\n
}
end

post-236960-0-96362100-1443001554_thumb.png

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Hi all:

After i install voodoopstate.kext in /S/L/E then reboot.

Pstatechanger couldn't display any message include FID or VID in PState.

 

Does anyone know the issue??

 

 

My OS: 10.11 EI Capitan.

CPU:i7-5700HQ  HM97

 

sorry about my bad english...

 

thanks for your help...

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Hi all:

After i install voodoopstate.kext in /S/L/E then reboot.

Pstatechanger couldn't display any message include FID or VID in PState.

 

Does anyone know the issue??

 

 

My OS: 10.11 EI Capitan.

CPU:i7-5700HQ  HM97

 

sorry about my bad english...

 

thanks for your help...

??????

 

Why are you using VoodooPState on natively supported hardware?

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