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DSDT: trick retail drivers by changing "device-id" (e.g USB)

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Out of curiosity are you overclocking? I see your speedstepping is for a FSB of 388. I'm running mine at 444 so I had to alter my speedstep _PSS states.

 

Hi

 

Yes 388 x 8 gives me 3.1GHz at around 1.21v, I've had it stable at 455 x 8 and 1.325v but 3.1GHz is enough for me.

 

Even with the Fids and Vids entered in PSS part of DSDT you can still up the FSB in BIOS regardless and it will step to that freq for your p-state 0. Obviously your Vids may be out of range! And when I've tried this OS did seem to run a little choppy, so maybe not recomended.

 

You've just got me thinking - there is also an entry for power in mW in these tables. I wonder if entering a lower power value will effect CPU temp?

 

I'll try this tonight and report.

 

D.

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My EHCI Controllers don't provide any Powermanagement abilities resulting in MacOS X turning them off while sleeping.

 

Aug 16 14:43:42 localhost kernel[0]: USBF:	0.346	AppleUSBOHCI[0x5e7f800]::CheckSleepCapability - controller will be unloaded across sleep
Aug 16 14:43:42 localhost kernel[0]: USBF:	0.346	AppleUSBOHCI[0x6065800]::CheckSleepCapability - controller will be unloaded across sleep

 

 

Anyone knows if this is fixable with a DSDT Patch?

 

take a peek at some of the earlier posts in this thread. A possible solution is talked about.

 

Hi

 

Yes 388 x 8 gives me 3.1GHz at around 1.21v, I've had it stable at 455 x 8 and 1.325v but 3.1GHz is enough for me.

 

Even with the Fids and Vids entered in PSS part of DSDT you can still up the FSB in BIOS regardless and it will step to that freq for your p-state 0. Obviously your Vids may be out of range! And when I've tried this OS did seem to run a little choppy, so maybe not recomended.

 

You've just got me thinking - there is also an entry for power in mW in these tables. I wonder if entering a lower power value will effect CPU temp?

 

I'll try this tonight and report.

 

D.

 

What's the easiest way to verify if my speedstep P-States are functioning properly?

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What's the easiest way to verify if my speedstep P-States are functioning properly?

 

I've been using MSRTools, then run a high demand process like cpu test.

You will see the result of any throttling. It should be smooth - no noticable lagg.

 

You should also notice NO loss of performance in XBench.

 

D.

 

@ kdawg

 

I would rather like to fix it by DSDT patching, not with a modified kext. I love vanilla :(

 

Not possible ATM!

 

Use Slices latest 10.5.8 USB.

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@ kdawg

 

I would rather like to fix it by DSDT patching, not with a modified kext. I love vanilla :(

 

 

I would think since you have a P45 MOBO it would be easy to fix with DSDT since Leopard natively supports ICH10.

 

You don't agree FormerlyKnownAs?

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I would think since you have a P45 MOBO it would be easy to fix with DSDT since Leopard natively supports ICH10.

 

You don't agree FormerlyKnownAs?

 

You're right - I thought you'd already tried the DSDT patch apex?

Give it a go the method is well outlined at by zhell at the start of this thread.

D

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@ formerly known as

 

You refer to the device-id injection? My device-ids are OK, cause i have a ICH10 Board. The only problem are the missing/not provided powermanagement abilities of the EHCI devices :)

 

I sent a bugreport to Gigabyte, but i don't think it will be of much avail.

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@ formerly known as

 

You refer to the device-id injection? My device-ids are OK, cause i have a ICH10 Board. The only problem are the missing/not provided powermanagement abilities of the EHCI devices :)

 

I sent a bugreport to Gigabyte, but i don't think it will be of much avail.

 

@ApexDE

 

See this post:

http://www.insanelymac.com/forum/index.php...t&p=1165031

 

Basically treat it as another USB. However I wouldn't think you would need to even apply this technique. Post your DSDT so we can take a look.

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Treating it as another USB Device "heals" the broken powermanagement infos given by the BIOS?

 

OK, here we go :(

 

 

I'll take a peek at this later tonight.

 

I've been using MSRTools, then run a high demand process like cpu test.

You will see the result of any throttling. It should be smooth - no noticable lagg.

 

You should also notice NO loss of performance in XBench.

 

D.

 

 

 

Not possible ATM!

 

Use Slices latest 10.5.8 USB.

 

@ FormerlyKnownAs

Is 2.66GHz the lowest the Q9450 can go? Basically supporting only three P-States?

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Treating it as another USB Device "heals" the broken powermanagement infos given by the BIOS?

 

OK, here we go :wacko:

 

I also need your lspci info. Download OSX86tools or EFIStudio and use that to output your lspci stuff.

 

It'll look like this:

00:00.0 Host bridge [0600]: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller [8086:29c0] (rev 02)
00:01.0 PCI bridge [0604]: Intel Corporation 82G33/G31/P35/P31 Express PCI Express Root Port [8086:29c1] (rev 02)
00:1a.0 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937] (rev 02)
00:1a.1 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938] (rev 02)
00:1a.2 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939] (rev 02)
00:1a.7 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c] (rev 02)
00:1b.0 Audio device [0403]: Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e] (rev 02)
00:1c.0 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 1 [8086:2940] (rev 02)
00:1c.4 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 5 [8086:2948] (rev 02)
00:1c.5 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 6 [8086:294a] (rev 02)
00:1d.0 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] (rev 02)
00:1d.1 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935] (rev 02)
00:1d.2 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936] (rev 02)
00:1d.7 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a] (rev 02)
00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev 92)
00:1f.0 ISA bridge [0601]: Intel Corporation 82801IR (ICH9R) LPC Interface Controller [8086:2916] (rev 02)
00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02)
00:1f.3 SMBus [0c05]: Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930] (rev 02)
01:00.0 VGA compatible controller [0300]: nVidia Corporation GeForce 8800 GT [10de:0611] (rev a2)
02:00.0 VGA compatible controller [0300]: nVidia Corporation GeForce 8500 GT [10de:0421] (rev a1)
03:00.0 SATA controller [0106]: JMicron Technologies, Inc. JMicron 20360/20363 AHCI Controller [197b:2363] (rev 02)
03:00.1 IDE interface [0101]: JMicron Technologies, Inc. JMicron 20360/20363 AHCI Controller [197b:2363] (rev 02)
04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 01)
05:01.0 Network controller [0280]: Atheros Communications Inc. AR5416 802.11abgn Wireless PCI Adapter [168c:0023] (rev 01)
05:06.0 FireWire (IEEE 1394) [0c00]: Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) [104c:8024]

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Ok here it is:

00:00.0 Host bridge [0600]: Intel Corporation Device [8086:2e20] (rev 02)
00:01.0 PCI bridge [0604]: Intel Corporation Device [8086:2e21] (rev 02)
00:1a.0 USB Controller [0c03]: Intel Corporation Device [8086:3a37]
00:1a.1 USB Controller [0c03]: Intel Corporation Device [8086:3a38]
00:1a.2 USB Controller [0c03]: Intel Corporation Device [8086:3a39]
00:1a.7 USB Controller [0c03]: Intel Corporation Device [8086:3a3c]
00:1b.0 Audio device [0403]: Intel Corporation Device [8086:3a3e]
00:1c.0 PCI bridge [0604]: Intel Corporation Device [8086:3a40]
00:1d.0 USB Controller [0c03]: Intel Corporation Device [8086:3a34]
00:1d.1 USB Controller [0c03]: Intel Corporation Device [8086:3a35]
00:1d.2 USB Controller [0c03]: Intel Corporation Device [8086:3a36]
00:1d.7 USB Controller [0c03]: Intel Corporation Device [8086:3a3a]
00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev 90)
00:1f.0 ISA bridge [0601]: Intel Corporation Device [8086:3a18]
00:1f.2 SATA controller [0106]: Intel Corporation Device [8086:3a22]
00:1f.3 SMBus [0c05]: Intel Corporation Device [8086:3a30]
01:00.0 VGA compatible controller [0300]: nVidia Corporation G70 [GeForce 7600 GT] [10de:0391] (rev a1)
03:01.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10)
03:07.0 FireWire (IEEE 1394) [0c00]: Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) [104c:8024]

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Ok here it is:

00:00.0 Host bridge [0600]: Intel Corporation Device [8086:2e20] (rev 02)
00:01.0 PCI bridge [0604]: Intel Corporation Device [8086:2e21] (rev 02)
00:1a.0 USB Controller [0c03]: Intel Corporation Device [8086:3a37]
00:1a.1 USB Controller [0c03]: Intel Corporation Device [8086:3a38]
00:1a.2 USB Controller [0c03]: Intel Corporation Device [8086:3a39]
00:1a.7 USB Controller [0c03]: Intel Corporation Device [8086:3a3c]
00:1b.0 Audio device [0403]: Intel Corporation Device [8086:3a3e]
00:1c.0 PCI bridge [0604]: Intel Corporation Device [8086:3a40]
00:1d.0 USB Controller [0c03]: Intel Corporation Device [8086:3a34]
00:1d.1 USB Controller [0c03]: Intel Corporation Device [8086:3a35]
00:1d.2 USB Controller [0c03]: Intel Corporation Device [8086:3a36]
00:1d.7 USB Controller [0c03]: Intel Corporation Device [8086:3a3a]
00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev 90)
00:1f.0 ISA bridge [0601]: Intel Corporation Device [8086:3a18]
00:1f.2 SATA controller [0106]: Intel Corporation Device [8086:3a22]
00:1f.3 SMBus [0c05]: Intel Corporation Device [8086:3a30]
01:00.0 VGA compatible controller [0300]: nVidia Corporation G70 [GeForce 7600 GT] [10de:0391] (rev a1)
03:01.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10)
03:07.0 FireWire (IEEE 1394) [0c00]: Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) [104c:8024]

 

OK you need to reoutput your DSDT file. That thing had a bunch of errors in it. I don't know how you output it but I would go back and redo it.

 

Most importantly you need to add this after the _WAK method:

   Method (DTGP, 5, NotSerialized)
   {
       If (LEqual (Arg0, Buffer (0x10)
               {
                   /* 0000 */    0xC6, 0xB7, 0xB5, 0xA0, 0x18, 0x13, 0x1C, 0x44, 
                   /* 0008 */    0xB0, 0xC9, 0xFE, 0x69, 0x5E, 0xAF, 0x94, 0x9B
               }))
       {
           If (LEqual (Arg1, One))
           {
               If (LEqual (Arg2, Zero))
               {
                   Store (Buffer (One)
                       {
                           0x03
                       }, Arg4)
                   Return (One)
               }

               If (LEqual (Arg2, One))
               {
                   Return (One)
               }
           }
       }

       Store (Buffer (One)
           {
               0x00
           }, Arg4)
       Return (One)
   }

 

This will replace your USB Device section.

           Device (USB0)
           {
               Name (_ADR, 0x001D0000)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x34, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x03, 
                   0x03
               })
           }

           Device (USB1)
           {
               Name (_ADR, 0x001D0001)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x35, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x04, 
                   0x03
               })
           }

           Device (USB2)
           {
               Name (_ADR, 0x001D0002)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x36, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x0C, 
                   0x03
               })
           }

           Device (US31)
           {
               Name (_ADR, 0x001A0003)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

               Name (_PRW, Package (0x02)
               {
                   0x0E, 
                   0x03
               })
           }

           Device (USB3)
           {
               Name (_ADR, 0x001A0000)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x37, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x0E, 
                   0x03
               })
           }

           Device (USB4)
           {
               Name (_ADR, 0x001A0001)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x38, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x05, 
                   0x03
               })
           }

           Device (USB5)
           {
               Name (_ADR, 0x001A0002)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x39, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x20, 
                   0x03
               })
           }

           Device (USBE)
           {
               Name (_ADR, 0x001D0007)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x3A, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x0D, 
                   0x03
               })
           }

           Device (USE2)
           {
               Name (_ADR, 0x001A0007)
               Method (_S3D, 0, NotSerialized)
               {
                   If (LEqual (OSFL, 0x02))
                   {
                       Return (0x02)
                   }

                   Return (0x03)
               }

              Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x3C, 0x3A, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

               Name (_PRW, Package (0x02)
               {
                   0x0D, 
                   0x03
               })
           }

 

From the looks of the DSDT file you posted you have a long way to go. The file format you should have posted would have ended in .DSL The above patch will most likely fix your problem.

 

You're right - I thought you'd already tried the DSDT patch apex?

Give it a go the method is well outlined at by zhell at the start of this thread.

D

 

FormerlyKnownAs have you opened a Speedstepping thread? This one has veered off topic. If not I'll start one.

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I'll take a peek at this later tonight.

 

 

 

@ FormerlyKnownAs

Is 2.66GHz the lowest the Q9450 can go? Basically supporting only three P-States?

 

Hi

 

Firstly changing the power value has no noticeable effect on CPU temp.

I dropped it by 5000mW then 10000mW for each step and there was no change.

 

We only have x6 x7 x8. I don't know if you can add fractions of multi's (6.5, 7.5) I haven't tried it but x6 is a low as it goes.

This gives me 2.33GHz (75%).

 

Please feel free to start a speedstep thread I'm happy to contribute - it's 90 degrees in my garden and I'm going to spend the day in the sun :thumbsup_anim:

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HI

 

Thanks for this method :)

 

i got sleep work in Snow leopard With my board P5E

 

but after wake up only the keyboard not work i need to re plug it

 

restart doesn't work after a sleep

 

my kext in Extra : dsmos.kext / openhaltrestart.kext / IOAHCIblockstorageinjector.kext / AD1988b.fix.kext

 

someone know how to fix this ?

 

her is my dsdt

dsdt.dsl.zip

post-189308-1250706868_thumb.png

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Sorry for the flood!

 

another slightly blond moment :P i dint' use DropSSDT=y when I took dmesg dump with voodoo.

 

Hi

i want to add my P-States into my dsdt.dsl , not in an extra ssdt-x. aml.

The changes(adds) in the DSDT cpu part are no problem, but i have a few questions around adding P-State tables in the CPU part of dsdt.dsl.

 

I use PC EFI bootloader 10.1 (or 10.2) for my 10.5.8 and also SL partitions.

Do i need that DropSSDT=yes option if i have pstates included in my dsdt.aml or is that only needed for users which have an extra ssdt-x.aml ?

I needed, does PC EFI 10.1 boot (rest is chameleon 2 RC1) support DropSSDT=yes ?

 

I can use IORegistry explorer and see in ACPI my DSDT/SSDT Entries (in HEX) ans all others.

Where can i check in the IORegistry explorer if the changed part of dsdt.aml (the added Pstates) is used ?

I have extracted my SSDT-0 (i only have one ).

Do i need some information out of there and add it toor my P-States adding in dsdt.dsl ?

Here the adding in general (not my needed psstates, i have my own values already):

 

Scope (\_PR)
{
   Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {

       Name (_PPC, 0x00)

       Name (_PCT, Package (0x02)
       {
           ResourceTemplate ()
           {
               Register (FFixedHW, // PERF_CTL
                   0x10,              // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000199, // Address
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (FFixedHW, // PERF_STATUS
                   0x10,               // Bit Width
                   0x00,    // Bit Offset
                   0x0000000000000198, // Address
                   ,)
           }
       })

       Name ([b]_PSS[/b], Package (0x03)
       {
           Package (0x06)// [b]P-State 0[/b]
           {
               3104, // f in MHz
               75000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x00000820, // value written to PERF_CTL; fid=8, vid=32
               0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
           }, 

           Package (0x06)// [b]P-State 1[/b]
           {
               2716, // f in MHz
               65000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x0000071C, // value written to PERF_CTL; fid=7, vid=28
               0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
           }, 

           Package (0x06)// P-State 2
           {
               2328, // f in MHz
               60000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x0000061A, // value written to PERF_CTL; fid=6, vid=26
               0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
           }, 
       })
   }

   Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06) {

       Name (_PPC, 0x00)

       Name (_PCT, Package (0x02)
       {
           ResourceTemplate ()
           {
               Register (FFixedHW, // PERF_CTL
                   0x10,              // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000199, // Address
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (FFixedHW, // PERF_STATUS
                   0x10,               // Bit Width
                   0x00,    // Bit Offset
                   0x0000000000000198, // Address
                   ,)
           }
       })

       Name (_PSS, Package (0x03)
       {
           Package (0x06)// P-State 0
           {
               3104, // f in MHz
               75000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x00000820, // value written to PERF_CTL; fid=8, vid=32
               0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
           }, 

           Package (0x06)// P-State 1
           {
               2716, // f in MHz
               65000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x0000071C, // value written to PERF_CTL; fid=7, vid=28
               0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
           }, 

           Package (0x06)// P-State 2
           {
               2328, // f in MHz
               60000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x0000061A, // value written to PERF_CTL; fid=6, vid=26
               0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
           }, 
       })
   }


   Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06) {

       Name (_PPC, 0x00)

       Name (_PCT, Package (0x02)
       {
           ResourceTemplate ()
           {
               Register (FFixedHW, // PERF_CTL
                   0x10,              // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000199, // Address
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (FFixedHW, // PERF_STATUS
                   0x10,               // Bit Width
                   0x00,    // Bit Offset
                   0x0000000000000198, // Address
                   ,)
           }
       })

       Name (_PSS, Package (0x03)
       {
           Package (0x06)// P-State 0
           {
               3104, // f in MHz
               75000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x00000820, // value written to PERF_CTL; fid=8, vid=32
               0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
           }, 

           Package (0x06)// P-State 1
           {
               2716, // f in MHz
               65000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x0000071C, // value written to PERF_CTL; fid=7, vid=28
               0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
           }, 

           Package (0x06)// P-State 2
           {
               2328, // f in MHz
               60000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x0000061A, // value written to PERF_CTL; fid=6, vid=26
               0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
           }, 
       })
   }
..... same for all other CPUx 

 

There are no _PSS entries in my ssdt-0, because my BIOS (GA-EP35-DS3) hasnt them included , thats the reason i will add them.

 

Thanks

 

For users who want to help i attached my extracted ssdt-0 (only one ssdt in my bios!).

SSDT_0.dsl.zip

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@ kdawg

 

@ formerlyknownas

 

Regarding the problem of EHCI Ports not sleeping: I managed to make a DSDT Patch which allows EHCI Ports to sleep properly! http://www.insanelymac.com/forum/index.php...t&p=1240686

 

 

YOU ROCK!!!! Was it just trial and error? I feel like I should pay you money or something. :(

 

Anyway I tried it out and it works on my GA-EP45-UD3P. No need for Slice's kext! Thanks ApedDE.

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My code looks different where do I put the device id etc?

 

 

 

 

 Device (USB0)
		 {
			 Name (_ADR, 0x001D0000)
			 Method (_S3D, 0, NotSerialized)

			 {
				 If (LEqual (OSFL, 0x02))
				 {
					 Return (0x02)
				 }

				 Return (0x03)
			 }

			 Name (_PRW, Package (0x02)
			 {
				 0x03, 
				 One
			 })
		 }

 

 

 

Problem solved!

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Is there a SSDT Thread already? I couldn't find one. I would like to dip a bit deeper into this, as i need to run AppleIntelCPUPowermanagement.kext for proper Sleep (SleepEnabler doesn't work good for me cause my DVD Drive {censored} around)

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Is there a SSDT Thread already? I couldn't find one. I would like to dip a bit deeper into this, as i need to run AppleIntelCPUPowermanagement.kext for proper Sleep (SleepEnabler doesn't work good for me cause my DVD Drive {censored} around)

 

I tried starting one in the xLabs but there aren't a lot of DSDT'ers there. Mostly speedstepping via kexts/kernels.

 

Try these:

http://www.insanelymac.com/forum/index.php?showforum=163

http://www.insanelymac.com/forum/index.php?showtopic=145792

 

Good references:

http://s2.enemy.org/~zaunmayc/speedstep8.04.html

http://www.ztex.de/misc/c2ctl.e.html#c1

 

FormerlyKnownAs and I have spent a lot of time trying to achieve this via DSDT. SpeedStepping is doable but c-states are another thing.

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@ kdawg

 

Thanks for the heads-up ;) I would be rather more interested in working C-States, as they are much more powersaving than Speedstepping IMHO. No one managed to get C-State-Control working?

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@ kdawg

 

Thanks for the heads-up -_- I would be rather more interested in working C-States, as they are much more powersaving than Speedstepping IMHO. No one managed to get C-State-Control working?

 

 

Not via DSTD alone. I have a Dell Mini 9 I was working on and I have to use VoodooPower. FKA and I are unable to retrieve working c-states from our boards, believing they don't exist. I'm sure it's possible we just haven't figured it out yet.

 

Mine and FKA DSDTs are in this thread somewhere. Take a peek to see where we ended up.

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