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About vasir15

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    InsanelyMac Protégé
  • Birthday 10/19/1970

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    anything and everything
  1. DSMOS has arrived help

    I had the exact same issues but after replacing the CPU to an i5 the issues ran away.
  2. Hello All, I have a TS140 and replaced the Xeon CPU with an i5-4430 mainly because I wanted to enable the DP on 2 ports and use the HD4600 iGP. I also did the hack to use Apple BT adapter which works well. All works well and I was able to get the right SSDT but I can't wake the machine from sleep via USB but works well with PB. I get this error when waking in dmesg: The USB device WirelessControllerDevice (Port 5 of Hub at 0x14000000) may have caused a wake by issuing a remote wakeup (2) USBF: 203.583 AppleUSBEHCI::CheckSleepCapability - controller will be unloaded across sleep **** [iOBluetoothHostControllerUSBTransport][sendHCIRequest] -- on suspended device! Data begins with: 0x010C08FF -- 0x2000 **** [iOBluetoothHCIController][EnqueueRequestForController] -- SendHCIRequestToTransport failed, error (0xE00002D8) -- kIOReturnNotReady [sendHCIRequestFormatted] ### ERROR: EnqueueRequestForController failed (err=0xe00002d8 (kIOReturnNotReady)) for opCode 0x0c01 (Set Event Mask) **** [iOBluetoothHostControllerUSBTransport][suspendDevice] -- Resume -- suspendDeviceCallResult = 0x0000 (kIOReturnSuccess) -- 0x2000 **** Looks like the BT adapter does issue a wake but system is still under and waiting for PB. I have used the DTGP and EHCI patch and compiled using MaciASL but no change. Included is my .aml for TS140 and I was wondering if the gurus here can look inside and tell me what I am missing. Thanks for your time. DSDT.aml.tar
  3. Hi, Anyone got the // { 0x8086041a, "HD Graphics P4600/P4700" }, // Haswell Integrated Graphics Controller working?
  4. Hello Guys, I just got a TS140 server (haswell) box and used [url="http://www.insanelymac.com/forum/topic/279450-why-insanelymac-does-not-support-tonymacx86/"]#####[/url] to create the usb stick and install. Patched the kernel for haswell reboot issue. Problem is that the box never enters S3/S4 and I also get unknown CPU 0c3 error. Included is my ubuntu extracted DSDT and was wondering if you guys can help me to get the .aml patched so the unit can enter S4. Thanks,
  5. You have swap on? I have 12 gigs memory and disabled it and runs pretty good. ( there are pro's and cons to swap disable but for wife's system works well since she does not use it for anything hard)
  6. Graphic not working (intel HD4000)

    As artur suggested try all the stings, for me the 6th one finally worked ... I know it is a pain but he has a sound suggestion for you. I actually created 9 different boot.plist's ...and this one worked for me with 786 meg on 10.8.4 7f0000000100000001000000730000000200000002010c00d041030a000000000101060000027fff04002c0000004100410050004c002c00690067002d0070006c006100740066006f0072006d002d006900640000000800000001006601140000006800640061002d0067006600780000000d0000006f6e626f6172642d31 good luck.
  7. Look at the SMBus error msg
  8. Haswell is HERE now!

    As I suspected new 2013 MBA is using Haswell LP , step 12. http://www.ifixit.com/Teardown/MacBook+Air+13-Inch+Mid+2013+Teardown/15042/1?singlePage
  9. Apple unveils OS X 10.9 "Mavericks"

    Interesting how it will work on new sleep states on 10.9, please keep us posted.
  10. Haswell is HERE now!

    The die shrinking plan is always an ongoing process and not specific to cougar point. Z68 is basically the same as P67 but fused differently for adding small enhancements that I am not going to explain here. You are just repeating what I stated before that Cougarpoint, Pantherpoint and Lynxpoint are basically enhanced ICH with additional design boxes moved from NB to PCH and yes "one" package. That statement is confusing because in 1990's we had no such thing as a true SOC please explain. The "design" technology to have a true SOC has been around since stone age and the only limiting factor was to FAB the design for the right failure rate and right price. True SOC will minimize power consumption, minimize design rules and need less parts which is music to toy makers around the world.
  11. Haswell is HERE now!

    Again you are wrong here Rampage: Intel's first implementation of MC to CPU was a side project before Yonah ( cant remember the name now but starts with a "D") which was shut down and Merom was born. Most area in NB was used for MC and that was moved to CPU and now called SA + few other minor designs. The bulky analogue design was moved to PCH ( glorified ICH) + what ever ICH had before. So instead of a 3 chip solution now you have 2 including HASWL BUT HASWL has now integrated voltage regulators to reduce MB makers BOM. HASWL has 2 different designs, 1) HASWL + Lynx point PCH => notice 2 packages 2) HASWL + Lynx point LP => 2 Si parts on 1 package making it smaller and cheaper to design and manufacture but harder to validate. Option 2 will be used for LP mobile devices and option 1 will be used for traditional computer designs Traditionally Intel does this so called iteration or evolution to fine-tune its manufacturing techniques and eventually will move everything into 1 Si package but for now the FR is too high and that has to wait a bit, I don't think even SL will be 1 Si design. I hope this helps you to understand. Yes they called it PCH now, as I mentioned before it is basically a glorified ICH and marketing name to show a "new" design but when it boils down to it still an ICH concept and nothing new here. Look at it as a pumped up ICH with DMI and FDI and few other things. Really if you look at it nothing revolutionary but evolutionary to reduce cost with least design change and most ICH designs still in PCH. Now when all things move together into one design that is when things really change but that also means reduced user visibility and almost no customization and OC ability which I don't like. Hope this helps.
  12. 10.8.4 Betas Builds

    love the chase
  13. 10.8.4 Betas Builds

    Come on Freeman don't tell me you were not worried about KP on first boot
  14. Haswell is HERE now!

    Z68 was not on the same package with SNB, I think you are confusing a few things there. Z68 had some enhancements and OC ability. You are incorrect when it comes to this discussion since LynxPoint LP has not been released yet. HSWL and Lynxpoint LP are 2 different die's on the on package and are targeted for LP and tablet devices. But for mainstream there are still the southbridge/ a.k.a PCH to CPU design. I don't think that the current motherboards have C2 LP yet, maybe a bit later. For Lynxpoint LP that is a different issue.