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  1. 1 point
    MorenoAv

    [Pre-Release] macOS Catalina 10.15.4

    Update made... all is well...
  2. 1 point
    This requires you to modify the C code yourself, then compile it, and the icon has to be found or drawn by yourself!
  3. 1 point
    Every Revision of EFI, dsdt and anything else I’ve ever released is on page one buddy
  4. 1 point
    While reading your reply I realised the same question was already asked by me some time ago. While searching on the net for a solution I found information about the app SwitchResX, tried it and could indeed disable the TV but even after a reboot the system could somehow see it. The memory clock of the RX kept turning @ 2Ghz. TV is disconnected at the moment and will keep it that way while looking for other possibilities to let the misses watch her series while I use the computer.
  5. 1 point
    Hi Follow what @AudioGod says. It's a good solution. One stupid question: I've a MSI Radeon RX580. No IGPU needed, this card supports 4 HDMI ports, so I could use one for monitor and for TV if I want it. Display TV can be disable in macOS.
  6. 1 point
    Yes sure no problem give me 30mins as I’m just eating my dinner bud side note - if you disable igpu and change shiki too 144 in the boot arguments it’s the same thing but your still running under the correct smbios 19,1 if you do that instead then let me know how it goes for you?
  7. 1 point
    The EFI released works perfectly provided you set up your system as he suggested. Get a proper macOS installer without errors. This is crucial as people use all sorts of dumb ways to make the stick, either pulling an incompatible version or an assortment of errors that either fubar the install process or leave you with a non-working system. Stop and take a step back. Make a USB installer on a real macOS running the latest OS. Ensure it's good and error free. Update your BIOS to the latest revision (F12d for the Pro and F12c for the Pro WIFI, both work with this EFI). Set up the BIOS properly. You need to first enable the dGPU, save settings and reboot, then go right back into the BIOS and finish setting it up. Only then will it list the following settings: • Settings -> IO Ports -> DVMT Pre-Allocated -> 64M • Settings -> IO Ports -> DVMT Total GFX0-Allocated -> 256M • Settings -> IO Ports -> Aperture Size -> 256MB That's mostly it. Unplug all your hardware that's not necessary. If you have some kind of radiator cooling system, then you may need to do some fiddling as there are known issues with lots of fancy cooling (by fancy I mean coming from traditional air cooling like the Notcua DH-14). macOS doesn't support anything other than traditional air cooling systems (fan + heatsink). You're throwing up a ton of info, way too much. I get what you're trying to do, but this EFI is bulletproof. You just toss in your EFI partition and you're good. Truly.
  8. 1 point
    The AirPortAtheros40.kext as similiar code found on linux freebsd. This first patch was tested on OS X 10.11.0 Working card: Qualcomm Atheros AR9565 pci168c,36 with bluetooth Download v01 for 0036 card + BTFirmwareUploader in attachments. Post your questions here You can find updates on EMlyDinEsH BTFirmwareUploader here http://forum.osxlatitude.com/index.php?/topic/2925-bluetooth-firmware-uploader/ v01 also works on 10.11.4 TOFIX: Bands/Channels limitation exist in macosx/windows driver but not in linux UPDATE: v03 fixed eprom local check. This kext check the following mac models. This might disable/enable some features. plz check your smbios mac model. I'm not using any of this models in my smbios v21 = 31; if ( PEGetModelName(&v40, 32LL) ) { v22 = !strcmp(&v40, "iMac10,1") || !strcmp(&v40, "iMac11,1") || !strcmp(&v40, "iMac11,2") || !strcmp(&v40, "MacBookPro5,2"); if ( !strcmp(&v40, "iMac12,1") || !strcmp(&v40, "iMac12,2") ) v21 = 29; } else { v22 = 0; } DEV NOTES: The driver attach procedure loads one of 2 main subs: ar5416Attach(); ar9300Attach(); On the 9300 tree we have native support for #define AR_SREV_VERSION_OSPREY 0x1C0 #define AR_SREV_VERSION_AR9580 0x1C0 #define AR_SREV_VERSION_HORNET 0x200 The 0036 card is set here #define AR_SREV_VERSION_APHRODITE 0x2C0 For other cards check here ath_hal_mac_name(struct ath_hal *ah) 90 { 91 switch (ah->ah_macVersion) { 92 case AR_SREV_VERSION_CRETE: 93 case AR_SREV_VERSION_MAUI_1: 94 return "AR5210"; 95 case AR_SREV_VERSION_MAUI_2: 96 case AR_SREV_VERSION_OAHU: 97 return "AR5211"; 98 case AR_SREV_VERSION_VENICE: 99 return "AR5212"; 100 case AR_SREV_VERSION_GRIFFIN: 101 return "AR2413"; 102 case AR_SREV_VERSION_CONDOR: 103 return "AR5424"; 104 case AR_SREV_VERSION_EAGLE: 105 return "AR5413"; 106 case AR_SREV_VERSION_COBRA: 107 return "AR2415"; 108 case AR_SREV_2425: /* Swan */ 109 return "AR2425"; 110 case AR_SREV_2417: /* Nala */ 111 return "AR2417"; 112 case AR_XSREV_VERSION_OWL_PCI: 113 return "AR5416"; 114 case AR_XSREV_VERSION_OWL_PCIE: 115 return "AR5418"; 116 case AR_XSREV_VERSION_HOWL: 117 return "AR9130"; 118 case AR_XSREV_VERSION_SOWL: 119 return "AR9160"; 120 case AR_XSREV_VERSION_MERLIN: 121 if (AH_PRIVATE(ah)->ah_ispcie) 122 return "AR9280"; 123 return "AR9220"; 124 case AR_XSREV_VERSION_KITE: 125 return "AR9285"; 126 case AR_XSREV_VERSION_KIWI: 127 if (AH_PRIVATE(ah)->ah_ispcie) 128 return "AR9287"; 129 return "AR9227"; 130 case AR_SREV_VERSION_AR9380: 131 if (ah->ah_macRev >= AR_SREV_REVISION_AR9580_10) 132 return "AR9580"; 133 return "AR9380"; 134 case AR_SREV_VERSION_AR9460: 135 return "AR9460"; 136 case AR_SREV_VERSION_AR9330: 137 return "AR9330"; 138 case AR_SREV_VERSION_AR9340: 139 return "AR9340"; 140 case AR_SREV_VERSION_QCA9550: 141 return "QCA9550"; 142 case AR_SREV_VERSION_AR9485: 143 return "AR9485"; 144 case AR_SREV_VERSION_QCA9565: 145 return "QCA9565"; 146 case AR_SREV_VERSION_QCA9530: 147 return "QCA9530"; 148 } 149 return "????"; 150 } A reference to freebsd source code (usefull to in code research for other cards): http://code.metager.de/source/xref/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ And ofc the linux id search engine: http://lxr.free-electrons.com/ident apple code is very old but still some patches can be done Todo: Test domains references: static REG_DMN_PAIR_MAPPING regDomainPairs[] = { 32 {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 33 {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 34 {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 35 {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 36 37 {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 38 {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 39 {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 40 {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 41 {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 42 {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 43 {FCC5_FCCB, FCC5, FCCB, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 44 45 {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 46 {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 47 {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 48 {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 49 {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 50 {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 51 52 {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 53 {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 54 55 {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 56 {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 57 {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 58 {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 59 {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 60 {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 61 {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 62 {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 63 {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 64 {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 65 66 {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 67 {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 68 {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 69 {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 70 71 {MKK1_MKKA, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN }, 72 {MKK1_MKKB, MKK1, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 }, 73 {MKK1_FCCA, MKK1, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 }, 74 {MKK1_MKKA1, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 }, 75 {MKK1_MKKA2, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 }, 76 {MKK1_MKKC, MKK1, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 }, 77 78 /* MKK2 */ 79 {MKK2_MKKA, MKK2, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 }, 80 81 /* MKK3 */ 82 {MKK3_MKKA, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC , PSCAN_MKKA, CTRY_DEFAULT }, 83 {MKK3_MKKB, MKK3, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 }, 84 {MKK3_MKKA1, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_DEFAULT }, 85 {MKK3_MKKA2,MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 }, 86 {MKK3_MKKC, MKK3, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 }, 87 {MKK3_FCCA, MKK3, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_DEFAULT }, 88 89 /* MKK4 */ 90 {MKK4_MKKB, MKK4, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 }, 91 {MKK4_MKKA1, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_DEFAULT }, 92 {MKK4_MKKA2, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 }, 93 {MKK4_MKKC, MKK4, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 }, 94 {MKK4_FCCA, MKK4, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_DEFAULT }, 95 96 /* MKK5 */ 97 {MKK5_MKKB, MKK5, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 }, 98 {MKK5_MKKA2,MKK5, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 }, 99 {MKK5_MKKC, MKK5, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 }, 100 101 /* MKK6 */ 102 {MKK6_MKKB, MKK6, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 }, 103 {MKK6_MKKA2, MKK6, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 }, 104 {MKK6_MKKC, MKK6, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 }, 105 106 /* MKK7 */ 107 {MKK7_MKKB, MKK7, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 }, 108 {MKK7_MKKA2, MKK7, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 }, 109 {MKK7_MKKC, MKK7, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 }, 110 111 /* MKK8 */ 112 {MKK8_MKKB, MKK8, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 }, 113 {MKK8_MKKA2,MKK8, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 }, 114 {MKK8_MKKC, MKK8, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 }, 115 116 {MKK9_MKKA, MKK9, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_DEFAULT }, 117 {MKK10_MKKA, MKK10, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_DEFAULT }, 118 119 /* These are super domains */ 120 {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 121 {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 122 {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 123 {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 124 {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 125 {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 126 {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 127 {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 128 {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 129 {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 130 {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 131 {WORB_WORLD, WORB_WORLD, WORB_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 132 {WORC_WORLD, WORC_WORLD, WORC_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 133}; and the ids: enum { 31 /* 32 * The following regulatory domain definitions are 33 * found in the EEPROM. Each regulatory domain 34 * can operate in either a 5GHz or 2.4GHz wireless mode or 35 * both 5GHz and 2.4GHz wireless modes. 36 * In general, the value holds no special 37 * meaning and is used to decode into either specific 38 * 2.4GHz or 5GHz wireless mode for that particular 39 * regulatory domain. 40 */ 41 NO_ENUMRD = 0x00, 42 NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ 43 NULL1_ETSIB = 0x07, /* Israel */ 44 NULL1_ETSIC = 0x08, 45 FCC1_FCCA = 0x10, /* USA */ 46 FCC1_WORLD = 0x11, /* Hong Kong */ 47 FCC4_FCCA = 0x12, /* USA - Public Safety */ 48 FCC5_FCCB = 0x13, /* USA w/ 1/2 and 1/4 width channels */ 49 FCC6_FCCA = 0x14, /* Canada for AP only */ 50 51 FCC2_FCCA = 0x20, /* Canada */ 52 FCC2_WORLD = 0x21, /* Australia & HK */ 53 FCC2_ETSIC = 0x22, 54 FCC_UBNT = 0x2A, /* Ubiquity PicoStation M2HP */ 55 FRANCE_RES = 0x31, /* Legacy France for OEM */ 56 FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ 57 FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ 58 59 ETSI1_WORLD = 0x37, 60 ETSI3_ETSIA = 0x32, /* France (optional) */ 61 ETSI2_WORLD = 0x35, /* Hungary & others */ 62 ETSI3_WORLD = 0x36, /* France & others */ 63 ETSI4_WORLD = 0x30, 64 ETSI4_ETSIC = 0x38, 65 ETSI5_WORLD = 0x39, 66 ETSI6_WORLD = 0x34, /* Bulgaria */ 67 ETSI8_WORLD = 0x3D, /* Russia */ 68 ETSI9_WORLD = 0x3E, /* Ukraine */ 69 ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ 70 71 MKK1_MKKA = 0x40, /* Japan (JP1) */ 72 MKK1_MKKB = 0x41, /* Japan (JP0) */ 73 APL4_WORLD = 0x42, /* Singapore */ 74 MKK2_MKKA = 0x43, /* Japan with 4.9G channels */ 75 APL_RESERVED = 0x44, /* Reserved (Do not used) */ 76 APL2_WORLD = 0x45, /* Korea */ 77 APL2_APLC = 0x46, 78 APL3_WORLD = 0x47, 79 MKK1_FCCA = 0x48, /* Japan (JP1-1) */ 80 APL2_APLD = 0x49, /* Korea with 2.3G channels */ 81 MKK1_MKKA1 = 0x4A, /* Japan (JE1) */ 82 MKK1_MKKA2 = 0x4B, /* Japan (JE2) */ 83 MKK1_MKKC = 0x4C, /* Japan (MKK1_MKKA,except Ch14) */ 84 APL2_FCCA = 0x4D, /* Mobile customer */ 85 86 APL3_FCCA = 0x50, 87 APL1_WORLD = 0x52, /* Latin America */ 88 APL1_FCCA = 0x53, 89 APL1_APLA = 0x54, 90 APL1_ETSIC = 0x55, 91 APL2_ETSIC = 0x56, /* Venezuela */ 92 APL5_WORLD = 0x58, /* Chile */ 93 APL6_WORLD = 0x5B, /* Singapore */ 94 APL7_FCCA = 0x5C, /* Taiwan 5.47 Band */ 95 APL8_WORLD = 0x5D, /* Malaysia 5GHz */ 96 APL9_WORLD = 0x5E, /* Korea 5GHz; before 11/2007; now APs only */ 97 APL10_WORLD = 0x5F, /* Korea 5GHz; After 11/2007; STAs only */ 98 99 /* 100 * World mode SKUs 101 */ 102 WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ 103 WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ 104 WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ 105 WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ 106 WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ 107 WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ 108 109 WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ 110 WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ 111 EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ 112 113 WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ 114 WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ 115 WORB_WORLD = 0x6B, /* WorldB (WOB SKU) */ 116 WORC_WORLD = 0x6C, /* WorldC (WOC SKU) */ 117 118 MKK3_MKKB = 0x80, /* Japan UNI-1 even + MKKB */ 119 MKK3_MKKA2 = 0x81, /* Japan UNI-1 even + MKKA2 */ 120 MKK3_MKKC = 0x82, /* Japan UNI-1 even + MKKC */ 121 122 MKK4_MKKB = 0x83, /* Japan UNI-1 even + UNI-2 + MKKB */ 123 MKK4_MKKA2 = 0x84, /* Japan UNI-1 even + UNI-2 + MKKA2 */ 124 MKK4_MKKC = 0x85, /* Japan UNI-1 even + UNI-2 + MKKC */ 125 126 MKK5_MKKB = 0x86, /* Japan UNI-1 even + UNI-2 + mid-band + MKKB */ 127 MKK5_MKKA2 = 0x87, /* Japan UNI-1 even + UNI-2 + mid-band + MKKA2 */ 128 MKK5_MKKC = 0x88, /* Japan UNI-1 even + UNI-2 + mid-band + MKKC */ 129 130 MKK6_MKKB = 0x89, /* Japan UNI-1 even + UNI-1 odd MKKB */ 131 MKK6_MKKA2 = 0x8A, /* Japan UNI-1 even + UNI-1 odd + MKKA2 */ 132 MKK6_MKKC = 0x8B, /* Japan UNI-1 even + UNI-1 odd + MKKC */ 133 134 MKK7_MKKB = 0x8C, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKB */ 135 MKK7_MKKA2 = 0x8D, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA2 */ 136 MKK7_MKKC = 0x8E, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKC */ 137 138 MKK8_MKKB = 0x8F, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKB */ 139 MKK8_MKKA2 = 0x90, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKA2 */ 140 MKK8_MKKC = 0x91, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKC */ 141 142 MKK14_MKKA1 = 0x92, /* Japan UNI-1 even + UNI-1 odd + 4.9GHz + MKKA1 */ 143 MKK15_MKKA1 = 0x93, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + 4.9GHz + MKKA1 */ 144 145 MKK10_FCCA = 0xD0, /* Japan UNI-1 even + UNI-2 + 4.9GHz + FCCA */ 146 MKK10_MKKA1 = 0xD1, /* Japan UNI-1 even + UNI-2 + 4.9GHz + MKKA1 */ 147 MKK10_MKKC = 0xD2, /* Japan UNI-1 even + UNI-2 + 4.9GHz + MKKC */ 148 MKK10_MKKA2 = 0xD3, /* Japan UNI-1 even + UNI-2 + 4.9GHz + MKKA2 */ 149 150 MKK11_MKKA = 0xD4, /* Japan UNI-1 even + UNI-2 + mid-band + 4.9GHz + MKKA */ 151 MKK11_FCCA = 0xD5, /* Japan UNI-1 even + UNI-2 + mid-band + 4.9GHz + FCCA */ 152 MKK11_MKKA1 = 0xD6, /* Japan UNI-1 even + UNI-2 + mid-band + 4.9GHz + MKKA1 */ 153 MKK11_MKKC = 0xD7, /* Japan UNI-1 even + UNI-2 + mid-band + 4.9GHz + MKKC */ 154 MKK11_MKKA2 = 0xD8, /* Japan UNI-1 even + UNI-2 + mid-band + 4.9GHz + MKKA2 */ 155 156 MKK12_MKKA = 0xD9, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + 4.9GHz + MKKA */ 157 MKK12_FCCA = 0xDA, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + 4.9GHz + FCCA */ 158 MKK12_MKKA1 = 0xDB, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + 4.9GHz + MKKA1 */ 159 MKK12_MKKC = 0xDC, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + 4.9GHz + MKKC */ 160 MKK12_MKKA2 = 0xDD, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + 4.9GHz + MKKA2 */ 161 162 MKK13_MKKB = 0xDE, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKB + All passive + no adhoc */ 163 164 /* 165 * Following definitions are used only by s/w to map old 166 * Japan SKUs. 167 */ 168 MKK3_MKKA = 0xF0, /* Japan UNI-1 even + MKKA */ 169 MKK3_MKKA1 = 0xF1, /* Japan UNI-1 even + MKKA1 */ 170 MKK3_FCCA = 0xF2, /* Japan UNI-1 even + FCCA */ 171 MKK4_MKKA = 0xF3, /* Japan UNI-1 even + UNI-2 + MKKA */ 172 MKK4_MKKA1 = 0xF4, /* Japan UNI-1 even + UNI-2 + MKKA1 */ 173 MKK4_FCCA = 0xF5, /* Japan UNI-1 even + UNI-2 + FCCA */ 174 MKK9_MKKA = 0xF6, /* Japan UNI-1 even + 4.9GHz */ 175 MKK10_MKKA = 0xF7, /* Japan UNI-1 even + UNI-2 + 4.9GHz */ 176 MKK6_MKKA1 = 0xF8, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA1 */ 177 MKK6_FCCA = 0xF9, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + FCCA */ 178 MKK7_MKKA1 = 0xFA, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA1 */ 179 MKK7_FCCA = 0xFB, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + FCCA */ 180 MKK9_FCCA = 0xFC, /* Japan UNI-1 even + 4.9GHz + FCCA */ 181 MKK9_MKKA1 = 0xFD, /* Japan UNI-1 even + 4.9GHz + MKKA1 */ 182 MKK9_MKKC = 0xFE, /* Japan UNI-1 even + 4.9GHz + MKKC */ 183 MKK9_MKKA2 = 0xFF, /* Japan UNI-1 even + 4.9GHz + MKKA2 */ 184 185 /* 186 * Regulator domains ending in a number (e.g. APL1, 187 * MK1, ETSI4, etc) apply to 5GHz channel and power 188 * information. Regulator domains ending in a letter 189 * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and 190 * power information. 191 */ 192 APL1 = 0x0150, /* LAT & Asia */ 193 APL2 = 0x0250, /* LAT & Asia */ 194 APL3 = 0x0350, /* Taiwan */ 195 APL4 = 0x0450, /* Jordan */ 196 APL5 = 0x0550, /* Chile */ 197 APL6 = 0x0650, /* Singapore */ 198 APL7 = 0x0750, /* Taiwan, disable ch52 */ 199 APL8 = 0x0850, /* Malaysia */ 200 APL9 = 0x0950, /* Korea. Before 11/2007. Now used only by APs */ 201 APL10 = 0x1050, /* Korea. After 11/2007. For STAs only */ 202 203 ETSI1 = 0x0130, /* Europe & others */ 204 ETSI2 = 0x0230, /* Europe & others */ 205 ETSI3 = 0x0330, /* Europe & others */ 206 ETSI4 = 0x0430, /* Europe & others */ 207 ETSI5 = 0x0530, /* Europe & others */ 208 ETSI6 = 0x0630, /* Europe & others */ 209 ETSI8 = 0x0830, /* Russia */ 210 ETSI9 = 0x0930, /* Ukraine */ 211 ETSIA = 0x0A30, /* France */ 212 ETSIB = 0x0B30, /* Israel */ 213 ETSIC = 0x0C30, /* Latin America */ 214 215 FCC1 = 0x0110, /* US & others */ 216 FCC2 = 0x0120, /* Canada, Australia & New Zealand */ 217 FCC3 = 0x0160, /* US w/new middle band & DFS */ 218 FCC4 = 0x0165, /* US Public Safety */ 219 FCC5 = 0x0166, /* US w/ 1/2 and 1/4 width channels */ 220 FCC6 = 0x0610, /* Canada and Australia */ 221 FCCA = 0x0A10, 222 FCCB = 0x0A11, /* US w/ 1/2 and 1/4 width channels */ 223 224 APLD = 0x0D50, /* South Korea */ 225 226 MKK1 = 0x0140, /* Japan (UNI-1 odd)*/ 227 MKK2 = 0x0240, /* Japan (4.9 GHz + UNI-1 odd) */ 228 MKK3 = 0x0340, /* Japan (UNI-1 even) */ 229 MKK4 = 0x0440, /* Japan (UNI-1 even + UNI-2) */ 230 MKK5 = 0x0540, /* Japan (UNI-1 even + UNI-2 + mid-band) */ 231 MKK6 = 0x0640, /* Japan (UNI-1 odd + UNI-1 even) */ 232 MKK7 = 0x0740, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 */ 233 MKK8 = 0x0840, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 + mid-band) */ 234 MKK9 = 0x0940, /* Japan (UNI-1 even + 4.9 GHZ) */ 235 MKK10 = 0x0B40, /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */ 236 MKK11 = 0x1140, /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */ 237 MKK12 = 0x1240, /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */ 238 MKK13 = 0x0C40, /* Same as MKK8 but all passive and no adhoc 11a */ 239 MKK14 = 0x1440, /* Japan UNI-1 even + UNI-1 odd + 4.9GHz */ 240 MKK15 = 0x1540, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + 4.9GHz */ 241 242 MKKA = 0x0A40, /* Japan */ 243 MKKC = 0x0A50, 244 245 NULL1 = 0x0198, 246 WORLD = 0x0199, 247 DEBUG_REG_DMN = 0x01ff, 248}; This can be changed in (btw original code as a little hack from apple): ar9300FillCapabilityInfo() ... *(_WORD *)(a1 + 2326) = 141; KPCM Tool to install extensions Check here https://www.firewolf.science/2015/10/kcpm-utility-pro-v5-0-installing-kexts-repairing-permissions-rebuilding-caches-configuring-sip-and-more/ Kernel kext debug here http://www.insanelymac.com/forum/topic/312254-realtek-ethernet-panic-debug-driver-using-xcode-ui/ Atm AR9462 and 9565 were patched using this mehod. I'll stop on 10.11 for the 9565 card as i cant get a stable kernel to work on my amd machine. AR9485, pci168c,32 also working gj dev9565.zip 0036v03.zip
  9. 1 point
    The issue has been fixed. The board's ME firmware was corrupt. Modding the BIOS to fix ME in conjunction with directly flashing the non-corrupt firmware to the ME region using FTK did the trick. Note that Windows was used for the fix. What was the issue? macOS currently expects a functioning ME device (HECI/IMEI) for Intel graphics to fully load. Because the firmware was corrupt, the kexts only loaded halfway and kextd stalled. On Windows, the ME device was "disconnected" in Device Manager. This is why even with IMEI in the IOReg, correct Clover settings and FramebufferAzul and HD5000Graphics kexts loaded in kextstat I could not get QE/CI, or even a proper graphics output. Once the firmware was restored, the ME coprocessor booted completely and the hack gets full acceleration now. For future note: should this method fail, the only option is to buy a new preflashed BIOS chip. Proceed with care. after.BMP before.BMP
  10. 1 point
    Hervé

    OSsxAptioFix3Drv Error on first start

    To enable trim on your SSD, you may use the following Terminal command: sudo trimforce enable You may plug your Windows-SSD to your Hackintosh, it won't cause any damage. You'd only use the trim command on it if you made it part of your macOS installation and intended to write data on it, for instance through a new macOS partition on it. If it entirely destined to Windows, you'll only read it from macOS, so no need for trimming. Contrary to (erroneous) popular belief, running OS X/macOS on a Hackintosh does not burn hardware, you can sleep safe and sound and reassure your neighbours, friends and family!
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