Slice i got RadeonPCI.kext and Radeon Dump.
Here is the dump for you
littlestevie, on Jul 15 2008, 04:14 PM, said:
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lea eax, [ebp+var_9] or byte ptr [eax], 10h // enable clock bit (1<<4) cmp [ebp+var_1C], 0 // arg == 0 ? jz short loc_1D1ED // if yes lea eax, [ebp+var_9] or byte ptr [eax], 2 // (if arg==1) v |= (1<<1) //set clock jmp short loc_1D1F3 ; --------------------------------------------------------------------------- loc_1D1ED:; CODE XREF: _DDCSetClock+20j lea eax, [ebp+var_9] and byte ptr [eax], 0FDh // v &= 0xfd //clear bit (1<<1) loc_1D1F3:; CODE XREF: _DDCSetClock+28jas you see it uses direct DAC (HIGH=1 LOW=0)
cmp [ebp+var_24], 2 jz short loc_1BBDA cmp [ebp+var_24], 3 jz short loc_1BBEE cmp [ebp+var_24], 1 jz short loc_1BBC6 jmp short loc_1BC00 ; --------------------------------------------------------------------------- loc_1BBC6: ; CODE XREF: _COMSetSense+A6j mov [ebp+var_E], 7E48h mov [ebp+var_C], 7E40h mov [ebp+var_A], 7E44h jmp short loc_1BC00 ; --------------------------------------------------------------------------- loc_1BBDA: ; CODE XREF: _COMSetSense+9Aj mov [ebp+var_E], 7E58h mov [ebp+var_C], 7E50h mov [ebp+var_A], 7E54h jmp short loc_1BC00 ; --------------------------------------------------------------------------- loc_1BBEE: ; CODE XREF: _COMSetSense+A0j mov [ebp+var_E], 7E68h mov [ebp+var_C], 7E60h mov [ebp+var_A], 7E64hI don't know what to patch in hardware I2C (edid_digital). Have you an idea?
mov [ebp+var_28], offset aNoneEdid; "NONE,EDID" mov [ebp+var_24], offset aTvEdid; "TV,EDID" mov [ebp+var_20], offset aDfp1Edid; "DFP1,EDID" mov [ebp+var_1C], offset aDfp2Edid; "DFP2,EDID" mov [ebp+var_18], offset aCrt1Edid; "CRT1,EDID" mov [ebp+var_14], offset aCrt2Edid; "CRT2,EDID" mov [ebp+var_10], offset aLvdsEdid; "LVDS,EDID" mov [ebp+var_C], offset aCompEdid; "COMP,EDID"It means you can inject EDID by Natit?
Slice, on Jul 16 2008, 06:03 AM, said:
Slice, on Jul 16 2008, 07:03 AM, said:
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dong, on Jul 16 2008, 05:42 PM, said:
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Slice, on Jul 16 2008, 09:03 PM, said:
Slice, on Jul 16 2008, 02:50 PM, said:
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info.ddc_i2c[2] = atom_setup_i2c_bus(0x7e60); .... i2c.put_clk_mask = (1 << 0); i2c.put_data_mask = (1 << 8); i2c.get_clk_mask = (1 << 0); i2c.get_data_mask = (1 << 8); i2c.mask_clk_mask = (1 << 0); i2c.mask_data_mask = (1 << 8); } i2c.mask_clk_reg = ddc_line; i2c.mask_data_reg = ddc_line; i2c.put_clk_reg = ddc_line + 0x8; i2c.put_data_reg = ddc_line + 0x8; i2c.get_clk_reg = ddc_line + 0xc; i2c.get_data_reg = ddc_line + 0xc;The last line arise me a question
loc_215D3: ; CODE XREF: _COMSetSense+A0j mov [ebp+var_E], 7E68h mov [ebp+var_C], 7E60h mov [ebp+var_A], 7E64hNow read RV630 AMD document
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val |= (Clock ? 0:pRADEONI2CBus->put_clk_mask);???
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tmp = INREG(BIOS_4_SCRATCH);
IOLog("ATIFB: radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
if (rinfo->has_CRTC2) {
/* primary DVI port */
if (tmp & 0x08)
rinfo->dviDisp_type = MT_DFP;
else if (tmp & 0x4)
rinfo->dviDisp_type = MT_LCD;
else if (tmp & 0x200)
rinfo->dviDisp_type = MT_CRT;
else if (tmp & 0x10)
rinfo->dviDisp_type = MT_CTV;
else if (tmp & 0x20)
rinfo->dviDisp_type = MT_STV;
/* secondary CRT port */
if (tmp & 0x2)
rinfo->crtDisp_type = MT_CRT;
else if (tmp & 0x800)
rinfo->crtDisp_type = MT_DFP;
else if (tmp & 0x400)
rinfo->crtDisp_type = MT_LCD;
else if (tmp & 0x1000)
rinfo->crtDisp_type = MT_CTV;
else if (tmp & 0x2000)
rinfo->crtDisp_type = MT_STV;
else
rinfo->crtDisp_type = MT_NONE;
} else {
rinfo->dviDisp_type = MT_NONE;
tmp = INREG(FP_GEN_CNTL);
if (tmp & FP_EN_TMDS)
rinfo->crtDisp_type = MT_DFP;
else
rinfo->crtDisp_type = MT_CRT;
}
With only LCD I have BIOS_4_SCRATCH=01000004 and BIOS_5_SCRATCH=01000001
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Espionage724, on Jul 19 2008, 01:50 AM, said:
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