1. My RadeonIGP have shared video memory located at physical address=0x38000000. But IONDRVFramebuffer works with address=0xd0000000. Internal Radeon readdressing? How it works?
I did a google and found this:
(II) RADEONHD(0): Mapped IO at 0x2b01de1c6000 (size 0x00010000)
(==) RADEONHD(0): Write-combining range (0xf0000000,0x8000000)
(II) RADEONHD(0): PCI FB Address (BAR) is at 0xF0000000 while card Internal
Address is 0x38000000
(II) RADEONHD(0): Mapped FB at 0x2b01de861000 (size 0x08000000)
Looks like PCI Address VS. GPU Address, but I have no idea about their detailed roles as both are Physical addresses in the eye of the device driver. Maybe DMA GART readdressing is involved in the PCI Address scheme.
2. Radeon Register
MPP_TB_CONFIG = 0x134
used only for save and restore. Its function?
Also by google, I found this:
> 1) If MEM_CNTL and CONFIG_MEMSIZE are not re-initialised to their power-up
> value, a BIOS bug ends up corrupting the chip's memory interface.
> 2) If the misnamed MPP_TB_CONFIG
register is not set properly, a bug in
> the chip causes it to return zeroes for read-outs of its PCI ROM.
> Both issues have been seen using various Radeon cores, including R200,
> RV200, etc.
> > > MPP_TB_CONFIG
was for an issue on the Radeon 7500
> > > (RV200). Unfortunately, I can't elaborate too much on what exactly it
> > > does, because it's a fix we got from ATI without much detail. The
> > > problem it fixed, though, is that without the MPP_TB_CONFIG
> > > BIOS ROM can't be read after the BIOS has been run.
ie., MPP_TB_CONFIG must be handled in case the card BIOS is run multiple times. Reboot is an example. Otherwise, only zero is returned when read the BIOS ROM for the second time.
3. How many differences between R400, R500 and R600 family?
Can't say much about this. The difference between R500 and R600 should be less when compared with R400 since at least R500 and R600 are dealt by the same linux driver although in many cases parallel functions are used to treat R500 and R600 differently.