Do we really need an SSDT for the CPU nowadays?

chriz74 · October 17, 2016

My cpu is an i7-3630QM .. if I put an ssdt (created with ssdtPRGen) in the ACPI/patched directory nothing will change.

While booting Clover gets the cpu properties like this:

0:100 0:000 === [ GetCPUProperties ] ==================================

0:100 0:000 CPU Vendor = 756E6547 Model=306A9

0:100 0:000 got cores from CPUID_1 = 0

0:100 0:000 The CPU supported turbo

0:100 0:000 BrandString = Intel® Core i7-3630QM CPU @ 2.40GHz

0:100 0:000 MSR 0xE2 before patch 1E000404

0:100 0:000 MSR 0xE4 00020414

0:100 0:000 MSR 0xCE 00080C10_E0011800

0:100 0:000 non-usable FLEX_RATIO = 110000

0:100 0:000 corrected FLEX_RATIO = 100000

0:100 0:000 MSR 0x1B0 00000000

0:100 0:000 FSBFrequency=100MHz DMIvalue=100000kHz

0:100 0:000 Corrected FSBFrequency=100MHz

0:100 0:000 Vendor/Model/Stepping: 0x756E6547/0x3A/0x9

0:100 0:000 Family/ExtFamily: 0x6/0x0

0:100 0:000 MaxDiv/MinDiv: 24.0/12

0:100 0:000 Turbo: 32/32/33/34

0:100 0:000 Features: 0xBFEBFBFF

0:100 0:000 Threads: 8

0:100 0:000 Cores: 4

0:100 0:000 FSB: 100 MHz

0:100 0:000 CPU: 2400 MHz

0:100 0:000 TSC: 2400 MHz

0:100 0:000 PIS: 400 MHz

Only strange thing I see there is in the turbo ratios being 32/32/33/34, why twice 32 ? I don't know.

However then Clover inserts the SSDT:

Inserting SSDT.AML from EFI\CLOVER\ACPI\patched ... Success

but nothing changes, I can remove it and the CPU will behave in the same way. So the question is, what is Clover doing with that ssdt? Shouldn't it look for an SSDT before searching for the CPU properties? And what use has the Drop OEM bool under ACPI/SSDT in Clover Config.plist? I can enable or disable it and nothing will change.

By the way here the tables that Clover finds during boot:

=== [ GetAcpiTablesList ] =================================

0:696 0:000 Get Acpi Tables List from RSDT:

0:696 0:000 - [00]: FACP Notebook len=132

0:696 0:000 - [01]: APIC Notebook len=146

0:696 0:000 - [02]: FPDT Notebook len=68

0:696 0:000 - [03]: ECDT Notebook len=193

0:696 0:000 - [04]: MCFG Notebook len=60

0:696 0:000 - [05]: SLIC Notebook len=374

0:696 0:000 - [06]: HPET Notebook len=56

0:696 0:000 - [07]: SSDT AhciTab1 len=1424

0:696 0:000 - [08]: SSDT AhciTab2 len=1182

0:696 0:000 - [09]: SSDT Cpu0Ist len=2380

0:696 0:000 - [10]: SSDT CpuPm len=2840

then if Drop OEM is active it will drop these:

2:291 0:000 === [ ACPIDropTables ] ====================================

2:291 0:000 === [ DropSSDT ] ==========================================

2:291 0:000 Drop tables from Xsdt, SIGN=SSDT TableID= Length=0

2:291 0:000 Xsdt has tables count=11

2:291 0:000 Table: SSDT AhciTab1 1424 dropped

2:291 0:000 Table: SSDT AhciTab2 1182 dropped

2:291 0:000 Table: SSDT Cpu0Ist 2380 dropped

2:291 0:000 Table: SSDT CpuPm 2840 dropped

2:291 0:000 corrected XSDT length=92

if not it will patch the length or something, either way nothing changes.

Allan · October 17, 2016

Check your states with AppleIntelInfo.

mnfesq · October 17, 2016

I checked my boot log and I have CPU properties and ACPI properties before the message that SSDT is loaded. I'm not sure that the message order is determinative of anything. My config.plist has no settings selected for SSDT other than to drop the OEM SSDT. If your config.plist has options selected, you may not see any difference between having an SSDT in ACPI/patched or not. When I remove my SSDT, I lose speedstepping. Enabling P States and C States in Clover restores it somewhat but not as fully as my custom SSDT.

Picasso · October 17, 2016

Haswell and Skylake don't need SSDT.

Off topic:

THe point now is the Rx 480 and Nvidia Pascal.

chriz74 · October 17, 2016

Mine is ivy bridge. Drop oem seems to be dropping acpi tables found in the bios not the injected ssdt. The ssdt will be used either way if you select drop oem or not. Anyway here the pc behavior doesn't change at all if selected or not.

P.s. I don't have anything in ssdt apart drop oem (if enabled)

chriz74 · October 18, 2016

Check that you've got the correct ssdtPRGen CPU definitions in your <home directory>/Library/ssdtPRGen/Data (from Terminal, its ~Library/ssdtPRGen/Data). You should see several files there including one called Ivy Bridge.cfg which should contain the following entry:
i7-3630QM,45,0,2400,3400,4,8
Then make sure you have an appropriate Ivy Bridge platform SMBIOS profile like MacBookPro9,1/9,2/10,1 for instance.

Are you getting native CPU speedstep + Turbo boost with your generated SSDT? If you do not, ensure you do not have NullCPUPM installed somewhere and loaded. If you post your generated SSDT, we can probably look for an eventual mistake in it that would cause the double x32 CPU multiplier and it should be very easy to repair that to x31/x32. But it really should not happen if you have the correct (latest) version of ssdtPRGen installed. Always get it directly off Pike R Alpha's repository site.

Probably I didn't make it clear. The ssdt is correct, my bios is unlocked. The 32/32 is Clover info, not from the ssdt. What I'm saying is 1) I can remove the ssdt and the CPU will be recognized by Clover without any hassle. 2) the Clover Drop OEM option albeit doing something if set or not doesn't modify anything in the OS and Computer Hardware behavior.

chriz74 · October 18, 2016

Here is the AppleIntel info for those who were interested:

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1

Warning: Clover hw.busfrequency error detected : 17d78400
InitialTSC...............................: 0x219252c525 (6 MHz)
MWAIT C-States...........................: 135456

Processor Brandstring....................:       Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz

Processor Signature..................... : 0x306A9
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 9
 - Model................................ : 0x3A (58)

Model Specific Registers (MSRs)
------------------------------------------

MSR_CORE_THREAD_COUNT............(0x35)  : 0xFFFFFF8023A8FA00
------------------------------------------
 - Core Count........................... : 4
 - Thread Count......................... : 8

MSR_PLATFORM_INFO................(0xCE)  : 0x80C10E0011800
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x18 (2400 MHz)
 - Ratio Limit for Turbo Mode........... : 0 (not programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 0 (LMP not supported)
 - Number of ConfigTDP Levels........... : 0 (only base TDP level available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x405
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 0 (disabled/unsupported)
 - C1 State Auto Demotion............... : 0 (disabled/unsupported)
 - C3 State Undemotion.................. : 0 (disabled/unsupported)
 - C1 State Undemotion.................. : 0 (disabled/unsupported)
 - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
 - Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x20414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 2 (C7 is the max C-State to include)

IA32_MPERF.......................(0xE7)  : 0x13485D9459
IA32_APERF.......................(0xE8)  : 0xFABB94C40

MSR_FLEX_RATIO...................(0x194) : 0x100000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x245900002000
------------------------------------------
 - Current Performance State Value...... : 0x2000 (3200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0x2100
------------------------------------------
 - Target performance State Value....... : 0x2100 (3300 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0
IA32_THERM_STATUS................(0x19C) : 0x88270808

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Performance Monitoring............... : 1 (available)
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - CFG Lock............................. : 0 (MSR not locked)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x691200
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 105
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400001
------------------------------------------
 - EIST Hardware Coordination........... : 1 (hardware coordination disabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x20202122
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 22 (3400 MHz) 
 - Maximum Ratio Limit for C02.......... : 21 (3300 MHz) 
 - Maximum Ratio Limit for C03.......... : 20 (3200 MHz) 
 - Maximum Ratio Limit for C04.......... : 20 (3200 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x4
------------------------------------------

MSR_POWER_CTL....................(0x1FC) : 0x14005F
------------------------------------------
 - C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA1003
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 16 (15.3 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x800081C2001E8168
------------------------------------------
 - Package Power Limit #1............... : 45 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 0 (disabled)
 - Time Window for Power Limit #1....... : 15 (81920 milli-Seconds)
 - Package Power Limit #2............... : 56 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 0 (disabled)
 - Time Window for Power Limit #2....... : 0 (2 milli-Seconds)
 - Lock................................. : 1 (MSR locked until next reset)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x39A3696
------------------------------------------
 - Total Energy Consumed................ : 922 Joules (Watt = Joules / seconds)

MSR_PKG_POWER_INFO...............(0x614) : 0x10000001200168
------------------------------------------
 - Thermal Spec Power................... : 45 Watt
 - Minimum Power........................ : 0
 - Maximum Power........................ : 0
 - Maximum Time Window.................. : 0

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x2D7331E
------------------------------------------
 - Total Energy Consumed................ : 727 Joules (Watt = Joules / seconds)

MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0
MSR_PP1_CURRENT_CONFIG...........(0x602) : 0x1814149480000170

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0x6CB24
------------------------------------------
 - Total Energy Consumed................ : 6 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x10
------------------------------------------
 - Priority Level....................... : 16

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x18
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x120000000000000
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x120000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x80000000
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x883B
MSR_PKGC6_IRTL...................(0x60b) : 0x8850
MSR_PKGC7_IRTL...................(0x60c) : 0x8857
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x183E700
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x2C62F8
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0x14EB8268

IA32_TSC_DEADLINE................(0x6E0) : 0x21959A8A3D

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 24 (2400 MHz)
Maximum Turbo Ratio/Frequency............: 34 (3400 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:  350 MHz
IGPU Minimum Frequency...................:  350 MHz
IGPU Maximum Non-Turbo Frequency.........:  650 MHz
IGPU Maximum Turbo Frequency.............: 1150 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ 21 32 (33) ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 3 4 5 ]
CPU C6-Cores [ 2 6 7 ]
CPU C7-Cores [ 0 1 6 7 ]
CPU P-States [ 21 (32) 33 34 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 3 4 5 7 ]
CPU C6-Cores [ 2 3 6 7 ]
CPU C7-Cores [ 0 1 2 4 5 6 7 ]
CPU C3-Cores [ 0 1 3 4 5 6 7 ]
CPU P-States [ (12) 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 17 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU C7-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 17 18 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 17 18 19 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 17 18 19 21 (22) 28 32 33 34 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 16 17 18 19 21 22 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 16 17 18 19 21 22 24 28 (32) 33 34 ] iGPU P-States [ (7) ]
CPU C6-Cores [ 2 3 4 5 6 7 ]
CPU P-States [ 12 16 17 18 19 21 22 24 25 28 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 16 17 18 19 21 22 24 25 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 16 17 18 19 20 21 22 24 25 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 16 17 18 19 20 21 22 24 25 26 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 (9) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 (23) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ (7) 9 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 (22) 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 (30) 31 32 33 34 ] iGPU P-States [ 7 9 (20) 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 (30) 31 32 33 34 ] iGPU P-States [ 7 9 (19) 20 22 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 9 (12) 19 20 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 (10) 12 19 20 22 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 (8) 9 10 12 19 20 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 12 (18) 19 20 22 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 (11) 12 18 19 20 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 (13) 18 19 20 22 23 ]

EDIT: I set QPI = 100 in Clover to get rid of the Warning "Clover hw.busfrequency error detected : 17d78400" and now I got this:

AppleIntelInfo.kext v1.8e Copyright © 2012-2016 Pike R. Alpha. All rights reserved

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1
InitialTSC...............................: 0x3328d5c194 (9 MHz)
MWAIT C-States...........................: 135456

Processor Brandstring....................:       Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz

Processor Signature..................... : 0x306A9
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 9
 - Model................................ : 0x3A (58)

Model Specific Registers (MSRs)
------------------------------------------

MSR_CORE_THREAD_COUNT............(0x35)  : 0xFFFFFF8044E4DA00
------------------------------------------
 - Core Count........................... : 4
 - Thread Count......................... : 8

MSR_PLATFORM_INFO................(0xCE)  : 0x80C10E0011800
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x18 (2400 MHz)
 - Ratio Limit for Turbo Mode........... : 0 (not programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 0 (LMP not supported)
 - Number of ConfigTDP Levels........... : 0 (only base TDP level available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x405
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 0 (disabled/unsupported)
 - C1 State Auto Demotion............... : 0 (disabled/unsupported)
 - C3 State Undemotion.................. : 0 (disabled/unsupported)
 - C1 State Undemotion.................. : 0 (disabled/unsupported)
 - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
 - Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x20414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 2 (C7 is the max C-State to include)

IA32_MPERF.......................(0xE7)  : 0x179B53089B
IA32_APERF.......................(0xE8)  : 0x1168BD6E1A

MSR_FLEX_RATIO...................(0x194) : 0x100000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x233A00002000
------------------------------------------
 - Current Performance State Value...... : 0x2000 (3200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0x2200
------------------------------------------
 - Target performance State Value....... : 0x2200 (3400 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0
IA32_THERM_STATUS................(0x19C) : 0x882F0808

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Performance Monitoring............... : 1 (available)
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - CFG Lock............................. : 0 (MSR not locked)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x691200
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 105
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400001
------------------------------------------
 - EIST Hardware Coordination........... : 1 (hardware coordination disabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x20202122
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 22 (3400 MHz) 
 - Maximum Ratio Limit for C02.......... : 21 (3300 MHz) 
 - Maximum Ratio Limit for C03.......... : 20 (3200 MHz) 
 - Maximum Ratio Limit for C04.......... : 20 (3200 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x4
------------------------------------------

MSR_POWER_CTL....................(0x1FC) : 0x14005F
------------------------------------------
 - C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA1003
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 16 (15.3 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x800081C2001E8168
------------------------------------------
 - Package Power Limit #1............... : 45 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 0 (disabled)
 - Time Window for Power Limit #1....... : 15 (81920 milli-Seconds)
 - Package Power Limit #2............... : 56 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 0 (disabled)
 - Time Window for Power Limit #2....... : 0 (2 milli-Seconds)
 - Lock................................. : 1 (MSR locked until next reset)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x42B6A8C
------------------------------------------
 - Total Energy Consumed................ : 1067 Joules (Watt = Joules / seconds)

MSR_PKG_POWER_INFO...............(0x614) : 0x10000001200168
------------------------------------------
 - Thermal Spec Power................... : 45 Watt
 - Minimum Power........................ : 0
 - Maximum Power........................ : 0
 - Maximum Time Window.................. : 0

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x3089806
------------------------------------------
 - Total Energy Consumed................ : 776 Joules (Watt = Joules / seconds)

MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0
MSR_PP1_CURRENT_CONFIG...........(0x602) : 0x1814149480000170

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0x73A74
------------------------------------------
 - Total Energy Consumed................ : 7 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x10
------------------------------------------
 - Priority Level....................... : 16

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x18
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x120000000000000
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x120000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x80000000
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x883B
MSR_PKGC6_IRTL...................(0x60b) : 0x8850
MSR_PKGC7_IRTL...................(0x60c) : 0x8857
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x222B62F8
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x7BDBF18
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0xC276DCF38

IA32_TSC_DEADLINE................(0x6E0) : 0x332CBA428E

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 24 (2400 MHz)
Maximum Turbo Ratio/Frequency............: 34 (3400 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:  350 MHz
IGPU Minimum Frequency...................:  350 MHz
IGPU Maximum Non-Turbo Frequency.........:  650 MHz
IGPU Maximum Turbo Frequency.............: 1150 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ (12) 19 22 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 4 5 ]
CPU C6-Cores [ 0 1 3 4 6 ]
CPU C7-Cores [ 2 3 4 6 ]
CPU P-States [ (12) 17 19 22 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 ]
CPU C6-Cores [ 0 1 2 3 4 6 ]
CPU C7-Cores [ 0 1 2 3 4 6 7 ]
CPU P-States [ (12) 15 17 19 22 ] iGPU P-States [ (7) ]
CPU C6-Cores [ 0 1 2 3 4 5 6 ]
CPU P-States [ 12 15 17 19 22 (30) ] iGPU P-States [ (7) ]
CPU P-States [ 12 15 17 19 22 30 (32) ] iGPU P-States [ (7) ]
CPU C7-Cores [ 0 1 2 3 4 5 6 7 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 15 17 19 22 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 15 17 19 21 22 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 17 19 21 22 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 17 19 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 17 18 19 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 13 15 16 17 18 19 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 16 17 18 19 20 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 30 32 (33) ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 29 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 (29) 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (33) ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 (12) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 (9) 12 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 9 (11) 12 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 (8) 9 11 12 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 8 9 (10) 11 12 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 8 9 10 11 12 (15) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 (21) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 21 (23) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 (20) 21 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 (16) 20 21 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 (13) 15 16 20 21 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 8 9 10 11 12 13 (14) 15 16 20 21 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (31) 32 33 ] iGPU P-States [ 7 8 9 10 11 12 13 14 15 16 (18) 20 21 23 ]

Edit 2: With QPI = 100 it seems I can't get the x34 multiplier. I made may tests it always stops at x33.

I tried to remove Drop OEM and nothing changed, BDMESG shows this behavior:

3:311  0:000  === [ ACPIDropTables ] ====================================
3:311  0:000  === [ PatchAllSSDT ] ======================================
3:311  0:000  Patch table: SSDT  AhciTab1
3:311  0:000   SSDT len = 0x590
3:311  0:000  Patch table: SSDT  AhciTab2
3:311  0:000   SSDT len = 0x49E
3:311  0:000  Patch table: SSDT  Cpu0Ist
3:311  0:000   SSDT len = 0x94C
3:311  0:000  Patch table: SSDT  CpuPm
3:311  0:000   SSDT len = 0xB18
3:311  0:000  Drop tables from Xsdt, SIGN=XXXX TableID= Length=0
3:311  0:000   Xsdt has tables count=11
3:311  0:000  corrected XSDT length=124
3:311  0:000  === [ ACPIPatchedAML ] ====================================
3:311  0:000  Start: Processing Patched AML(s): Unsorted
3:311  0:000  Inserting SSDT.AML from EFI\CLOVER\ACPI\patched ... Success
3:312  0:001  End: Processing Patched AML(s)
3:312  0:000  CPUBase=0 and ApicCPUBase=1 ApicCPUNum=8

It seems to me it first patches the ACPI tables including Cpu0Ist then it inserts the SSDT.aml which AFAIK should replace that table.

Here are the two ssdt I am using to test:

This one is an old generated one:

/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20160422-64(RM)
 * Copyright (c) 2000 - 2016 Intel Corporation
 * 
 * Disassembling to non-symbolic legacy ASL operators
 *
 * Disassembly of iASLiyekUv.aml, Tue Oct 18 12:35:43 2016
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x0000083E (2110)
 *     Revision         0x01
 *     Checksum         0x72
 *     OEM ID           "APPLE "
 *     OEM Table ID     "CpuPm"
 *     OEM Revision     0x00015600 (87552)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20100331 (537920305)
 */
DefinitionBlock ("", "SSDT", 1, "APPLE ", "CpuPm", 0x00015600)
{
    External (_PR_.CPU0, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU1, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU2, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU3, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU4, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU5, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU6, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU7, DeviceObj)    // Warning: Unknown object

    Scope (\_PR.CPU0)
    {
        Method (_INI, 0, NotSerialized)  // _INI: Initialize
        {
            Store ("ssdtPRGen version....: 15.6 / Mac OS X 10.10.2 (14C109)", Debug)
            Store ("target processor.....: i7-3630QM", Debug)
            Store ("running processor....: Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz", Debug)
            Store ("baseFrequency........: 1200", Debug)
            Store ("frequency............: 2400", Debug)
            Store ("busFrequency.........: 100", Debug)
            Store ("logicalCPUs..........: 8", Debug)
            Store ("maximum TDP..........: 45", Debug)
            Store ("packageLength........: 23", Debug)
            Store ("turboStates..........: 10", Debug)
            Store ("maxTurboFrequency....: 3400", Debug)
            Store ("IvyWorkArounds.......: 3", Debug)
            Store ("machdep.xcpm.mode....: 0", Debug)
        }

        Name (APLF, 0x04)
        Name (APSN, 0x0B)
        Name (APSS, Package (0x1C)
        {
            Package (0x06)
            {
                0x0D49, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2300, 
                0x2300
            }, 

            Package (0x06)
            {
                0x0D48, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2200, 
                0x2200
            }, 

            Package (0x06)
            {
                0x0CE4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2100, 
                0x2100
            }, 

            Package (0x06)
            {
                0x0C80, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2000, 
                0x2000
            }, 

            Package (0x06)
            {
                0x0C1C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1F00, 
                0x1F00
            }, 

            Package (0x06)
            {
                0x0BB8, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1E00, 
                0x1E00
            }, 

            Package (0x06)
            {
                0x0B54, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1D00, 
                0x1D00
            }, 

            Package (0x06)
            {
                0x0AF0, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1C00, 
                0x1C00
            }, 

            Package (0x06)
            {
                0x0A8C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1B00, 
                0x1B00
            }, 

            Package (0x06)
            {
                0x0A28, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1A00, 
                0x1A00
            }, 

            Package (0x06)
            {
                0x09C4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1900, 
                0x1900
            }, 

            Package (0x06)
            {
                0x0960, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1800, 
                0x1800
            }, 

            Package (0x06)
            {
                0x08FC, 
                0xA68C, 
                0x0A, 
                0x0A, 
                0x1700, 
                0x1700
            }, 

            Package (0x06)
            {
                0x0898, 
                0x9D7D, 
                0x0A, 
                0x0A, 
                0x1600, 
                0x1600
            }, 

            Package (0x06)
            {
                0x0834, 
                0x949C, 
                0x0A, 
                0x0A, 
                0x1500, 
                0x1500
            }, 

            Package (0x06)
            {
                0x07D0, 
                0x8BE6, 
                0x0A, 
                0x0A, 
                0x1400, 
                0x1400
            }, 

            Package (0x06)
            {
                0x076C, 
                0x835D, 
                0x0A, 
                0x0A, 
                0x1300, 
                0x1300
            }, 

            Package (0x06)
            {
                0x0708, 
                0x7B00, 
                0x0A, 
                0x0A, 
                0x1200, 
                0x1200
            }, 

            Package (0x06)
            {
                0x06A4, 
                0x72CD, 
                0x0A, 
                0x0A, 
                0x1100, 
                0x1100
            }, 

            Package (0x06)
            {
                0x0640, 
                0x6AC6, 
                0x0A, 
                0x0A, 
                0x1000, 
                0x1000
            }, 

            Package (0x06)
            {
                0x05DC, 
                0x62EA, 
                0x0A, 
                0x0A, 
                0x0F00, 
                0x0F00
            }, 

            Package (0x06)
            {
                0x0578, 
                0x5B37, 
                0x0A, 
                0x0A, 
                0x0E00, 
                0x0E00
            }, 

            Package (0x06)
            {
                0x0514, 
                0x53AF, 
                0x0A, 
                0x0A, 
                0x0D00, 
                0x0D00
            }, 

            Package (0x06)
            {
                0x04B0, 
                0x4C50, 
                0x0A, 
                0x0A, 
                0x0C00, 
                0x0C00
            }, 

            Package (0x06)
            {
                0x044C, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0B00, 
                0x0B00
            }, 

            Package (0x06)
            {
                0x03E8, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0A00, 
                0x0A00
            }, 

            Package (0x06)
            {
                0x0384, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0900, 
                0x0900
            }, 

            Package (0x06)
            {
                0x0320, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0800, 
                0x0800
            }
        })
        Method (ACST, 0, NotSerialized)
        {
            Store ("Method CPU0.ACST Called", Debug)
            Store ("CPU0 C-States    : 29", Debug)
            Return (Package (0x06)
            {
                One, 
                0x04, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    Zero, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xCD, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000020, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x06, 
                    0xF5, 
                    0x015E
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x07, 
                    0xF5, 
                    0xC8
                }
            })
        }

        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
        {
            Store ("Method CPU0._DSM Called", Debug)
            If (LEqual (Arg2, Zero))
            {
                Return (Buffer (One)
                {
                     0x03                                           
                })
            }

            Return (Package (0x02)
            {
                "plugin-type", 
                One
            })
        }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU1.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method CPU1.ACST Called", Debug)
            Store ("CPU1 C-States    : 7", Debug)
            Return (Package (0x05)
            {
                One, 
                0x03, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    0x03E8, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x02, 
                    0x94, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xC6, 
                    0xC8
                }
            })
        }
    }

    Scope (\_PR.CPU2)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU2.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU3)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU3.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU4)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU4.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU5)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU5.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU6)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU6.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU7)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU7.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }
}

Anf this the one that ssdtPRGen creates with latest release:

/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20160422-64(RM)
 * Copyright (c) 2000 - 2016 Intel Corporation
 * 
 * Disassembling to non-symbolic legacy ASL operators
 *
 * Disassembly of iASLGCB1n6.aml, Tue Oct 18 12:36:43 2016
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x00000875 (2165)
 *     Revision         0x01
 *     Checksum         0x6A
 *     OEM ID           "APPLE "
 *     OEM Table ID     "CpuPm"
 *     OEM Revision     0x00020500 (132352)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20140926 (538183974)
 */
DefinitionBlock ("", "SSDT", 1, "APPLE ", "CpuPm", 0x00020500)
{
    External (_PR_.CPU0, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU1, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU2, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU3, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU4, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU5, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU6, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU7, DeviceObj)    // Warning: Unknown object

    Scope (\_PR.CPU0)
    {
        Method (_INI, 0, NotSerialized)  // _INI: Initialize
        {
            Store ("ssdtPRGen version.....: 20.5 / Mac OS X 10.12 (16A323)", Debug)
            Store ("custom mode...........: 0", Debug)
            Store ("host processor........: Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz", Debug)
            Store ("target processor......: i7-3630QM", Debug)
            Store ("number of processors..: 1", Debug)
            Store ("baseFrequency.........: 1200", Debug)
            Store ("frequency.............: 2400", Debug)
            Store ("busFrequency..........: 100", Debug)
            Store ("logicalCPUs...........: 8", Debug)
            Store ("maximum TDP...........: 45", Debug)
            Store ("packageLength.........: 23", Debug)
            Store ("turboStates...........: 10", Debug)
            Store ("maxTurboFrequency.....: 3400", Debug)
            Store ("CPU Workarounds.......: 2", Debug)
        }

        Name (APLF, 0x05)
        Name (APSN, 0x0A)
        Name (APSS, Package (0x1C)
        {
            Package (0x06)
            {
                0x0D48, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2200, 
                0x2200
            }, 

            Package (0x06)
            {
                0x0CE4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2100, 
                0x2100
            }, 

            Package (0x06)
            {
                0x0C80, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2000, 
                0x2000
            }, 

            Package (0x06)
            {
                0x0C1C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1F00, 
                0x1F00
            }, 

            Package (0x06)
            {
                0x0BB8, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1E00, 
                0x1E00
            }, 

            Package (0x06)
            {
                0x0B54, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1D00, 
                0x1D00
            }, 

            Package (0x06)
            {
                0x0AF0, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1C00, 
                0x1C00
            }, 

            Package (0x06)
            {
                0x0A8C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1B00, 
                0x1B00
            }, 

            Package (0x06)
            {
                0x0A28, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1A00, 
                0x1A00
            }, 

            Package (0x06)
            {
                0x09C4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1900, 
                0x1900
            }, 

            Package (0x06)
            {
                0x0960, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1800, 
                0x1800
            }, 

            Package (0x06)
            {
                0x08FC, 
                0xA68C, 
                0x0A, 
                0x0A, 
                0x1700, 
                0x1700
            }, 

            Package (0x06)
            {
                0x0898, 
                0x9D7D, 
                0x0A, 
                0x0A, 
                0x1600, 
                0x1600
            }, 

            Package (0x06)
            {
                0x0834, 
                0x949C, 
                0x0A, 
                0x0A, 
                0x1500, 
                0x1500
            }, 

            Package (0x06)
            {
                0x07D0, 
                0x8BE6, 
                0x0A, 
                0x0A, 
                0x1400, 
                0x1400
            }, 

            Package (0x06)
            {
                0x076C, 
                0x835D, 
                0x0A, 
                0x0A, 
                0x1300, 
                0x1300
            }, 

            Package (0x06)
            {
                0x0708, 
                0x7B00, 
                0x0A, 
                0x0A, 
                0x1200, 
                0x1200
            }, 

            Package (0x06)
            {
                0x06A4, 
                0x72CD, 
                0x0A, 
                0x0A, 
                0x1100, 
                0x1100
            }, 

            Package (0x06)
            {
                0x0640, 
                0x6AC6, 
                0x0A, 
                0x0A, 
                0x1000, 
                0x1000
            }, 

            Package (0x06)
            {
                0x05DC, 
                0x62EA, 
                0x0A, 
                0x0A, 
                0x0F00, 
                0x0F00
            }, 

            Package (0x06)
            {
                0x0578, 
                0x5B37, 
                0x0A, 
                0x0A, 
                0x0E00, 
                0x0E00
            }, 

            Package (0x06)
            {
                0x0514, 
                0x53AF, 
                0x0A, 
                0x0A, 
                0x0D00, 
                0x0D00
            }, 

            Package (0x06)
            {
                0x04B0, 
                0x4C50, 
                0x0A, 
                0x0A, 
                0x0C00, 
                0x0C00
            }, 

            Package (0x06)
            {
                0x044C, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0B00, 
                0x0B00
            }, 

            Package (0x06)
            {
                0x03E8, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0A00, 
                0x0A00
            }, 

            Package (0x06)
            {
                0x0384, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0900, 
                0x0900
            }, 

            Package (0x06)
            {
                0x0320, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0800, 
                0x0800
            }, 

            Package (0x06)
            {
                0x02BC, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0700, 
                0x0700
            }
        })
        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU0.ACST Called", Debug)
            Store ("CPU0 C-States    : 29", Debug)
            Return (Package (0x06)
            {
                One, 
                0x04, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    Zero, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xCD, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000020, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x06, 
                    0xF5, 
                    0x015E
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x07, 
                    0xF5, 
                    0xC8
                }
            })
        }

        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
        {
            Store ("Method _PR_.CPU0._DSM Called", Debug)
            If (LEqual (Arg2, Zero))
            {
                Return (Buffer (One)
                {
                     0x03                                           
                })
            }

            Return (Package (0x02)
            {
                "plugin-type", 
                One
            })
        }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU1.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU1.ACST Called", Debug)
            Store ("CPU1 C-States    : 7", Debug)
            Return (Package (0x05)
            {
                One, 
                0x03, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    0x03E8, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x02, 
                    0x94, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xC6, 
                    0xC8
                }
            })
        }
    }

    Scope (\_PR.CPU2)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU2.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU3)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU3.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU4)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU4.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU5)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU5.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU6)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU6.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU7)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU7.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }
}

By the way, HWmon from time to time shows insane multiplier data for single cores like x152 or similar.

Edit 3: After removing Drop OEM the x34 multiplier showed up again, this with the newly generated SSDT:

CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) ] iGPU P-States [ (7) 9 10 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 9 10 (12) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 10 12 13 (14) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 (8) 9 10 12 13 14 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 (24) 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 (11) 12 13 14 ]

Full report:

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1
InitialTSC...............................: 0x390e69e8f8 (10 MHz)
MWAIT C-States...........................: 135456

Processor Brandstring....................:       Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz

Processor Signature..................... : 0x306A9
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 9
 - Model................................ : 0x3A (58)

Model Specific Registers (MSRs)
------------------------------------------

MSR_CORE_THREAD_COUNT............(0x35)  : 0xFFFFFF805337B500
------------------------------------------
 - Core Count........................... : 4
 - Thread Count......................... : 8

MSR_PLATFORM_INFO................(0xCE)  : 0x80C10E0011800
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x18 (2400 MHz)
 - Ratio Limit for Turbo Mode........... : 0 (not programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 0 (LMP not supported)
 - Number of ConfigTDP Levels........... : 0 (only base TDP level available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x405
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 0 (disabled/unsupported)
 - C1 State Auto Demotion............... : 0 (disabled/unsupported)
 - C3 State Undemotion.................. : 0 (disabled/unsupported)
 - C1 State Undemotion.................. : 0 (disabled/unsupported)
 - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
 - Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x20414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 2 (C7 is the max C-State to include)

IA32_MPERF.......................(0xE7)  : 0x2FA50A3DDD
IA32_APERF.......................(0xE8)  : 0x1C8AC2206A

MSR_FLEX_RATIO...................(0x194) : 0x100000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x1A1900000C00
------------------------------------------
 - Current Performance State Value...... : 0xC00 (1200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0x2000
------------------------------------------
 - Target performance State Value....... : 0x2000 (3200 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0
IA32_THERM_STATUS................(0x19C) : 0x882C080C

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Performance Monitoring............... : 1 (available)
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - CFG Lock............................. : 0 (MSR not locked)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x691200
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 105
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400001
------------------------------------------
 - EIST Hardware Coordination........... : 1 (hardware coordination disabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x20202122
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 22 (3400 MHz) 
 - Maximum Ratio Limit for C02.......... : 21 (3300 MHz) 
 - Maximum Ratio Limit for C03.......... : 20 (3200 MHz) 
 - Maximum Ratio Limit for C04.......... : 20 (3200 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x4
------------------------------------------

MSR_POWER_CTL....................(0x1FC) : 0x14005F
------------------------------------------
 - C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA1003
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 16 (15.3 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x800081C2001E8168
------------------------------------------
 - Package Power Limit #1............... : 45 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 0 (disabled)
 - Time Window for Power Limit #1....... : 15 (81920 milli-Seconds)
 - Package Power Limit #2............... : 56 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 0 (disabled)
 - Time Window for Power Limit #2....... : 0 (2 milli-Seconds)
 - Lock................................. : 1 (MSR locked until next reset)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x55A25CA
------------------------------------------
 - Total Energy Consumed................ : 1370 Joules (Watt = Joules / seconds)

MSR_PKG_POWER_INFO...............(0x614) : 0x10000001200168
------------------------------------------
 - Thermal Spec Power................... : 45 Watt
 - Minimum Power........................ : 0
 - Maximum Power........................ : 0
 - Maximum Time Window.................. : 0

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x40D0DEA
------------------------------------------
 - Total Energy Consumed................ : 1037 Joules (Watt = Joules / seconds)

MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0
MSR_PP1_CURRENT_CONFIG...........(0x602) : 0x1814149480000170

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0xB6214
------------------------------------------
 - Total Energy Consumed................ : 11 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x10
------------------------------------------
 - Priority Level....................... : 16

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x18
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x120000000000000
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x120000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x80000000
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x883B
MSR_PKGC6_IRTL...................(0x60b) : 0x8850
MSR_PKGC7_IRTL...................(0x60c) : 0x8857
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x9802B0
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x3584E8
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0xCA2A338

IA32_TSC_DEADLINE................(0x6E0) : 0x3912996722

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 24 (2400 MHz)
Maximum Turbo Ratio/Frequency............: 34 (3400 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:  350 MHz
IGPU Minimum Frequency...................:  350 MHz
IGPU Maximum Non-Turbo Frequency.........:  650 MHz
IGPU Maximum Turbo Frequency.............: 1150 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ 12 14 (32) ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 2 5 6 7 ]
CPU C6-Cores [ 3 4 5 ]
CPU C7-Cores [ 1 3 4 6 ]
CPU C3-Cores [ 0 2 3 4 5 6 7 ]
CPU C6-Cores [ 2 3 4 5 ]
CPU C7-Cores [ 0 1 2 3 4 6 7 ]
CPU P-States [ 12 14 31 (32) ] iGPU P-States [ (7) ]
CPU C7-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 14 29 31 32 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 14 15 29 31 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 14 15 20 29 31 32 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 20 (24) 29 31 32 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 19 20 24 29 (30) 31 32 ] iGPU P-States [ 7 (13) ]
CPU P-States [ (12) 14 15 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 14 15 16 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 18 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 18 19 20 22 24 29 30 31 32 (33) ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 22 24 29 30 31 (32) 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 22 23 24 29 30 31 (32) 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 22 23 24 27 29 30 31 32 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 22 23 24 25 27 29 30 31 (32) 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 29 30 31 32 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 (33) ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (26) 27 28 29 30 31 32 33 ] iGPU P-States [ (7) 13 ]
CPU C6-Cores [ 0 1 2 3 4 5 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 (9) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 9 (10) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) ] iGPU P-States [ (7) 9 10 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 9 10 (12) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 10 12 13 (14) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 (8) 9 10 12 13 14 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 (24) 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 (11) 12 13 14 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 (22) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 (19) 22 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 (15) 19 22 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 15 (17) 19 22 ]

virgosun · November 23, 2016

Here is the AppleIntel info for those who were interested:

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1

Warning: Clover hw.busfrequency error detected : 17d78400
InitialTSC...............................: 0x219252c525 (6 MHz)
MWAIT C-States...........................: 135456

Processor Brandstring....................:       Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz

Processor Signature..................... : 0x306A9
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 9
 - Model................................ : 0x3A (58)

Model Specific Registers (MSRs)
------------------------------------------

MSR_CORE_THREAD_COUNT............(0x35)  : 0xFFFFFF8023A8FA00
------------------------------------------
 - Core Count........................... : 4
 - Thread Count......................... : 8

MSR_PLATFORM_INFO................(0xCE)  : 0x80C10E0011800
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x18 (2400 MHz)
 - Ratio Limit for Turbo Mode........... : 0 (not programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 0 (LMP not supported)
 - Number of ConfigTDP Levels........... : 0 (only base TDP level available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x405
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 0 (disabled/unsupported)
 - C1 State Auto Demotion............... : 0 (disabled/unsupported)
 - C3 State Undemotion.................. : 0 (disabled/unsupported)
 - C1 State Undemotion.................. : 0 (disabled/unsupported)
 - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
 - Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x20414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 2 (C7 is the max C-State to include)

IA32_MPERF.......................(0xE7)  : 0x13485D9459
IA32_APERF.......................(0xE8)  : 0xFABB94C40

MSR_FLEX_RATIO...................(0x194) : 0x100000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x245900002000
------------------------------------------
 - Current Performance State Value...... : 0x2000 (3200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0x2100
------------------------------------------
 - Target performance State Value....... : 0x2100 (3300 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0
IA32_THERM_STATUS................(0x19C) : 0x88270808

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Performance Monitoring............... : 1 (available)
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - CFG Lock............................. : 0 (MSR not locked)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x691200
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 105
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400001
------------------------------------------
 - EIST Hardware Coordination........... : 1 (hardware coordination disabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x20202122
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 22 (3400 MHz) 
 - Maximum Ratio Limit for C02.......... : 21 (3300 MHz) 
 - Maximum Ratio Limit for C03.......... : 20 (3200 MHz) 
 - Maximum Ratio Limit for C04.......... : 20 (3200 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x4
------------------------------------------

MSR_POWER_CTL....................(0x1FC) : 0x14005F
------------------------------------------
 - C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA1003
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 16 (15.3 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x800081C2001E8168
------------------------------------------
 - Package Power Limit #1............... : 45 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 0 (disabled)
 - Time Window for Power Limit #1....... : 15 (81920 milli-Seconds)
 - Package Power Limit #2............... : 56 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 0 (disabled)
 - Time Window for Power Limit #2....... : 0 (2 milli-Seconds)
 - Lock................................. : 1 (MSR locked until next reset)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x39A3696
------------------------------------------
 - Total Energy Consumed................ : 922 Joules (Watt = Joules / seconds)

MSR_PKG_POWER_INFO...............(0x614) : 0x10000001200168
------------------------------------------
 - Thermal Spec Power................... : 45 Watt
 - Minimum Power........................ : 0
 - Maximum Power........................ : 0
 - Maximum Time Window.................. : 0

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x2D7331E
------------------------------------------
 - Total Energy Consumed................ : 727 Joules (Watt = Joules / seconds)

MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0
MSR_PP1_CURRENT_CONFIG...........(0x602) : 0x1814149480000170

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0x6CB24
------------------------------------------
 - Total Energy Consumed................ : 6 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x10
------------------------------------------
 - Priority Level....................... : 16

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x18
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x120000000000000
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x120000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x80000000
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x883B
MSR_PKGC6_IRTL...................(0x60b) : 0x8850
MSR_PKGC7_IRTL...................(0x60c) : 0x8857
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x183E700
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x2C62F8
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0x14EB8268

IA32_TSC_DEADLINE................(0x6E0) : 0x21959A8A3D

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 24 (2400 MHz)
Maximum Turbo Ratio/Frequency............: 34 (3400 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:  350 MHz
IGPU Minimum Frequency...................:  350 MHz
IGPU Maximum Non-Turbo Frequency.........:  650 MHz
IGPU Maximum Turbo Frequency.............: 1150 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ 21 32 (33) ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 3 4 5 ]
CPU C6-Cores [ 2 6 7 ]
CPU C7-Cores [ 0 1 6 7 ]
CPU P-States [ 21 (32) 33 34 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 3 4 5 7 ]
CPU C6-Cores [ 2 3 6 7 ]
CPU C7-Cores [ 0 1 2 4 5 6 7 ]
CPU C3-Cores [ 0 1 3 4 5 6 7 ]
CPU P-States [ (12) 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 17 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU C7-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 17 18 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 17 18 19 21 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 17 18 19 21 (22) 28 32 33 34 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 16 17 18 19 21 22 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 16 17 18 19 21 22 24 28 (32) 33 34 ] iGPU P-States [ (7) ]
CPU C6-Cores [ 2 3 4 5 6 7 ]
CPU P-States [ 12 16 17 18 19 21 22 24 25 28 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 16 17 18 19 21 22 24 25 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 16 17 18 19 20 21 22 24 25 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 16 17 18 19 20 21 22 24 25 26 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 (32) 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 (9) ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 (23) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ (7) 9 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 (22) 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 (30) 31 32 33 34 ] iGPU P-States [ 7 9 (20) 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 (30) 31 32 33 34 ] iGPU P-States [ 7 9 (19) 20 22 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 9 (12) 19 20 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 (10) 12 19 20 22 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 (8) 9 10 12 19 20 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 12 (18) 19 20 22 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 (11) 12 18 19 20 22 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 (13) 18 19 20 22 23 ]

EDIT: I set QPI = 100 in Clover to get rid of the Warning "Clover hw.busfrequency error detected : 17d78400" and now I got this:

AppleIntelInfo.kext v1.8e Copyright © 2012-2016 Pike R. Alpha. All rights reserved

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1
InitialTSC...............................: 0x3328d5c194 (9 MHz)
MWAIT C-States...........................: 135456

Processor Brandstring....................:       Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz

Processor Signature..................... : 0x306A9
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 9
 - Model................................ : 0x3A (58)

Model Specific Registers (MSRs)
------------------------------------------

MSR_CORE_THREAD_COUNT............(0x35)  : 0xFFFFFF8044E4DA00
------------------------------------------
 - Core Count........................... : 4
 - Thread Count......................... : 8

MSR_PLATFORM_INFO................(0xCE)  : 0x80C10E0011800
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x18 (2400 MHz)
 - Ratio Limit for Turbo Mode........... : 0 (not programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 0 (LMP not supported)
 - Number of ConfigTDP Levels........... : 0 (only base TDP level available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x405
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 0 (disabled/unsupported)
 - C1 State Auto Demotion............... : 0 (disabled/unsupported)
 - C3 State Undemotion.................. : 0 (disabled/unsupported)
 - C1 State Undemotion.................. : 0 (disabled/unsupported)
 - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
 - Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x20414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 2 (C7 is the max C-State to include)

IA32_MPERF.......................(0xE7)  : 0x179B53089B
IA32_APERF.......................(0xE8)  : 0x1168BD6E1A

MSR_FLEX_RATIO...................(0x194) : 0x100000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x233A00002000
------------------------------------------
 - Current Performance State Value...... : 0x2000 (3200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0x2200
------------------------------------------
 - Target performance State Value....... : 0x2200 (3400 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0
IA32_THERM_STATUS................(0x19C) : 0x882F0808

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Performance Monitoring............... : 1 (available)
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - CFG Lock............................. : 0 (MSR not locked)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x691200
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 105
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400001
------------------------------------------
 - EIST Hardware Coordination........... : 1 (hardware coordination disabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x20202122
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 22 (3400 MHz) 
 - Maximum Ratio Limit for C02.......... : 21 (3300 MHz) 
 - Maximum Ratio Limit for C03.......... : 20 (3200 MHz) 
 - Maximum Ratio Limit for C04.......... : 20 (3200 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x4
------------------------------------------

MSR_POWER_CTL....................(0x1FC) : 0x14005F
------------------------------------------
 - C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA1003
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 16 (15.3 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x800081C2001E8168
------------------------------------------
 - Package Power Limit #1............... : 45 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 0 (disabled)
 - Time Window for Power Limit #1....... : 15 (81920 milli-Seconds)
 - Package Power Limit #2............... : 56 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 0 (disabled)
 - Time Window for Power Limit #2....... : 0 (2 milli-Seconds)
 - Lock................................. : 1 (MSR locked until next reset)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x42B6A8C
------------------------------------------
 - Total Energy Consumed................ : 1067 Joules (Watt = Joules / seconds)

MSR_PKG_POWER_INFO...............(0x614) : 0x10000001200168
------------------------------------------
 - Thermal Spec Power................... : 45 Watt
 - Minimum Power........................ : 0
 - Maximum Power........................ : 0
 - Maximum Time Window.................. : 0

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x3089806
------------------------------------------
 - Total Energy Consumed................ : 776 Joules (Watt = Joules / seconds)

MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0
MSR_PP1_CURRENT_CONFIG...........(0x602) : 0x1814149480000170

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0x73A74
------------------------------------------
 - Total Energy Consumed................ : 7 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x10
------------------------------------------
 - Priority Level....................... : 16

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x18
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x120000000000000
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x120000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x80000000
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x883B
MSR_PKGC6_IRTL...................(0x60b) : 0x8850
MSR_PKGC7_IRTL...................(0x60c) : 0x8857
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x222B62F8
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x7BDBF18
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0xC276DCF38

IA32_TSC_DEADLINE................(0x6E0) : 0x332CBA428E

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 24 (2400 MHz)
Maximum Turbo Ratio/Frequency............: 34 (3400 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:  350 MHz
IGPU Minimum Frequency...................:  350 MHz
IGPU Maximum Non-Turbo Frequency.........:  650 MHz
IGPU Maximum Turbo Frequency.............: 1150 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ (12) 19 22 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 4 5 ]
CPU C6-Cores [ 0 1 3 4 6 ]
CPU C7-Cores [ 2 3 4 6 ]
CPU P-States [ (12) 17 19 22 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 ]
CPU C6-Cores [ 0 1 2 3 4 6 ]
CPU C7-Cores [ 0 1 2 3 4 6 7 ]
CPU P-States [ (12) 15 17 19 22 ] iGPU P-States [ (7) ]
CPU C6-Cores [ 0 1 2 3 4 5 6 ]
CPU P-States [ 12 15 17 19 22 (30) ] iGPU P-States [ (7) ]
CPU P-States [ 12 15 17 19 22 30 (32) ] iGPU P-States [ (7) ]
CPU C7-Cores [ 0 1 2 3 4 5 6 7 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 15 17 19 22 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 15 17 19 21 22 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 17 19 21 22 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 17 19 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 17 18 19 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 13 15 16 17 18 19 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 15 16 17 18 19 20 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 30 32 ] iGPU P-States [ (7) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 30 32 (33) ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 29 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 (29) 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 ] iGPU P-States [ (7) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (33) ] iGPU P-States [ (7) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 (12) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 (9) 12 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 9 (11) 12 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 (8) 9 11 12 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 8 9 (10) 11 12 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 8 9 10 11 12 (15) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 (21) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 21 (23) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 (20) 21 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 15 (16) 20 21 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 8 9 10 11 12 (13) 15 16 20 21 23 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ] iGPU P-States [ 7 8 9 10 11 12 13 (14) 15 16 20 21 23 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (31) 32 33 ] iGPU P-States [ 7 8 9 10 11 12 13 14 15 16 (18) 20 21 23 ]

Edit 2: With QPI = 100 it seems I can't get the x34 multiplier. I made may tests it always stops at x33.

I tried to remove Drop OEM and nothing changed, BDMESG shows this behavior:

3:311  0:000  === [ ACPIDropTables ] ====================================
3:311  0:000  === [ PatchAllSSDT ] ======================================
3:311  0:000  Patch table: SSDT  AhciTab1
3:311  0:000   SSDT len = 0x590
3:311  0:000  Patch table: SSDT  AhciTab2
3:311  0:000   SSDT len = 0x49E
3:311  0:000  Patch table: SSDT  Cpu0Ist
3:311  0:000   SSDT len = 0x94C
3:311  0:000  Patch table: SSDT  CpuPm
3:311  0:000   SSDT len = 0xB18
3:311  0:000  Drop tables from Xsdt, SIGN=XXXX TableID= Length=0
3:311  0:000   Xsdt has tables count=11
3:311  0:000  corrected XSDT length=124
3:311  0:000  === [ ACPIPatchedAML ] ====================================
3:311  0:000  Start: Processing Patched AML(s): Unsorted
3:311  0:000  Inserting SSDT.AML from EFI\CLOVER\ACPI\patched ... Success
3:312  0:001  End: Processing Patched AML(s)
3:312  0:000  CPUBase=0 and ApicCPUBase=1 ApicCPUNum=8

It seems to me it first patches the ACPI tables including Cpu0Ist then it inserts the SSDT.aml which AFAIK should replace that table.

Here are the two ssdt I am using to test:

This one is an old generated one:

/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20160422-64(RM)
 * Copyright (c) 2000 - 2016 Intel Corporation
 * 
 * Disassembling to non-symbolic legacy ASL operators
 *
 * Disassembly of iASLiyekUv.aml, Tue Oct 18 12:35:43 2016
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x0000083E (2110)
 *     Revision         0x01
 *     Checksum         0x72
 *     OEM ID           "APPLE "
 *     OEM Table ID     "CpuPm"
 *     OEM Revision     0x00015600 (87552)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20100331 (537920305)
 */
DefinitionBlock ("", "SSDT", 1, "APPLE ", "CpuPm", 0x00015600)
{
    External (_PR_.CPU0, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU1, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU2, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU3, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU4, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU5, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU6, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU7, DeviceObj)    // Warning: Unknown object

    Scope (\_PR.CPU0)
    {
        Method (_INI, 0, NotSerialized)  // _INI: Initialize
        {
            Store ("ssdtPRGen version....: 15.6 / Mac OS X 10.10.2 (14C109)", Debug)
            Store ("target processor.....: i7-3630QM", Debug)
            Store ("running processor....: Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz", Debug)
            Store ("baseFrequency........: 1200", Debug)
            Store ("frequency............: 2400", Debug)
            Store ("busFrequency.........: 100", Debug)
            Store ("logicalCPUs..........: 8", Debug)
            Store ("maximum TDP..........: 45", Debug)
            Store ("packageLength........: 23", Debug)
            Store ("turboStates..........: 10", Debug)
            Store ("maxTurboFrequency....: 3400", Debug)
            Store ("IvyWorkArounds.......: 3", Debug)
            Store ("machdep.xcpm.mode....: 0", Debug)
        }

        Name (APLF, 0x04)
        Name (APSN, 0x0B)
        Name (APSS, Package (0x1C)
        {
            Package (0x06)
            {
                0x0D49, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2300, 
                0x2300
            }, 

            Package (0x06)
            {
                0x0D48, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2200, 
                0x2200
            }, 

            Package (0x06)
            {
                0x0CE4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2100, 
                0x2100
            }, 

            Package (0x06)
            {
                0x0C80, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2000, 
                0x2000
            }, 

            Package (0x06)
            {
                0x0C1C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1F00, 
                0x1F00
            }, 

            Package (0x06)
            {
                0x0BB8, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1E00, 
                0x1E00
            }, 

            Package (0x06)
            {
                0x0B54, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1D00, 
                0x1D00
            }, 

            Package (0x06)
            {
                0x0AF0, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1C00, 
                0x1C00
            }, 

            Package (0x06)
            {
                0x0A8C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1B00, 
                0x1B00
            }, 

            Package (0x06)
            {
                0x0A28, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1A00, 
                0x1A00
            }, 

            Package (0x06)
            {
                0x09C4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1900, 
                0x1900
            }, 

            Package (0x06)
            {
                0x0960, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1800, 
                0x1800
            }, 

            Package (0x06)
            {
                0x08FC, 
                0xA68C, 
                0x0A, 
                0x0A, 
                0x1700, 
                0x1700
            }, 

            Package (0x06)
            {
                0x0898, 
                0x9D7D, 
                0x0A, 
                0x0A, 
                0x1600, 
                0x1600
            }, 

            Package (0x06)
            {
                0x0834, 
                0x949C, 
                0x0A, 
                0x0A, 
                0x1500, 
                0x1500
            }, 

            Package (0x06)
            {
                0x07D0, 
                0x8BE6, 
                0x0A, 
                0x0A, 
                0x1400, 
                0x1400
            }, 

            Package (0x06)
            {
                0x076C, 
                0x835D, 
                0x0A, 
                0x0A, 
                0x1300, 
                0x1300
            }, 

            Package (0x06)
            {
                0x0708, 
                0x7B00, 
                0x0A, 
                0x0A, 
                0x1200, 
                0x1200
            }, 

            Package (0x06)
            {
                0x06A4, 
                0x72CD, 
                0x0A, 
                0x0A, 
                0x1100, 
                0x1100
            }, 

            Package (0x06)
            {
                0x0640, 
                0x6AC6, 
                0x0A, 
                0x0A, 
                0x1000, 
                0x1000
            }, 

            Package (0x06)
            {
                0x05DC, 
                0x62EA, 
                0x0A, 
                0x0A, 
                0x0F00, 
                0x0F00
            }, 

            Package (0x06)
            {
                0x0578, 
                0x5B37, 
                0x0A, 
                0x0A, 
                0x0E00, 
                0x0E00
            }, 

            Package (0x06)
            {
                0x0514, 
                0x53AF, 
                0x0A, 
                0x0A, 
                0x0D00, 
                0x0D00
            }, 

            Package (0x06)
            {
                0x04B0, 
                0x4C50, 
                0x0A, 
                0x0A, 
                0x0C00, 
                0x0C00
            }, 

            Package (0x06)
            {
                0x044C, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0B00, 
                0x0B00
            }, 

            Package (0x06)
            {
                0x03E8, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0A00, 
                0x0A00
            }, 

            Package (0x06)
            {
                0x0384, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0900, 
                0x0900
            }, 

            Package (0x06)
            {
                0x0320, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0800, 
                0x0800
            }
        })
        Method (ACST, 0, NotSerialized)
        {
            Store ("Method CPU0.ACST Called", Debug)
            Store ("CPU0 C-States    : 29", Debug)
            Return (Package (0x06)
            {
                One, 
                0x04, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    Zero, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xCD, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000020, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x06, 
                    0xF5, 
                    0x015E
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x07, 
                    0xF5, 
                    0xC8
                }
            })
        }

        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
        {
            Store ("Method CPU0._DSM Called", Debug)
            If (LEqual (Arg2, Zero))
            {
                Return (Buffer (One)
                {
                     0x03                                           
                })
            }

            Return (Package (0x02)
            {
                "plugin-type", 
                One
            })
        }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU1.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method CPU1.ACST Called", Debug)
            Store ("CPU1 C-States    : 7", Debug)
            Return (Package (0x05)
            {
                One, 
                0x03, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    0x03E8, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x02, 
                    0x94, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xC6, 
                    0xC8
                }
            })
        }
    }

    Scope (\_PR.CPU2)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU2.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU3)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU3.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU4)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU4.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU5)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU5.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU6)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU6.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU7)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU7.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }
}

Anf this the one that ssdtPRGen creates with latest release:

/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20160422-64(RM)
 * Copyright (c) 2000 - 2016 Intel Corporation
 * 
 * Disassembling to non-symbolic legacy ASL operators
 *
 * Disassembly of iASLGCB1n6.aml, Tue Oct 18 12:36:43 2016
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x00000875 (2165)
 *     Revision         0x01
 *     Checksum         0x6A
 *     OEM ID           "APPLE "
 *     OEM Table ID     "CpuPm"
 *     OEM Revision     0x00020500 (132352)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20140926 (538183974)
 */
DefinitionBlock ("", "SSDT", 1, "APPLE ", "CpuPm", 0x00020500)
{
    External (_PR_.CPU0, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU1, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU2, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU3, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU4, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU5, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU6, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU7, DeviceObj)    // Warning: Unknown object

    Scope (\_PR.CPU0)
    {
        Method (_INI, 0, NotSerialized)  // _INI: Initialize
        {
            Store ("ssdtPRGen version.....: 20.5 / Mac OS X 10.12 (16A323)", Debug)
            Store ("custom mode...........: 0", Debug)
            Store ("host processor........: Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz", Debug)
            Store ("target processor......: i7-3630QM", Debug)
            Store ("number of processors..: 1", Debug)
            Store ("baseFrequency.........: 1200", Debug)
            Store ("frequency.............: 2400", Debug)
            Store ("busFrequency..........: 100", Debug)
            Store ("logicalCPUs...........: 8", Debug)
            Store ("maximum TDP...........: 45", Debug)
            Store ("packageLength.........: 23", Debug)
            Store ("turboStates...........: 10", Debug)
            Store ("maxTurboFrequency.....: 3400", Debug)
            Store ("CPU Workarounds.......: 2", Debug)
        }

        Name (APLF, 0x05)
        Name (APSN, 0x0A)
        Name (APSS, Package (0x1C)
        {
            Package (0x06)
            {
                0x0D48, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2200, 
                0x2200
            }, 

            Package (0x06)
            {
                0x0CE4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2100, 
                0x2100
            }, 

            Package (0x06)
            {
                0x0C80, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x2000, 
                0x2000
            }, 

            Package (0x06)
            {
                0x0C1C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1F00, 
                0x1F00
            }, 

            Package (0x06)
            {
                0x0BB8, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1E00, 
                0x1E00
            }, 

            Package (0x06)
            {
                0x0B54, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1D00, 
                0x1D00
            }, 

            Package (0x06)
            {
                0x0AF0, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1C00, 
                0x1C00
            }, 

            Package (0x06)
            {
                0x0A8C, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1B00, 
                0x1B00
            }, 

            Package (0x06)
            {
                0x0A28, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1A00, 
                0x1A00
            }, 

            Package (0x06)
            {
                0x09C4, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1900, 
                0x1900
            }, 

            Package (0x06)
            {
                0x0960, 
                0xAFC8, 
                0x0A, 
                0x0A, 
                0x1800, 
                0x1800
            }, 

            Package (0x06)
            {
                0x08FC, 
                0xA68C, 
                0x0A, 
                0x0A, 
                0x1700, 
                0x1700
            }, 

            Package (0x06)
            {
                0x0898, 
                0x9D7D, 
                0x0A, 
                0x0A, 
                0x1600, 
                0x1600
            }, 

            Package (0x06)
            {
                0x0834, 
                0x949C, 
                0x0A, 
                0x0A, 
                0x1500, 
                0x1500
            }, 

            Package (0x06)
            {
                0x07D0, 
                0x8BE6, 
                0x0A, 
                0x0A, 
                0x1400, 
                0x1400
            }, 

            Package (0x06)
            {
                0x076C, 
                0x835D, 
                0x0A, 
                0x0A, 
                0x1300, 
                0x1300
            }, 

            Package (0x06)
            {
                0x0708, 
                0x7B00, 
                0x0A, 
                0x0A, 
                0x1200, 
                0x1200
            }, 

            Package (0x06)
            {
                0x06A4, 
                0x72CD, 
                0x0A, 
                0x0A, 
                0x1100, 
                0x1100
            }, 

            Package (0x06)
            {
                0x0640, 
                0x6AC6, 
                0x0A, 
                0x0A, 
                0x1000, 
                0x1000
            }, 

            Package (0x06)
            {
                0x05DC, 
                0x62EA, 
                0x0A, 
                0x0A, 
                0x0F00, 
                0x0F00
            }, 

            Package (0x06)
            {
                0x0578, 
                0x5B37, 
                0x0A, 
                0x0A, 
                0x0E00, 
                0x0E00
            }, 

            Package (0x06)
            {
                0x0514, 
                0x53AF, 
                0x0A, 
                0x0A, 
                0x0D00, 
                0x0D00
            }, 

            Package (0x06)
            {
                0x04B0, 
                0x4C50, 
                0x0A, 
                0x0A, 
                0x0C00, 
                0x0C00
            }, 

            Package (0x06)
            {
                0x044C, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0B00, 
                0x0B00
            }, 

            Package (0x06)
            {
                0x03E8, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0A00, 
                0x0A00
            }, 

            Package (0x06)
            {
                0x0384, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0900, 
                0x0900
            }, 

            Package (0x06)
            {
                0x0320, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0800, 
                0x0800
            }, 

            Package (0x06)
            {
                0x02BC, 
                Zero, 
                0x0A, 
                0x0A, 
                0x0700, 
                0x0700
            }
        })
        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU0.ACST Called", Debug)
            Store ("CPU0 C-States    : 29", Debug)
            Return (Package (0x06)
            {
                One, 
                0x04, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    Zero, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xCD, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000020, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x06, 
                    0xF5, 
                    0x015E
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x07, 
                    0xF5, 
                    0xC8
                }
            })
        }

        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
        {
            Store ("Method _PR_.CPU0._DSM Called", Debug)
            If (LEqual (Arg2, Zero))
            {
                Return (Buffer (One)
                {
                     0x03                                           
                })
            }

            Return (Package (0x02)
            {
                "plugin-type", 
                One
            })
        }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU1.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU1.ACST Called", Debug)
            Store ("CPU1 C-States    : 7", Debug)
            Return (Package (0x05)
            {
                One, 
                0x03, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    0x03E8, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x02, 
                    0x94, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    }, 

                    0x03, 
                    0xC6, 
                    0xC8
                }
            })
        }
    }

    Scope (\_PR.CPU2)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU2.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU3)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU3.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU4)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU4.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU5)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU5.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU6)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU6.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }

    Scope (\_PR.CPU7)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR_.CPU7.APSS Called", Debug)
            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Return (\_PR.CPU1.ACST ())
        }
    }
}

By the way, HWmon from time to time shows insane multiplier data for single cores like x152 or similar.

Edit 3: After removing Drop OEM the x34 multiplier showed up again, this with the newly generated SSDT:

CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) ] iGPU P-States [ (7) 9 10 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 9 10 (12) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 10 12 13 (14) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 (8) 9 10 12 13 14 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 (24) 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 (11) 12 13 14 ]

Full report:

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1
InitialTSC...............................: 0x390e69e8f8 (10 MHz)
MWAIT C-States...........................: 135456

Processor Brandstring....................:       Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz

Processor Signature..................... : 0x306A9
------------------------------------------
 - Family............................... : 6
 - Stepping............................. : 9
 - Model................................ : 0x3A (58)

Model Specific Registers (MSRs)
------------------------------------------

MSR_CORE_THREAD_COUNT............(0x35)  : 0xFFFFFF805337B500
------------------------------------------
 - Core Count........................... : 4
 - Thread Count......................... : 8

MSR_PLATFORM_INFO................(0xCE)  : 0x80C10E0011800
------------------------------------------
 - Maximum Non-Turbo Ratio.............. : 0x18 (2400 MHz)
 - Ratio Limit for Turbo Mode........... : 0 (not programmable)
 - TDP Limit for Turbo Mode............. : 1 (programmable)
 - Low Power Mode Support............... : 0 (LMP not supported)
 - Number of ConfigTDP Levels........... : 0 (only base TDP level available)
 - Maximum Efficiency Ratio............. : 12
 - Minimum Operating Ratio.............. : 8

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x405
------------------------------------------
 - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
 - CFG Lock............................. : 0 (MSR not locked)
 - C3 State Auto Demotion............... : 0 (disabled/unsupported)
 - C1 State Auto Demotion............... : 0 (disabled/unsupported)
 - C3 State Undemotion.................. : 0 (disabled/unsupported)
 - C1 State Undemotion.................. : 0 (disabled/unsupported)
 - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
 - Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x20414
------------------------------------------
 - LVL_2 Base Address................... : 0x414
 - C-state Range........................ : 2 (C7 is the max C-State to include)

IA32_MPERF.......................(0xE7)  : 0x2FA50A3DDD
IA32_APERF.......................(0xE8)  : 0x1C8AC2206A

MSR_FLEX_RATIO...................(0x194) : 0x100000
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x1A1900000C00
------------------------------------------
 - Current Performance State Value...... : 0xC00 (1200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0x2000
------------------------------------------
 - Target performance State Value....... : 0x2000 (3200 MHz)
 - Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0
IA32_THERM_STATUS................(0x19C) : 0x882C080C

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
 - Fast-Strings......................... : 1 (enabled)
 - Automatic Thermal Control Circuit.... : 1 (enabled)
 - Performance Monitoring............... : 1 (available)
 - Processor Event Based Sampling....... : 0 (PEBS supported)
 - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
 - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
 - CFG Lock............................. : 0 (MSR not locked)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x691200
------------------------------------------
 - Turbo Attenuation Units.............. : 0 
 - Temperature Target................... : 105
 - TCC Activation Offset................ : 0

MSR_MISC_PWR_MGMT................(0x1AA) : 0x400001
------------------------------------------
 - EIST Hardware Coordination........... : 1 (hardware coordination disabled)
 - Energy/Performance Bias support...... : 1
 - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
 - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x20202122
------------------------------------------
 - Maximum Ratio Limit for C01.......... : 22 (3400 MHz) 
 - Maximum Ratio Limit for C02.......... : 21 (3300 MHz) 
 - Maximum Ratio Limit for C03.......... : 20 (3200 MHz) 
 - Maximum Ratio Limit for C04.......... : 20 (3200 MHz) 

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x4
------------------------------------------

MSR_POWER_CTL....................(0x1FC) : 0x14005F
------------------------------------------
 - C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA1003
------------------------------------------
 - Power Units.......................... : 3 (1/8 Watt)
 - Energy Status Units.................. : 16 (15.3 micro-Joules)
 - Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x800081C2001E8168
------------------------------------------
 - Package Power Limit #1............... : 45 Watt
 - Enable Power Limit #1................ : 1 (enabled)
 - Package Clamping Limitation #1....... : 0 (disabled)
 - Time Window for Power Limit #1....... : 15 (81920 milli-Seconds)
 - Package Power Limit #2............... : 56 Watt
 - Enable Power Limit #2................ : 1 (enabled)
 - Package Clamping Limitation #2....... : 0 (disabled)
 - Time Window for Power Limit #2....... : 0 (2 milli-Seconds)
 - Lock................................. : 1 (MSR locked until next reset)

MSR_PKG_ENERGY_STATUS............(0x611) : 0x55A25CA
------------------------------------------
 - Total Energy Consumed................ : 1370 Joules (Watt = Joules / seconds)

MSR_PKG_POWER_INFO...............(0x614) : 0x10000001200168
------------------------------------------
 - Thermal Spec Power................... : 45 Watt
 - Minimum Power........................ : 0
 - Maximum Power........................ : 0
 - Maximum Time Window.................. : 0

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x40D0DEA
------------------------------------------
 - Total Energy Consumed................ : 1037 Joules (Watt = Joules / seconds)

MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0
MSR_PP1_CURRENT_CONFIG...........(0x602) : 0x1814149480000170

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0xB6214
------------------------------------------
 - Total Energy Consumed................ : 11 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x10
------------------------------------------
 - Priority Level....................... : 16

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x18
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x120000000000000
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x120000000000000
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x80000000
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x883B
MSR_PKGC6_IRTL...................(0x60b) : 0x8850
MSR_PKGC7_IRTL...................(0x60c) : 0x8857
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x9802B0
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x3584E8
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0xCA2A338

IA32_TSC_DEADLINE................(0x6E0) : 0x3912996722

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 24 (2400 MHz)
Maximum Turbo Ratio/Frequency............: 34 (3400 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:  350 MHz
IGPU Minimum Frequency...................:  350 MHz
IGPU Maximum Non-Turbo Frequency.........:  650 MHz
IGPU Maximum Turbo Frequency.............: 1150 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ 12 14 (32) ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 2 5 6 7 ]
CPU C6-Cores [ 3 4 5 ]
CPU C7-Cores [ 1 3 4 6 ]
CPU C3-Cores [ 0 2 3 4 5 6 7 ]
CPU C6-Cores [ 2 3 4 5 ]
CPU C7-Cores [ 0 1 2 3 4 6 7 ]
CPU P-States [ 12 14 31 (32) ] iGPU P-States [ (7) ]
CPU C7-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 14 29 31 32 ] iGPU P-States [ (7) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (12) 14 15 29 31 32 ] iGPU P-States [ (7) ]
CPU P-States [ (12) 14 15 20 29 31 32 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 20 (24) 29 31 32 ] iGPU P-States [ (7) ]
CPU P-States [ 12 14 15 19 20 24 29 (30) 31 32 ] iGPU P-States [ 7 (13) ]
CPU P-States [ (12) 14 15 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 14 15 16 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 18 19 20 22 24 29 30 31 32 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 18 19 20 22 24 29 30 31 32 (33) ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 22 24 29 30 31 (32) 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 22 23 24 29 30 31 (32) 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 22 23 24 27 29 30 31 32 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 22 23 24 25 27 29 30 31 (32) 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 27 29 30 31 32 33 ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 (33) ] iGPU P-States [ (7) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (26) 27 28 29 30 31 32 33 ] iGPU P-States [ (7) 13 ]
CPU C6-Cores [ 0 1 2 3 4 5 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 (9) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 ] iGPU P-States [ 7 9 (10) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) ] iGPU P-States [ (7) 9 10 13 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 9 10 (12) 13 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 9 10 12 13 (14) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 (8) 9 10 12 13 14 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 (24) 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 (11) 12 13 14 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 (22) ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 (19) 22 ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 (15) 19 22 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) 33 34 ] iGPU P-States [ 7 8 9 10 11 12 13 14 15 (17) 19 22 ]

Me too ssdtPRGen not work for Ivi Bridge in Sierra, no thing change. I have a guy at other forum editing the ssdt and it works

Do we really need an SSDT for the CPU nowadays?

Recommended Posts

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites