DSDT for Asus P8P67-M PRO

flAked · May 30, 2011

APSN apparently is not the number of Turbo States, but the number of P-States. What about that. Can that be it?

If I set APSN to 0x13 I get

kernel[0]: P-State Stepper Error 18 at step 41 on CPU 2

Can you post the SSDT_PR that worked?

Time2Retire · May 30, 2011

If I set APSN to 0x13 I get

That's because you don't have 19 but 18 on your i5 (1600-3300). And use all (P-States) of them.

Can you post the SSDT_PR that worked?

Of course, but I'm not on my hack right now. Will do this later today. Need a few hours of sleep first.

flAked · May 30, 2011

I have 15 normal P-States (0x0F) and 4 Turbo-States = 19 States (0x13).

Setting APSN to 0x13 results in the above error, but setting it to 0x0F works.

I can confirm, that for the first time, I'm seeing 20x and 21x multipliers. The midrange between 22-33 is rarely covered however, so I'm gonna extend MSRDumper with some profiling.

But let's try setting APSN to 16 (0x10) first and see if that will trigger the error as I would expect.

Hmm, no. I can set APSN to 16, 17, 18 without errors.

Setting it it 19 will again result in:

May 30 12:36:15 slAve kernel[0]: P-State Stepper Error 18 at step 41 on CPU 3

I'm not sure what's going on because if I decrement APSN from 19 to 18 I would suspect an error on "step 40", which isn't defined either. But there is no error.

--------------------------------------------

About the MSR issue, I found this on the mailing list: http://lists.apple.com/archives/darwin-ker...c/msg00006.html

But before doing a crazy thread implementation, let's see what we have.

1) we know that mp_rendezvous_no_intrs() is being called on every logical core, because cpu_number() reflects that

2) for the unique IA32_THERM_STATUS MSR we see:

May 30 14:39:20 slave kernel[0]: MSRDumper(@35) CoreTemps: 50	57	60	56	
May 30 14:39:21 slave kernel[0]: MSRDumper(@35) CoreTemps: 57	58	61	57	
May 30 14:39:21 slave kernel[0]: MSRDumper(@35) CoreTemps: 56	58	59	48	
May 30 14:39:22 slave kernel[0]: MSRDumper(@35) CoreTemps: 47	52	50	44	
May 30 14:39:22 slave kernel[0]: MSRDumper(@16) CoreTemps: 46	46	46	46

Telling us that this MSR in fact retrieved from every core independently.

Now, let's have some fun in Linux, using the msr kernel module, the msr-tools and this simple bash-script:

#!/bin/bash

while [ true ]
do
	A=`./rdmsr -p0 -f 16:8 0x198`
	B=`./rdmsr -p1 -f 16:8 0x198`
	C=`./rdmsr -p2 -f 16:8 0x198`
	D=`./rdmsr -p3 -f 16:8 0x198`

	printf "multi: %d %d %d %d\n" $A $B $C $D
	sleep 1
done

This will give me (ondemand governor):

multi: 26 26 27 24
multi: 24 24 24 23
multi: 26 26 26 23
multi: 26 26 26 24
multi: 26 26 24 23
multi: 26 24 24 24
multi: 24 24 23 24
multi: 23 24 24 24
multi: 26 26 24 23
multi: 24 10 10 26
multi: 24 24 24 24

Clearly showing that MSR 0x198 is unique to every logical core.

Time2Retire · May 30, 2011

...

Now, let's have some fun in Linux, using the msr kernel module, the msr-tools and this simple bash-script...

This will give me (ondemand governor)...

Clearly showing that MSR 0x198 is unique to every logical core.

Right. Just like I though it should be – and why I didn't remove the per-core readout code. First confirmed by your Windows screenies and now by your script in Linux. And long before that by several threads here.

The one remaining question, one that has yet to be answered is; What sets this MSR?

I have an idea. Look at this snippet found in CPUi.h:

if (GlobalThrottle[i]) 
{
	DebugLog("Writing control: %d", GlobalThrottle[i]);

	wrmsr64(MSR_IA32_PERF_CTL, msr | GlobalThrottle[i]);
	IntelWaitForSts();
}

And this one by Intel:

if (TargetPstate != currentPstate) { 
SetPState(TargetPstate);
}

Note: See Example 14-1. "Determine Target P-state From Hardware Coordinated Feedback" in Volume 3A: System Programming Guide, Part 1.

Does this mean that we have to do this our selfs? This would explain as to why it isn't set right now. Knowing that both Microsoft and Linux engineers read this kind of documentation, but why don't we check this in the (Linux) source code?

p.s. The problem I had with not seeing P-State changes was a broken DSDT.

Tip: Check your kernel_task in Activity Monitor. Should be a low percentage. I had 50-60% when idle and a low Geekbench score (now back @13K non OC'ed) and that was caused by an IRQ conflict in the ARnn sections of my DSDT.

Still no bit-5 set (unsurprisingly) but I know now that it is hardware coordinated on Sandy Bridge processors, and that PM works differently on CPU's with Hyper Threading.

flAked · May 30, 2011

Does this mean that we have to do this our selfs? This would explain as to why it isn't set right now. Knowing that both Microsoft and Linux engineers read this kind of documentation, but why don't we check this in the (Linux) source code?

But why define PERF_CTL per thread and PERF_STATUS per package?

IA32_PERF_STATUS is RO and set by the CPU, so we are only seeing the effects of IA32_PERF_CTL being used.

That must mean that AICPUPM is using PERF_CTL to set the exact same P-State on every core.

Wether this is intentional or due to a bit we are missing, we must find out.

The code from CPUi is about something different, CPUi is actually enabling clock modulation.

I also did a read-out of bits 47:32 of PERF_STATUS (Core Voltage on SNB), they are the same as well.

Tip: Check your kernel_task in Activity Monitor. Should be a low percentage. I had 50-60% when idle, and that was caused by an IRQ conflict in the ARnn sections of my DSDT.

Thanks, everything looking good there.

Time2Retire · May 30, 2011

But why define PERF_CTL per thread and PERF_STATUS per package?

IA32_PERF_STATUS is RO and set by the CPU, so we are only seeing the effects of IA32_PERF_CTL being used.

That must mean that AICPUPM is using PERF_CTL to set the exact same P-State on every core.

You could verify this by nop'ing the two write actions to 0x199 in AICPUPM. That should tell you if this is the case. And when the stepper stops working, then we know what is doing the stepping

The code from CPUi is about something different, CPUi is actually enabling clock modulation.

No they don't. The stuff GlobalThrottle into it. That's the current frequency.

Back later. Last hockey training for this season (in the low countries).

flAked · May 30, 2011

You could verify this by nop'ing the two write actions to 0x199 in AICPUPM. That should tell you if this is the case. And when the stepper stops working, then we know what is doing the stepping

Nopping out every 0x199 write (there are 7) I get:

May 30 18:04:02 slave kernel[0]: MSRDumper CoreMulti(33) 33 33 33 33 
May 30 18:04:18: --- last message repeated 31 times ---
May 30 18:04:18 slave kernel[0]: MSRDumper CoreMulti(16) 16 16 16 16 
May 30 18:04:18 slave kernel[0]: MSRDumper CoreMulti(33) 33 33 33 33 
May 30 18:04:23: --- last message repeated 7 times ---
May 30 18:04:22 slave kernel[0]: MSRDumper CoreMulti(16) 16 16 16 16 

(monitored for 10 minutes without any other multiplier)

Suggesting that a basic hardware coordination is going on regardless. It's unlikely that AICPUPM is activating a fall-back mode, it just can't set it's desired state. Meaning that this basic hardware coordination is always happening.

And to be complete, this is what I'm seeing if I only change the binary back:

May 30 18:29:21 slave kernel[0]: MSRDumper CoreMulti(16) 16 16 16 16 
May 30 18:29:22: --- last message repeated 1 time ---
May 30 18:29:22 slave kernel[0]: MSRDumper CoreMulti(35) 35 35 35 35 
May 30 18:29:22 slave kernel[0]: MSRDumper CoreMulti(16) 16 16 16 16 
May 30 18:29:25: --- last message repeated 4 times ---
May 30 18:29:25 slave kernel[0]: MSRDumper CoreMulti(21) 21 21 21 21 
May 30 18:29:25 slave kernel[0]: MSRDumper CoreMulti(20) 20 20 20 20 
May 30 18:29:26 slave kernel[0]: MSRDumper CoreMulti(16) 16 16 16 16 
May 30 18:29:27: --- last message repeated 1 time ---
May 30 18:29:27 slave kernel[0]: MSRDumper CoreMulti(35) 35 35 35 35

Note that I see something different, if I remove the mp_rendezvous call:

May 30 18:35:38 slave kernel[0]: MSRDumper CoreMulti(16) 
May 30 18:35:47: --- last message repeated 16 times ---
May 30 18:35:46 slave kernel[0]: MSRDumper CoreMulti(20) 
May 30 18:35:47 slave kernel[0]: MSRDumper CoreMulti(16) 
May 30 18:35:50: --- last message repeated 5 times ---
May 30 18:35:50 slave kernel[0]: MSRDumper CoreMulti(36) 
May 30 18:35:50 slave kernel[0]: MSRDumper CoreMulti(35) 
May 30 18:35:51 slave kernel[0]: MSRDumper CoreMulti(36) 
May 30 18:35:51 slave kernel[0]: MSRDumper CoreMulti(38) 
May 30 18:35:52 slave kernel[0]: MSRDumper CoreMulti(35)
--------------------
May 30 18:37:45 slave kernel[0]: MSRDumper CoreMulti(16) 
May 30 18:37:47 slave kernel[0]: MSRDumper CoreMulti(39) 
May 30 18:37:48 slave kernel[0]: MSRDumper CoreMulti(16) 
May 30 18:37:49 slave kernel[0]: MSRDumper CoreMulti(39) 
May 30 18:37:49 slave kernel[0]: MSRDumper CoreMulti(16) 
May 30 18:37:55 slave kernel[0]: MSRDumper CoreMulti(20) 
May 30 18:37:56 slave kernel[0]: MSRDumper CoreMulti(16)

THe KiNG · May 30, 2011

Had a chance to dump MSR's from iMac12,1 i5 2400S:

========================= MSR Information==========================

  MSR (ECX)         EAX         EDX	Description
   00000000    0000001F    00000000	IA32_P5_MC_ADDR
   00000001    00000000    00000000	IA32_P5_MC_TYPE
   00000006    00000040    00000000	IA32_MONITOR_FILTER_SIZE
   00000010    DA879FC7    00001855	IA32_TIME_STAMP_COUNTER, Timer Stamp Counter
   00000017    00000000    00040000	IA32_PLATFORM_ID, Platform ID
   0000001B    FEE00900    00000000	IA32_APIC_BASE, APIC Location and Status
   00000034    0000001C    00000000	MSR_SMI_COUNT, SMI Counter. (R/O).
   00000035    00040004    00000000	MSR_CORE_THREAD_COUNT
   0000003A    0000FF07    00000000	IA32_FEATURE_CONTROL, Control Features in Intel 64Processor. (R/W).
   00000079         N/A         N/A	IA32_BIOS_UPDT_TRIG, BIOS update trigger register
   0000008B    00000000    00000014	IA32_BIOS_SIGN_ID, BIOS update signature ID
   000000C1    00000000    00000000	IA32_PMC0, Performance counter register(Thread)
   000000C2    00000000    00000000	IA32_PMC1, Performance counter register(Thread)
   000000C3    00000000    00000000	IA32_PMC2, Performance counter register(Thread)
   000000C4    00000000    00000000	IA32_PMC3, Performance counter register(Thread)
   000000C5    00000000    00000000	IA32_PMC4, Performance counter register(Core)
   000000C6    00000000    00000000	IA32_PMC5, Performance counter register(Core)
   000000C7    00000000    00000000	IA32_PMC6, Performance counter register(Core)
   000000C8    00000000    00000000	IA32_PMC7, Performance counter register(Core)
   000000CE    70011900    00001000	MSR_PLATFORM_INFO
   000000E2    00000403    00000000	MSR_PKG_CST_CONFIG_CONTROL, C-State Configuration Control (R/W)
   000000E4    00010414    00000000	MSR_PMG_IO_CAPTURE_BASE, Power Management IO Redirection in C-state (R/W)
   000000E7    0006D335    00000000	IA32_MPERF, Maximum Performance Frequency Clock Count. (RW)
   000000E8    00161B2B    00000000	IA32_APERF, Actual Performance Frequency Clock Count. (RW)
   000000FE    00000D0A    00000000	IA32_MTRRCAP, MTRR Information.
   00000174    00000008    00000000	IA32_SYSENTER_CS, CS register target for CPL 0 code.
   00000175    8039E000    00000000	IA32_SYSENTER_ESP, Stack Pointer for CPL 0 stack.
   00000176    81A95B50    00000000	IA32_SYSENTER_EIP, CPL 0 code entry point.
   00000179    00000C09    00000000	IA32_MCG_CAP, Machine check capabilities.
   0000017A    00000000    00000000	IA32_STATUS, Machine check status.
   00000186    00000000    00000000	IA32_PERFEVTSEL0 (Thread)
   00000187    00000000    00000000	IA32_PERFEVTSEL1 (Thread)
   00000188    00000000    00000000	IA32_PERFEVTSEL2 (Thread)
   00000189    00000000    00000000	IA32_PERFEVTSEL3 (Thread)
   0000018A    00000000    00000000	IA32_PERFEVTSEL4 (Core)
   0000018B    00000000    00000000	IA32_PERFEVTSEL5 (Core)
   0000018C    00000000    00000000	IA32_PERFEVTSEL6 (Core)
   0000018D    00000000    00000000	IA32_PERFEVTSEL7 (Core)
   00000198    00002100    000026E9	IA32_PERF_STATUS/MSR_PERF_STATUS
   00000199    00002100    00000000	IA32_PERF_CTL
   0000019A    00000000    00000000	IA32_CLOCK_MODULATION, Clock Modulation Control.
   0000019B    00000010    00000000	IA32_THERM_INTERRUPT, Thermal Interrupt Control.
   0000019C    88280000    00000000	IA32_THERM_STATUS, Thermal Monitor Status.
   000001A0    00850089    00000000	IA32_MISC_ENABLE, Enable Miscellaneous Processor Features.
   000001A2    00560600    00000000	MSR_TEMPERATURE_TARGET
   000001A6    00000000    00000000	MSR_OFFCORE_RSP_0, Offcore Response Event Select Register (R/W)
   000001AA    00400000    00000000	MSR_MISC_PWR_MGMT
   000001AC         N/A         N/A	MSR_TURBO_POWER_CURRENT_LIMIT
   000001AD    1A1C2021    00000000	MSR_TURBO_RATIO_LIMIT, Maximum Ratio Limit of Turbo Mode.
   000001B0         N/A         N/A	IA32_ENERGY_PERF_BIAS, Performance Energy Bias Hint.
   000001B1    88280000    00000000	IA32_PACKAGE_THERM_STATUS, Package Thermal Status Information (RO).
   000001B2    00000000    00000000	IA32_PACKAGE_THERM_INTERRUPT, Pkg Thermal Interrupt Control.
   000001C8    00000000    00000000	MSR_LBR_SELECT, Last Branch Record Filtering Select Register (R/W)
   000001C9    00000000    00000000	MSR_LASTBRANCH_TOS, Last Branch Record Stack TOS. ®
   000001D9    00000000    00000000	IA32_DEBUGCTL, Debug Control.
   000001DD    00000000    00000000	MSR_LER_FROM_LIP, Last Exception Record From Linear IP. ®
   000001DE    00000000    00000000	MSR_LER_TO_LIP, Last Exception Record To Linear IP. ®
   000001F2    8F000006    00000000	IA32_SMRR_PHYSBASE, SMRR Base Address (Writeable only in SMM).
   000001F3    FF800800    00000000	IA32_SMRR_PHYSMASK, SMRR Range Mask (Writeable only in SMM).
   000001FC    0000005F    00000000	MSR_POWER_CTL
   00000200    8F800000    00000000	IA32_MTRR_PHYSBASE0, Variable Range Base MTRR.
   00000201    FF800800    0000000F	IA32_MTRR_PHYSMASK0, Variable Range Mask MTRR.
   00000202    90000000    00000000	IA32_MTRR_PHYSBASE1, Variable Range Base MTRR.
   00000203    F0000800    0000000F	IA32_MTRR_PHYSMASK1, Variable Range Mask MTRR.
   00000204    A0000000    00000000	IA32_MTRR_PHYSBASE2, Variable Range Base MTRR.
   00000205    E0000800    0000000F	IA32_MTRR_PHYSMASK2, Variable Range Mask MTRR.
   00000206    C0000000    00000000	IA32_MTRR_PHYSBASE3, Variable Range Base MTRR.
   00000207    C0000800    0000000F	IA32_MTRR_PHYSMASK3, Variable Range Mask MTRR.
   00000208    00000000    00000000	IA32_MTRR_PHYSBASE4, Variable Range Base MTRR.
   00000209    00000000    00000000	IA32_MTRR_PHYSMASK4, Variable Range Mask MTRR.
   0000020A    00000000    00000000	IA32_MTRR_PHYSBASE5, Variable Range Base MTRR.
   0000020B    00000000    00000000	IA32_MTRR_PHYSMASK5, Variable Range Mask MTRR.
   0000020C    00000000    00000000	IA32_MTRR_PHYSBASE6, Variable Range Base MTRR.
   0000020D    00000000    00000000	IA32_MTRR_PHYSMASK6, Variable Range Mask MTRR.
   0000020E    00000000    00000000	IA32_MTRR_PHYSBASE7, Variable Range Base MTRR.
   0000020F    00000000    00000000	IA32_MTRR_PHYSMASK7, Variable Range Mask MTRR.
   00000210    00000000    00000000	IA32_MTRR_PHYSBASE8
   00000211    00000000    00000000	IA32_MTRR_PHYSMASK8
   00000212    00000000    00000000	IA32_MTRR_PHYSBASE9
   00000213    00000000    00000000	IA32_MTRR_PHYSMASK9
   00000250    06060606    06060606	IA32_MTRR_FIX64K_00000, Fixed Range MTRR.
   00000258    06060606    06060606	IA32_MTRR_FIX16K_80000, Fixed Range MTRR.
   00000259    00000000    00000000	IA32_MTRR_FIX16K_A0000, Fixed Range MTRR.
   00000268    05050505    05050505	IA32_MTRR_FIX4K_C0000, Fixed Range MTRR.
   00000269    05050505    05050505	IA32_MTRR_FIX4K_C8000, Fixed Range MTRR.
   0000026A    05050505    05050505	IA32_MTRR_FIX4K_D0000, Fixed Range MTRR.
   0000026B    05050505    05050505	IA32_MTRR_FIX4K_D8000, Fixed Range MTRR.
   0000026C    00000000    00000000	IA32_MTRR_FIX4K_E0000, Fixed Range MTRR.
   0000026D    00000000    00000000	IA32_MTRR_FIX4K_E8000, Fixed Range MTRR.
   0000026E    00000000    00000000	IA32_MTRR_FIX4K_F0000, Fixed Range MTRR.
   0000026F    00000000    00000000	IA32_MTRR_FIX4K_F8000, Fixed Range MTRR.
   00000277    00070106    00070106	IA32_CR_PAT, Page Attribute Table
   00000280    00000000    00000000	IA32_MC0_CTL2
   00000281    00000000    00000000	IA32_MC1_CTL2
   00000282    00000000    00000000	IA32_MC2_CTL2
   00000283    00000000    00000000	IA32_MC3_CTL2
   00000284    00000000    00000000	IA32_MC4_CTL2, Always 0 (CMCI not supported)
   00000285    00000000    00000000	IA32_MC5_CTL2
   00000286    00000000    00000000	IA32_MC6_CTL2
   00000287    00000000    00000000	IA32_MC7_CTL2
   00000288    00000000    00000000	IA32_MC8_CTL2
   00000289         N/A         N/A	IA32_MC9_CTL2
   0000028A         N/A         N/A	IA32_MC10_CTL2
   0000028B         N/A         N/A	IA32_MC11_CTL2
   0000028C         N/A         N/A	IA32_MC12_CTL2
   0000028D         N/A         N/A	IA32_MC13_CTL2
   0000028E         N/A         N/A	IA32_MC14_CTL2
   0000028F         N/A         N/A	IA32_MC15_CTL2
   00000290         N/A         N/A	IA32_MC16_CTL2
   00000291         N/A         N/A	IA32_MC17_CTL2
   00000292         N/A         N/A	IA32_MC18_CTL2
   00000293         N/A         N/A	IA32_MC19_CTL2
   000002FF    00000C06    00000000	IA32_MTRR_DEF_TYPE, Default Memory Types.
   00000309    00000000    00000000	IA32_FIXED_CTR0, Fixed-Function Performance Counter 0 (R/W)
   0000030A    00000000    00000000	IA32_FIXED_CTR1, Fixed-Function Performance Counter 1 (R/W)
   0000030B    00000000    00000000	IA32_FIXED_CTR2, Fixed-Function Performance Counter 2 (R/W)
   00000345    000031C3    00000000	IA32_PERF_CAPABILITIES (RO)
   0000038D    00000000    00000000	IA32_FIXED_CTR_CTRL, Fixed-Function Performance Counter Control (R/W)
   0000038E    00000000    80000000	IA32_PERF_GLOBAL_STATUS, Global Performance Counter Status (RO)
   0000038F    000000FF    00000000	IA32_PERF_GLOBAL_CTRL, Global Performance Counter Control (R/W)
   00000390    00000000    00000000	IA32_PERF_GLOBAL_OVF_CTRL, Global Performance Counter Overflow Control (R/W)
   00000391    00000000    00000000	MSR_UNC_PERF_GLOBAL_CTRL, Uncore PMU global control
   00000392    00000000    00000000	MSR_UNC_PERF_GLOBAL_STATUS, Uncore PMU main status
   00000394    00000000    00000000	MSR_UNC_PERF_FIXED_CTRL, Uncore fixed counter control (R/W)
   00000395    00000000    00000000	MSR_UNC_PERF_FIXED_CTR, Uncore fixed counter
   000003F1    00000000    00000000	MSR_PEBS_ENABLE, Precise Event-Based Sampling (PEBS).
   000003F6    0000FFFF    00000000	MSR_PEBS_LD_LAT
   000003F8    C33A60DC    00000001	MSR_PKG_C3_RESIDENCY
   000003F9    06743B9C    00000F12	MSR_PKG_C6_RESIDENCY
   000003FA    00000000    00000000	MSR_PKG_C7_RESIDENCY
   000003FC    5D4CE4D8    00000002	MSR_CORE_C3_RESIDENCY
   000003FD    D8376708    0000178C	MSR_CORE_C6_RESIDENCY
   000003FE    00000000    00000000	MSR_CORE_C7_RESIDENCY
   00000400    0000001F    00000000	IA32_MC0_CTL
   00000401    00000000    00000000	IA32_MC0_STATUS
   00000402    00000000    00000000	IA32_MC0_ADDR
   00000403    00000000    00000000	IA32_MC0_MISC
   00000404    00000003    00000000	IA32_MC1_CTL
   00000405    00000000    09800000	IA32_MC1_STATUS
   00000406    00000000    00000000	IA32_MC1_ADDR
   00000407    00000086    00000000	IA32_MC1_MISC
   00000408    00000003    00000000	IA32_MC2_CTL
   00000409    00000000    00000000	IA32_MC2_STATUS
   0000040A         N/A         N/A	IA32_MC2_ADDR
   0000040B         N/A         N/A	IA32_MC2_MISC
   0000040C    00000007    00000000	IA32_MC3_CTL
   0000040D    00000000    00000000	IA32_MC3_STATUS
   0000040E    00000000    00000000	IA32_MC3_ADDR
   0000040F    00000000    00000000	IA32_MC3_MISC
   00000410    00000007    00000000	MSR_MC4_CTL
   00000411    00000000    00000000	IA32_MC4_STATUS
   00000414    0000003F    00000000	MSR_MC5_CTL
   00000415    00000000    00200000	MSR_MC5_STATUS
   00000416    FFB0FF80    00000000	MSR_MC5_ADDR
   00000417    40000086    00000010	MSR_MC5_MISC
   00000418    0000003F    00000000	MSR_MC6_CTL
   00000419    00000000    00200000	MSR_MC6_STATUS
   0000041A    FFB0FFC0    00000000	MSR_MC6_ADDR
   0000041B    40000086    00000010	MSR_MC6_MISC
   0000041C    0000003F    00000000	MSR_MC7_CTL
   0000041D    00000000    00200000	MSR_MC7_STATUS
   0000041E    FFB0FF00    00000000	MSR_MC7_ADDR
   0000041F    40000086    00000010	MSR_MC7_MISC
   00000420    0000003F    00000000	MSR_MC8_CTL
   00000421    00000000    00200000	MSR_MC8_STATUS
   00000422    FFB0FF40    00000000	MSR_MC8_ADDR
   00000423    40000086    00000050	MSR_MC8_MISC
   00000424         N/A         N/A	MSR_MC9_CTL
   00000425         N/A         N/A	MSR_MC9_STATUS
   00000426         N/A         N/A	MSR_MC9_ADDR
   00000427         N/A         N/A	MSR_MC9_MISC
   00000428         N/A         N/A	MSR_MC10_CTL
   00000429         N/A         N/A	MSR_MC10_STATUS
   0000042A         N/A         N/A	MSR_MC10_ADDR
   0000042B         N/A         N/A	MSR_MC10_MISC
   0000042C         N/A         N/A	MSR_MC11_CTL
   0000042D         N/A         N/A	MSR_MC11_STATUS
   0000042E         N/A         N/A	MSR_MC11_ADDR
   0000042F         N/A         N/A	MSR_MC11_MISC
   00000430         N/A         N/A	MSR_MC12_CTL
   00000431         N/A         N/A	MSR_MC12_STATUS
   00000432         N/A         N/A	MSR_MC12_ADDR
   00000433         N/A         N/A	MSR_MC12_MISC
   00000434         N/A         N/A	MSR_MC13_CTL
   00000435         N/A         N/A	MSR_MC13_STATUS
   00000436         N/A         N/A	MSR_MC13_ADDR
   00000437         N/A         N/A	MSR_MC13_MISC
   00000438         N/A         N/A	MSR_MC14_CTL
   00000439         N/A         N/A	MSR_MC14_STATUS
   0000043A         N/A         N/A	MSR_MC14_ADDR
   0000043B         N/A         N/A	MSR_MC14_MISC
   0000043C         N/A         N/A	MSR_MC15_CTL
   0000043D         N/A         N/A	MSR_MC15_STATUS
   0000043E         N/A         N/A	MSR_MC15_ADDR
   0000043F         N/A         N/A	MSR_MC15_MISC
   00000440         N/A         N/A	MSR_MC16_CTL
   00000441         N/A         N/A	MSR_MC16_STATUS
   00000442         N/A         N/A	MSR_MC16_ADDR
   00000443         N/A         N/A	MSR_MC16_MISC
   00000444         N/A         N/A	MSR_MC17_CTL
   00000445         N/A         N/A	MSR_MC17_STATUS
   00000446         N/A         N/A	MSR_MC17_ADDR
   00000447         N/A         N/A	MSR_MC17_MISC
   00000448         N/A         N/A	MSR_MC18_CTL
   00000449         N/A         N/A	MSR_MC18_STATUS
   0000044A         N/A         N/A	MSR_MC18_ADDR
   0000044B         N/A         N/A	MSR_MC18_MISC
   0000044C         N/A         N/A	MSR_MC19_CTL
   0000044D         N/A         N/A	MSR_MC19_STATUS
   0000044E         N/A         N/A	MSR_MC19_ADDR
   0000044F         N/A         N/A	MSR_MC19_MISC
   00000480    00000010    00DA0400	IA32_VMX_BASIC, Reporting Register of Basic VMX Capabilities. (R/O)
   00000481    00000016    0000007F	IA32_VMX_PINBASED_CTLS, Capability Reporting Register of Pin-based VM-execution Controls. (R/O)
   00000482    0401E172    FFF9FFFE	IA32_VMX_PROCBASED_CTLS, Capability Reporting Register of Primary Processor-based VM-execution Controls. (R/O)
   00000483    00036DFF    007FFFFF	IA32_VMX_EXIT_CTLS, Capability Reporting Register of VM-exit Controls. (R/O)
   00000484    000011FF    0000FFFF	IA32_VMX_ENTRY_CTLS, Capability Reporting Register of VM-entry Controls. (R/O)
   00000485    100401E5    00000000	IA32_VMX_MISC, Reporting Register of Miscellaneous VMX Capabilities. (R/O)
   00000486    80000021    00000000	IA32_VMX_CR0_FIXED0, Capability Reporting Register of CR0 Bits Fixed to 0. (R/O)
   00000487    FFFFFFFF    00000000	IA32_VMX_CR0_FIXED1, Capability Reporting Register of CR0 Bits Fixed to 1. (R/O)
   00000488    00002000    00000000	IA32_VMX_CR4_FIXED0, Capability Reporting Register of CR4 Bits Fixed to 0. (R/O)
   00000489    000667FF    00000000	IA32_VMX_CR4_FIXED1, Capability Reporting Register of CR4 Bits Fixed to 1. (R/O)
   0000048A    0000002A    00000000	IA32_VMX_VMCS_ENUM, Capability Reporting Register of VMCS Field Enumeration. (R/O)
   0000048B    00000000    000000FF	IA32_VMX_PROCBASED_CTLS2, Capability Reporting Register of Secondary Processor-based VM-execution Controls. (R/O)
   000004C1    00000000    00000000	IA32_A_PMC0
   000004C2    00000000    00000000	IA32_A_PMC1
   000004C3    00000000    00000000	IA32_A_PMC2
   000004C4    00000000    00000000	IA32_A_PMC3
   000004C5    00000000    00000000	IA32_A_PMC4
   000004C6    00000000    00000000	IA32_A_PMC5
   000004C7    00000000    00000000	IA32_A_PMC6
   00000600    00000000    00000000	IA32_DS_AREA, DS Save Area.
   00000602    00000104    18141494	???
   00000606    000A1003    00000000	MSR_RAPL_POWER_UNIT, Unit Multipliers used in RAPL Interfaces (R/O)
   0000060A    00008C02    00000000	MSR_PKGC3_IRTL, Package C3 Interrupt Response Limit (R/W)
   0000060B    0000885B    00000000	MSR_PKGC6_IRTL, Package C6 Interrupt Response Limit (R/W)
   0000060C    0000885B    00000000	MSR_PKGC7_IRTL, Package C7 Interrupt Response Limit (R/W)
   0000060D    876D627B    0000078A	MSR_PKG_C2_RESIDENCY
   00000610    00148208    0000028A	MSR_PKG_RAPL_POWER_LIMIT, PKG RAPL Power Limit Control (R/W)
   00000611    E5832729    00000000	MSR_PKG_ENERGY_STATUS, PKG Energy Status (R/O)
   00000613         N/A         N/A	MSR_PKG_PERF_STATUS, PKG Performance Throttling Status (R/O)
   00000614    01E00208    00000000	MSR_PKG_POWER_INFO, PKG RAPL Parameters (R/W)
   00000618         N/A         N/A	MSR_DRAM_POWER_LIMIT, DRAM RAPL Power Limit Control (R/W)
   00000619         N/A         N/A	MSR_DRAM_ENERY_STATUS, DRAM Energy Status (R/O)
   0000061B         N/A         N/A	MSR_DRAM_PERF_STATUS, DRAM Performance Throttling Status (R/O)
   0000061C         N/A         N/A	MSR_DRAM_POWER_INFO, DRAM RAPL Parameters (R/W)
   00000638    00000000    00000000	MSR_PP0_POWER_LIMIT, PP0 RAPL Power Limit Control (R/W)
   00000639    4DACAF6F    00000000	MSR_PP0_ENERGY_STATUS, PP0 Energy Status (R/O)
   0000063A    00000000    00000000	MSR_PP0_POLICY, PP0 Balance Policy (R/W)
   0000063B         N/A         N/A	MSR_PP0_PERF_STATUS, PP0 Performance Throttling Status (R/O)
   00000640    00000000    00000000	MSR_PP1_POWER_LIMIT, PP1 RAPL Power Limit Control (R/W)
   00000641    07311C14    00000000	MSR_PP1_ENERGY_STATUS, PP1 Energy Status (R/O)
   00000642    00000010    00000000	MSR_PP1_POLICY, PP1 Balance Policy (R/W)
   00000680    00000000    00000000	MSR_LASTBRANCH_0_FROM_IP, Last Branch Record 0 From IP. (R/W)
   00000681    00000000    00000000	MSR_LASTBRANCH_1_FROM_IP, Last Branch Record 1 From IP. (R/W)
   00000682    00000000    00000000	MSR_LASTBRANCH_2_FROM_IP, Last Branch Record 2 From IP. (R/W)
   00000683    00000000    00000000	MSR_LASTBRANCH_3_FROM_IP, Last Branch Record 3 From IP. (R/W)
   00000684    00000000    00000000	MSR_LASTBRANCH_4_FROM_IP, Last Branch Record 4 From IP. (R/W)
   00000685    00000000    00000000	MSR_LASTBRANCH_5_FROM_IP, Last Branch Record 5 From IP. (R/W)
   00000686    00000000    00000000	MSR_LASTBRANCH_6_FROM_IP, Last Branch Record 6 From IP. (R/W)
   00000687    00000000    00000000	MSR_LASTBRANCH_7_FROM_IP, Last Branch Record 7 From IP. (R/W)
   00000688    00000000    00000000	MSR_LASTBRANCH_8_FROM_IP, Last Branch Record 8 From IP. (R/W)
   00000689    00000000    00000000	MSR_LASTBRANCH_9_FROM_IP, Last Branch Record 9 From IP. (R/W)
   0000068A    00000000    00000000	MSR_LASTBRANCH_10_FROM_IP, Last Branch Record 10 From IP. (R/W)
   0000068B    00000000    00000000	MSR_LASTBRANCH_11_FROM_IP, Last Branch Record 11 From IP. (R/W)
   0000068C    00000000    00000000	MSR_LASTBRANCH_12_FROM_IP, Last Branch Record 12 From IP. (R/W)
   0000068D    00000000    00000000	MSR_LASTBRANCH_13_FROM_IP, Last Branch Record 13 From IP. (R/W)
   0000068E    00000000    00000000	MSR_LASTBRANCH_14_FROM_IP, Last Branch Record 14 From IP. (R/W)
   0000068F    00000000    00000000	MSR_LASTBRANCH_15_FROM_IP, Last Branch Record 15 From IP. (R/W)
   000006C0    00000000    00000000	MSR_LASTBRANCH_0_TO_LIP, Last Branch Record 0 To IP. (R/W)
   000006C1    00000000    00000000	MSR_LASTBRANCH_1_TO_LIP, Last Branch Record 1 To IP. (R/W)
   000006C2    00000000    00000000	MSR_LASTBRANCH_2_TO_LIP, Last Branch Record 2 To IP. (R/W)
   000006C3    00000000    00000000	MSR_LASTBRANCH_3_TO_LIP, Last Branch Record 3 To IP. (R/W)
   000006C4    00000000    00000000	MSR_LASTBRANCH_4_TO_LIP, Last Branch Record 4 To IP. (R/W)
   000006C5    00000000    00000000	MSR_LASTBRANCH_5_TO_LIP, Last Branch Record 5 To IP. (R/W)
   000006C6    00000000    00000000	MSR_LASTBRANCH_6_TO_LIP, Last Branch Record 6 To IP. (R/W)
   000006C7    00000000    00000000	MSR_LASTBRANCH_7_TO_LIP, Last Branch Record 7 To IP. (R/W)
   000006C8    00000000    00000000	MSR_LASTBRANCH_8_TO_LIP, Last Branch Record 8 To IP. (R/W)
   000006C9    00000000    00000000	MSR_LASTBRANCH_9_TO_LIP, Last Branch Record 9 To IP. (R/W)
   000006CA    00000000    00000000	MSR_LASTBRANCH_10_TO_LIP, Last Branch Record 10 To IP. (R/W)
   000006CB    00000000    00000000	MSR_LASTBRANCH_11_TO_LIP, Last Branch Record 11 To IP. (R/W)
   000006CC    00000000    00000000	MSR_LASTBRANCH_12_TO_LIP, Last Branch Record 12 To IP. (R/W)
   000006CD    00000000    00000000	MSR_LASTBRANCH_13_TO_LIP, Last Branch Record 13 To IP. (R/W)
   000006CE    00000000    00000000	MSR_LASTBRANCH_14_TO_LIP, Last Branch Record 14 To IP. (R/W)
   000006CF    00000000    00000000	MSR_LASTBRANCH_15_TO_LIP, Last Branch Record 15 To IP. (R/W)
   000006E0    00000000    00000000	IA32_TSC_DEADLINE
   00000700    00000000    00000000	MSR_UNC_CBO_0_PERFEVTSEL0, Uncore C-Box 0, counter 0 event select MSR
   00000701    00000000    00000000	MSR_UNC_CBO_0_PERFEVTSEL1, Uncore C-Box 0, counter 1 event select MSR
   00000705    00000000    00000000	MSR_UNC_CBO_0_UNIT_STATUS, Uncore C-Box 0, Overflow Status
   00000706    00000000    00000000	MSR_UNC_CBO_0_PER_CTR0, Uncore C-Box 0, performance counter 0
   00000707    00000000    00000000	MSR_UNC_CBO_0_PER_CTR1, Uncore C-Box 0, performance counter 1
   00000710    00000000    00000000	MSR_UNC_CBO_1_PERFEVTSEL0, Uncore C-Box 1, counter 0 event select MSR
   00000711    00000000    00000000	MSR_UNC_CBO_1_PERFEVTSEL1, Uncore C-Box 1, counter 1 event select MSR
   00000715    00000000    00000000	MSR_UNC_CBO_1_UNIT_STATUS, Uncore C-Box 1, Overflow Status
   00000716    00000000    00000000	MSR_UNC_CBO_1_PER_CTR0, Uncore C-Box 1, performance counter 0
   00000717    00000000    00000000	MSR_UNC_CBO_1_PER_CTR1, Uncore C-Box 1, performance counter 1
   00000720    00000000    00000000	MSR_UNC_CBO_2_PERFEVTSEL0, Uncore C-Box 2, counter 0 event select MSR
   00000721    00000000    00000000	MSR_UNC_CBO_2_PERFEVTSEL1, Uncore C-Box 2, counter 1 event select MSR
   00000725    00000000    00000000	MSR_UNC_CBO_2_UNIT_STATUS, Uncore C-Box 2, Overflow Status
   00000726    00000000    00000000	MSR_UNC_CBO_2_PER_CTR0, Uncore C-Box 2, performance counter 0
   00000727    00000000    00000000	MSR_UNC_CBO_2_PER_CTR1, Uncore C-Box 2, performance counter 1
   00000730    00000000    00000000	MSR_UNC_CBO_3_PERFEVTSEL0, Uncore C-Box 3, counter 0 event select MSR
   00000731    00000000    00000000	MSR_UNC_CBO_3_PERFEVTSEL1, Uncore C-Box 3, counter 1 event select MSR
   00000735    00000000    00000000	MSR_UNC_CBO_3_UNIT_STATUS, Uncore C-Box 3, Overflow Status
   00000736    00000000    00000000	MSR_UNC_CBO_3_PER_CTR0, Uncore C-Box 3, performance counter 0
   00000737    00000000    00000000	MSR_UNC_CBO_3_PER_CTR1, Uncore C-Box 3, performance counter 1

They where dumped with HWDirect tool under 32 bit windows.

If someone what to compare attached is the config I made for sandy bridge, hope I didn't miss some...

HwMsrSandyBridge.msr.zip

mrmojorisin17 · May 30, 2011

This is what I get with flAked's MSRDumper.kext and my i5-2500K @3,3GHz (Turbo Ratios 1234):

May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x35): 0x40004
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0xCE): 0x70012100
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0xE2): 0x1e008407
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0xE4): 0x10414
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0xE7): 0x8819a0f8
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0xE8): 0xa892bf01
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x198): 0x2200
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x199): 0x2200
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x19A): 0x0
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x19C): 0x883d0000
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x1A0): 0x850089
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x1AA): 0x400001
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x1AD): 0x22232425
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x1B0): 0x4
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x1FC): 0x4005f
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x602): 0x104
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x606): 0xa1003
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x610): 0x1487f8
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x611): 0xa0f41ebe
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x639): 0x78af8726
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x640): 0x0
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x641): 0x0
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper: rdmsr64(0x642): 0x10
May 30 19:56:33 iHack122-di-Mr-Mojo-Risin kernel[0]: CoreCount: 4ThreadCount: 40x2E: 0x1e008407
May 30 19:56:38 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:56:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:56:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:56:42 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:56:43 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:56:43 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:56:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:56:54 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 19:56:55 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:56:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:56:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:56:58 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:56:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:57:00 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:57:01 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:57:02 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:57:03 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:57:04 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:57:05 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:57:06 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:57:07 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:57:07 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:57:08 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:57:09 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:57:09 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:57:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:57:11 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:57:11 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:57:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:57:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:57:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:57:26 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:30 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 19:57:30 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(37) 
May 30 19:57:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:57:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:46 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 19:57:46 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:47 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(22) 
May 30 19:57:47 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:53 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 19:57:53 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:57:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:57:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:57:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:13 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 19:58:13 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:21 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 19:58:21 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:58:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:26 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:27 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:28 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(37) 
May 30 19:58:30 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:58:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:38 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:38 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:45 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:45 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:58:46 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:48 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(22) 
May 30 19:58:49 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:49 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:58:50 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:50 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:58:51 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:55 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:56 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:58:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:58:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:00 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:59:00 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:01 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:59:02 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:05 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:59:06 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:07 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:59:08 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:14 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:59:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:59:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 19:59:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:59:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 19:59:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:45 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:59:46 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:48 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:59:49 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 19:59:52 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 19:59:52 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:00:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:00:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:00:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:00:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:00:54 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:01:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:01:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:01:42 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:02:11 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:02:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:03:11 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:03:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:03:58 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:03:58 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:03:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:03:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:01 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:04:01 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:03 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:04:03 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 20:04:04 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:07 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(37) 
May 30 20:04:08 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:11 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:13 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:13 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:14 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:14 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:04:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:04:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:04:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(22) 
May 30 20:04:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:04:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(37) 
May 30 20:04:21 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:04:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:26 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:27 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:04:27 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:28 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:04:30 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:30 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 20:04:35 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:36 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:37 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:04:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:04:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:03 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:03 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:11 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:12 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:12 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:13 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:14 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:05:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:05:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:05:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:05:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:21 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:05:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(22) 
May 30 20:05:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 20:05:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:43 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:05:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:54 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:05:55 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:05:55 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:05:56 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:05:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:00 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:06:01 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:06 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:06:06 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:14 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:06:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:06:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:06:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:06:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:06:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:06:21 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:06:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:47 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:06:48 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:55 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:06:56 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:56 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:06:57 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:06:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:06:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:02 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:07:03 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:04 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:07:04 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:08 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:08 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:09 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:09 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:07:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:13 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:13 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:14 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:07:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:07:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:07:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:21 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:07:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:07:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:07:40 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:07:42 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:07:43 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:07:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:07:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:08:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:08:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:08:36 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:08:37 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:08:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:09:00 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:09:07 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:09:07 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:09:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:09:26 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:09:55 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:10:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:10:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:10:51 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:10:52 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:11:04 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:11:05 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:11:05 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:11:06 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:11:35 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:12:05 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:12:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:12:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:13:02 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:13:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:14:02 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:14:08 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:14:09 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:14:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:14:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:14:40 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:15:10 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:15:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:15:22 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:15:52 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:16:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:16:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:16:45 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:17:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:17:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:17:40 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:18:09 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:18:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:09 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:26 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:19:27 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:19:27 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 20:19:28 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:28 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:19:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 20:19:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:19:30 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:30 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:19:31 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:31 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:19:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:19:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:48 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:19:48 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:19:49 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:50 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:19:51 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:19:54 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(22) 
May 30 20:19:54 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:20:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:20:20 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(37) 
May 30 20:20:23 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 20:20:25 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:20:29 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(35) 
May 30 20:20:33 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:34 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:35 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(36) 
May 30 20:20:36 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:38 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:39 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:40 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:41 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:45 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:46 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:47 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:48 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:49 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:20:58 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:20:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:01 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:01 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:07 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:08 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:18 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:24 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:31 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:32 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(21) 
May 30 20:21:44 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:45 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:45 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:46 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:46 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:49 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(34) 
May 30 20:21:49 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:50 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:21:58 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:21:59 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:22:14 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:22:15 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:22:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:22:16 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16) 
May 30 20:22:17 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(20) 
May 30 20:22:19 iHack122-di-Mr-Mojo-Risin kernel[0]: MSRDumper CoreMulti(16)

All with EIST, Turbo Mode and C-States enabled.

A list of step that I get:

16, 20, 21, 22, 24, 34, 35, 36, 37

flAked · May 30, 2011

Official word from Intel:

On IA different cores from the same package are always running at the same P-State. Therefore PERF_STATUS will give you the P-State all non-idle cores within a package are running at.

Hmm, why do I get only these steppings, APSN = 0x0F

May 30 23:40:33 slave kernel[0]: MSRDumper PStatesReached: 16 20 21 22 35 36 38 39

APSN = 0x12, worse?

May 30 23:53:56 slave kernel[0]: MSRDumper PStatesReached: 16 35 36 38 39

This can't be a coincidence: 0x12 - 0x0F = 0x03 and I see 3 less P-States.

Let's try APSN = 0x0E:

May 31 00:00:16 slave kernel[0]: MSRDumper PStatesReached: 16 20 21 22 23 35 36 38 39

Nice! Now, do some math. We are seeing 9 out of 19 P-States... Wait a minute, that brings us back to 0x04.

So APSN are in fact the Turbo States?

Hmm, this is definitely not worse, but where is the correlation? APSN = 0x04:

May 31 00:16:52 slave kernel[0]: MSRDumper PStatesReached: 16 22 26 30 33 35 36 38 39

APSN = 0x0D and yet another set of numbers I've never seen so far:

May 31 00:29:40 slave kernel[0]: MSRDumper PStatesReached: 16 20 21 23 24 35 36 38 39 
May 31 01:03:57 slave kernel[0]: MSRDumper PStatesReached: 16 20 21 23 24 35 36 38 39
May 31 01:09:24 slave kernel[0]: MSRDumper PStatesReached: 16 20 21 23 24 35 36 38 39

Let's make sure this isn't random and reboot twice with 0x0D. Good.

So for some reason we won't see more than 9 states being used (with the tested APSN so far).

MacBookPro8,1: APSS = 22 P-States and APSN = 0x06 = 6

MacBookPro8,2: APSS = 27 P-States and APSN = 0x0B = 11

According to the dumps from THe KiNG the Turbo Ratio multipliers for the iMac12,1 are 26, 28, 32, 33

Also, MSR_MISC_PWR_MGMT (0x1AA) bit 22 is set, which is undocumented.

Time2Retire · May 30, 2011

Official word from Intel:
On IA different cores from the same package are always running at the same P-State. Therefore PERF_STATUS will give you the P-State all non-idle cores within a package are running at.

I don't get it. This can't be true. That would mean that the load factor calculated by using 0xE7 and 0xE8 is pointless from the beginning. That all you need is to read MSR 0x198 anyway. Please ask him to explain this for me. Thanks.

Nice! Now, do some math. We are seeing 9 out of 19 P-States... Wait a minute, that brings us back to 0x04.
So APSN are in fact the Turbo States?

Hmm, this is definitely not worse, but where is the correlation? APSN = 0x04:

APSN = 0x0D and yet another set of numbers I've never seen so far:...

So for some reason we won't see more than 9 states being used (with the tested APSN so far).

Whatever APSN is, there's no 'T' in it. Could be the index number where normal P-States start. We might want to ask around in the Apple dev forums.

I'm also puzzled about the ringFreqTable found in the iMac12 and MacBookPro8 plists. Changing it seems to break things.

According to the dumps from THe KiNG the Turbo Ratio multipliers for the iMac12,1 are 26, 28, 32, 33

But we already knew this.

Also, MSR_MISC_PWR_MGMT (0x1AA) bit 22 is set, which is undocumented.

I haven't checked his dump, will do that next, but in the one I have it is: MSR 000001AA: 0000-0000-0040-0000

Correct. That is indeed bit 22. Hmm. Let's try to find a document/source code file that explains this one...

flAked · May 31, 2011

I don't get it. This can't be true. That would mean that the load factor calculated by using 0xE7 and 0xE8 is pointless from the beginning. That all you need is to read MSR 0x198 anyway. Please ask him to explain this for me. Thanks.

Someone posted this: http://software . intel . com/en-us/forums/showthread.php?t=83060&p=1#151426

But we already knew this.

Yeah, yeah. Reading out seemingly unknown MSR, still fun though

LOL the first google hit is..... this thread: http://www.google.com/search?q=MSR_MISC_PWR_MGMT

PS: how was your last match?

Time2Retire · May 31, 2011

Someone posted this: http://software . intel . com/en-us/forums/showthread.php?t=83060&p=1#151426

Yeah I got your PM. Thanks for that BTW. Bit of a backlog with TODO's that I can't seem to finish in time. I haven't even installed 10K531 yet.

LOL the first google hit is..... this thread:

LOL

PS: how was your last match?

Oh it was great. Thanks for asking.

Mom arranged a real nice dinner in a restaurant – she said to go to work, but that was a lie. Some of the girls are coming over for a short holiday break. One will even be flying with me. Mom rescheduled the flight because I am really afraid of flying alone for so long, and now we're in business class as well. Thanks to my sponsor (Rabobank).

flAked · May 31, 2011

I'm also puzzled about the ringFreqTable found in the iMac12 and MacBookPro8 plists. Changing it seems to break things.

The table appears to be identical across SB models, suggesting it is not processor model specific?

Maybe we need to mod the StepDataDict?

Is your ACPI_SMC_PlatformPlugin -> IOPlatformThermalProfile empty as well? Is that a problem?

Time2Retire · May 31, 2011

The table appears to be identical across SB models, suggesting it is not processor model specific?

Maybe we need to mod the StepDataDict?

I wouldn't know where to start. I only know that the first word is the length and the second one the version. Other than that... but maybe this 42 there is related to the error you have seen when you change APSN?

I checked it in hexedit and found: pstates, minpstate, mntpstate and npstates

Is your ACPI_SMC_PlatformPlugin -> IOPlatformThermalProfile empty as well? Is that a problem?

Yes. Same on MacBookPro's

Time to get some food now (getting used to my new timezone).

flAked · May 31, 2011

I checked it in hexedit and found: pstates, minpstate, mntpstate and npstates

Hmm I'm unable to convert the data, my brain stopped working. Can you give me a hint?

I guess I call it a day, have a good night.

Time2Retire · May 31, 2011

This is what I have so far from looking at StepDataDict (SP13) in the MacBookPro8_3.plist:

92 0A 00 00 = Length

00 00 00 01 = Version

00 02 04 00 00 [color="#FF0000"][b]42[/b][/color] 00 00 00 23 04 00 00 02 00 81 

00 70 00 73 00 74 00 61 00 74 00 65 00 73 = "pstates"

[color="#FF0000"][b]0A[/b][/color] 00 00 06 03 00 00 80 

00 6D 00 69 00 6E 00 70 00 73 00 74 00 61 00 74 00 65 = "minpstate"

0D 00 00 80 

00 6D 00 6E 00 74 00 70 00 73 00 74 00 61 00 74 00 65 = "mntpstate"

0D 00 00 80 

00 6E 00 70 00 73 00 74 00 61 00 74 00 65 00 73  = "npstates"

FF 00 FF 00 FF 00 FF 00 FF 00 B2 00 00

[color="#006400"]FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 

FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 

FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 

FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 

FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 

FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 

FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0F 00 00 
FF 01 00 03 FF 00 0B 0A 00 00 [/color]

--------------------------------------------------------------------------------------------------------------------

01 0A 00 00 64 00 00 00 05 08 00 00 01 00 00 05 FF

[color="#A0522D"]00 01 00 00 00 01 00 00 00 01 06 00 00 65 00 00 00 0E 08 00 00 02 00 00 05 FF 

00 01 00 00 00 02 00 00 00 02 06 00 00 64 00 00 00 03 00 00 00 02 06 00 00 03 00 00 05 FF

00 01 00 00 00 03 00 00 00 03 06 00 00 65 00 00 00 0E 04 00 00 01 02 00 00 04 00 00 05 FF 

00 01 00 00 00 04 00 00 00 04 06 00 00 64 00 00 00 05 00 00 00 04 06 00 00 05 00 00 05 FF 

00 01 00 00 00 05 00 00 00 05 06 00 00 64 00 00 00 03 00 00 00 02 06 00 00 06 00 00 05 FF 

00 01 00 00 00 06 00 00 00 06 06 00 00 64 00 00 00 03 00 00 00 03 06 00 00 07 00 00 05 FF 

00 01 00 00 00 07 00 00 00 07 06 00 00 67 0A 00 00 08 00 00 05 FF 

00 01 00 00 00 08 00 00 00 08 06 00 00 69 0A 00 00 09 00 00 05 FF 

00 01 00 00 00 09 00 00 00 09 06 00 00 64 00 00 00 03 00 00 00 02 06 00 00 0A 00 00 05 FF 

00 01 00 00 00 0A 00 00 00 0A 06 00 00 66 0A 00 00 0B 00 00 05 FF 

00 01 00 00 00 0B 00 00 00 0B 06 00 00 65 00 00 00 0E 04 00 00 02 02 00 00 0C 00 00 05 FF 

00 01 00 00 00 0C 00 00 00 0C 06 00 00 64 00 00 00 05 00 00 00 02 06 00 00 0D 00 00 05 FF 

00 01 00 00 00 0D 00 00 00 0D 06 00 00 64 00 00 00 03 00 00 00 02 06 00 00 0E 00 00 05 FF 

00 01 00 00 00 0E 00 00 00 0E 06 00 00 64 00 00 00 03 00 00 00 03 06 00 00 0F 00 00 05 FF

00 01 00 00 00 0F 00 00 00 0F 06 00 00 67 0A 00 00 10 00 00 05 FF 

00 01 00 00 00 10 00 00 00 10 06 00 00 69 0A 00 00 11 00 00 05 FF 

00 01 00 00 00 11 00 00 00 11 06 00 00 64 00 00 00 03 00 00 00 02 06 00 00 12 00 00 05 FF 

00 01 00 00 00 12 00 00 00 12 06 00 00 66 0A 00 00 13 00 00 05 FF

00 01 00 00 00 13 00 00 00 13 06 00 00 65 00 00 00 0E 04 00 00 03 02 00 00 14 00 00 05 FF 

00 01 00 00 00 14 00 00 00 14 06 00 00 64 00 00 00 05 00 00 00 04 06 00 00 15 00 00 05 FF 

00 01 00 00 00 15 00 00 00 15 06 00 00 64 00 00 00 05 00 00 00 03 06 00 00 16 00 00 05 FF 

00 01 00 00 00 16 00 00 00 16 06 00 00 64 00 00 00 03 00 00 00 02 06 00 00 17 00 00 05 FF 

00 01 00 00 00 17 00 00 00 17 06 00 00 64 00 00 00 03 00 00 00 03 06 00 00 18 00 00 05 FF 

00 01 00 00 00 18 00 00 00 18 06 00 00 67 0A 00 00 19 00 00 05 FF 

00 01 00 00 00 19 00 00 00 19 06 00 00 68 0A 00 00 1A 00 00 05 FF 

00 01 00 00 00 1A 00 00 00 1A 06 00 00 69 0A 00 00 1B 00 00 05 FF 

00 01 00 00 00 1B 00 00 00 1B 06 00 00 64 00 00 00 03 00 00 00 02 06 00 00 1C 00 00 05 FF 

00 01 00 00 00 1C 00 00 00 1C 06 00 00 66 0A 00 00 1D 00 00 05 FF 

00 01 00 00 00 1D 00 00 00 1D 06 00 00 65 00 00 00 0E 04 00 00 04 02 00 00 1E 00 00 05 FF 

00 01 00 00 00 1E 00 00 00 1E 06 00 00 64 00 00 00 03 00 00 00 01 06 00 00 1F 00 00 05 FF 

00 01 00 00 00 1F 00 00 00 1F 06 00 00 65 00 00 00 0E 04 00 00 05 02 00 00 20 00 00 05 FF 

00 01 00 00 00 20 00 00 00 20 06 00 00 0F 00 27 09 00 00 21 00 00 05 FF 

00 02 02 00 00 21 06 00 00 01 00 00 00 0E 04 00 00 05 02 00 00 22 00 00 05 FF [/color]

--------------------------------------------------------------------------------------------------------------------

00 02 00 00 00 01 00 00 00 22 06 00 00 02 00 00 00 04 01 00 00 80 00 C3 00 B7 00 2E 00 34 00 0B 00 00 00 23 00 00 00 22 00 00 00 22 00 00 00 23 00 00 00 03 02 00 00 23 06 00 00 01 00 00 00 0E 04 00 00 05 02 00 00 24 00 00 05 FF 

00 04 02 00 00 24 06 00 00 09 00 00 00 04 00 00 00 C8 06 00 00 25 00 00 05 FF 

00 04 00 00 00 01 00 00 00 25 04 00 00 80 00 00 00 0A 0A 00 00 29 00 00 00 26 00 00 00 29 00 00 00 26 00 00 00 04 00 00 00 02 00 00 00 26 06 00 00 07 00 00 00 01 00 00 00 F5 00 01 05 00 00 27 00 00 05 FF 

00 04 00 00 00 03 00 00 00 27 06 00 00 02 00 00 00 04 00 00 00 A0 00 0F 05 00 00 28 00 00 00 21 00 00 00 21 00 00 00 28 00 00 00 04 00 00 00 04 00 00 00 28 06 00 00 08 0A 00 00 24 00 00 05 FF 

00 05 02 00 00 29 06 00 00 01 00 00 00 0E 04 00 00 04 02 00 00 2A 00 00 05 FF 

00 06 02 00 00 2A 06 00 00 02 00 00 00 04 00 00 00 D0 00 07 05 00 00 2E 00 00 00 2B 00 00 00 2E 00 00 00 2B 00 00 00 06 00 00 00 01 00 00 00 2B 06 00 00 07 00 00 00 01 00 00 00 F5 00 01 05 00 00 2C 00 00 05 FF 

00 06 00 00 00 02 00 00 00 2C 06 00 00 02 00 00 00 04 00 00 00 A0 00 0F 05 00 00 2D 00 00 00 21 00 00 00 21 00 00 00 2D 00 00 00 06 00 00 00 03 00 00 00 2D 06 00 00 08 0A 00 00 2A 00 00 05 FF 

00 07 02 00 00 2E 06 00 00 01 00 00 00 0E 04 00 00 03 02 00 00 2F 00 00 05 FF 

00 08 02 00 00 2F 06 00 00 02 00 00 00 04 00 00 00 AC 00 0D 05 00 00 33 00 00 00 30 00 00 00 33 00 00 00 30 00 00 00 08 00 00 00 01 00 00 00 30 06 00 00 07 00 00 00 01 00 00 00 F5 00 01 05 00 00 31 00 00 05 FF 

00 08 00 00 00 02 00 00 00 31 06 00 00 02 00 00 00 04 00 00 00 A0 00 0F 05 00 00 32 00 00 00 21 00 00 00 21 00 00 00 32 00 00 00 08 00 00 00 03 00 00 00 32 06 00 00 08 0A 00 00 2F 00 00 05 FF 

00 09 02 00 00 33 06 00 00 01 00 00 00 0E 04 00 00 02 02 00 00 34 00 00 05 FF 

00 0A 02 00 00 34 06 00 00 02 00 00 00 04 00 00 00 AC 00 0D 05 00 00 38 00 00 00 35 00 00 00 38 00 00 00 35 00 00 00 0A 00 00 00 01 00 00 00 35 06 00 00 07 00 00 00 01 00 00 00 F5 00 01 05 00 00 36 00 00 05 FF 

00 0A 00 00 00 02 00 00 00 36 06 00 00 02 00 00 00 04 00 00 00 A0 00 0F 05 00 00 37 00 00 00 21 00 00 00 21 00 00 00 37 00 00 00 0A 00 00 00 03 00 00 00 37 06 00 00 08 0A 00 00 34 00 00 05 FF 

00 0B 02 00 00 38 06 00 00 01 00 00 00 0E 04 00 00 01 02 00 00 39 00 00 05 FF 

00 0C 02 00 00 39 06 00 00 02 00 00 00 04 00 00 00 D0 00 07 05 00 00 3D 00 00 00 3A 00 00 00 3D 00 00 00 3A 00 00 00 0C 00 00 00 01 00 00 00 3A 06 00 00 07 00 00 00 01 00 00 00 F5 00 01 05 00 00 3B 00 00 05 FF 

00 0C 00 00 00 02 00 00 00 3B 06 00 00 02 00 00 00 04 00 00 00 A0 00 0F 05 00 00 3C 00 00 00 21 00 00 00 21 00 00 00 3C 00 00 00 0C 00 00 00 03 00 00 00 3C 06 00 00 08 0A 00 00 39 00 00 05 FF 

00 0D 02 00 00 3D 06 00 00 01 00 00 00 0E 08 00 00 3E 00 00 05 FF 

00 0E 02 00 00 3E 06 00 00 02 00 00 00 04 01 00 00 80 00 C3 00 B7 00 2E 00 34 00 0B 00 00 00 3E 00 00 00 3F 00 00 00 3E 00 00 00 3F 00 00 00 0E 00 00 00 01 00 00 00 3F 06 00 00 07 00 00 00 01 00 00 00 F5 00 01 05 00 00 40 00 00 05 FF 

00 0E 00 00 00 02 00 00 00 40 06 00 00 02 00 00 00 04 00 00 00 A0 00 0F 05 00 00 41 00 00 00 21 00 00 00 21 00 00 00 41 00 00 00 0E 00 00 00 03 00 00 00 41 06 00 00 08 0A 00 00 3E 00 00 05 FF

Note the two red marked values which may be related to the maximum number of P-States we see, and the 42 might be related to the number we saw when APSN was wrong.

The green marked block, with 64 values, is exactly the same as in the MacPro3_1.plist

Note: I seem to be one off with the end-marker because I see odd numbers of values. Should be even I guess.

flAked · May 31, 2011

The version string suggested that it is nested NSDictionary, but I had no luck with it:

NSDictionary *plist = [NSDictionary dictionaryWithContentsOfFile:@"data.plist"];
NSData *data = [plist valueForKey:@"SP13"];

NSString *tmp = nil;
NSPropertyListFormat *format = nil;

NSDictionary *dic = (NSDictionary*)[NSPropertyListSerialization propertyListFromData:data mutabilityOption:NSPropertyListBinaryFormat_v1_0 format:format errorDescription:&tmp];

NSLog(@"%@ %@", tmp, format);

Time2Retire · May 31, 2011

I see in the Intel Speedstep thread that there is no need to specify the frequency / power fields. At least back in the old days. Let's try that. One at a time. Let's start with the power – maybe AICPUPM is using these fields to determine the target P-State and when we're off too much it won't select it?

Have to do some shopping now and visit a friend (the one that is flying with me).

flAked · May 31, 2011

I booted up with MBP8,3 and got the same result as with iMac12,2:

May 31 16:48:55 slave kernel[0]: MSRDumper PStatesReached: 16 20 21 23 24 35 36 38 39

MacPro5,1 gives me:

May 31 16:57:42 slave kernel[0]: MSRDumper PStatesReached: 16 35 36 38 39

So what are the differences in the plist?

1) there is no ringFreqTables

2) StepDataDict is different

Adding the ringFreqTables to the MacPro5_1.plist doesn't change a thing, but replacing the StepDataDict now results in:

May 31 17:19:00 slave kernel[0]: MSRDumper PStatesReached: 16 22 26 30 33 35 36 38 39

Don't worry about the different mid-values, I changed APSN back to 0x04.

Let's go bonkers and add this into the plist:

<key>StepDataDict</key>
	  <dict>
		<key>MacPro5,1</key>
		<array>
		  <dict>
			<key>num-states</key>
			<integer>13</integer>
			<key>program</key>
			<string>SP13</string>
		  </dict>
	</array>
		<key>SP13</key>
		<data>.....

This triggers the following error:

WARNING - ACPI_SMC_CtrlLoop::initCPUCtrlLoop - no sub-config match for MacPro5,1 with 19 p-states, using default stepper instead

And the default stepper seems to be:

MSRDumper PStatesReached: 16 35 36 38 39

So now, if we change num-states to 19 the error is gone and I get:

MSRDumper PStatesReached: 16 22 26 30 33 35 36 38 39

So is the StepDataDict hardcoded to 9 states for the iMac12?

On Lion DP3 they changed the StepDataDict for the iMac12,2 to a new SP11 which is much smaller, but doesn't work on 10.6.8. In Lion it gives me only the "default stepper" with 16 35 36 38 39 (without errors in the log).

Changing SP13 (replacing 0A with 0F) will result in:

 ACPI_SMC_CtrlLoop::loadStepperProgram - pmCPUControl (PMIOCSETPSTATESTEPPER) failed, result = 0x4

Let's try some other Stepper Programs, SP12:

MSRDumper PStatesReached: 16 35 36 38 39

SP1 gives me something new, my first 5 p-states in a row:

MSRDumper PStatesReached: 16 20 21 22 23 35 36 38 39

SP11 (iMac11):

MSRDumper PStatesReached: 16 35 36 38 39

For the first time, SP4 is showing 10 p-states:

MSRDumper PStatesReached: 16 20 21 22 23 24 35 36 38 39

SP10 with only 8 p-states, but a broader range:

MSRDumper PStatesReached: 16 22 27 32 35 36 38 39

mrmojorisin17 · May 31, 2011

No one with a new iMac can test with MSRDumper how many P-States it use?

Or better: there is a method in Windows to show the P-States that system is using?

Are you sure that all P-States are used?

flAked · May 31, 2011

Or better: there is a method in Windows to show the P-States that system is using?
Are you sure that all P-States are used?

Good thinking, yes. Let's figure out which P-States are actually supported by our CPU.

Not just relying on the PSS object by Asus.

mrmojorisin17 · May 31, 2011

Because maybe you're trying to find a solution for something that is not necessary for our CPU.

I'm google(ing) but for the moment I dont' find anything.

Maybe this could be help us -> BITS

I mean: if our CPU supports "only" 9 P-States we can define it on our SSDT_PR and then check with MSRDumper if all are working. If yes I think that "we're sitting pretty" (italian translation is "essere a cavallo" and don't know if also in english is used) :thumbsup_anim:

flAked · May 31, 2011

The thing is, if I put all the experiments together, I get way more than 9 P-States. Even just changing APSN shifts the offset so other P-States are being used. So the pure CPU capability must be more.

The question is (for the original models), why have all these P-States in APSS if the Stepper Program won't use them?

Time2Retire · June 1, 2011

The thing is, if I put all the experiments together, I get way more than 9 P-States. Even just changing APSN shifts the offset so other P-States are being used. So the pure CPU capability must be more.

The question is (for the original models), why have all these P-States in APSS if the Stepper Program won't use them?

You can define a P-State for each used (supported) multiplier. I also found this:

Chapter 4.2.1 in 324621.pdf (May 2011) Enhanced Intel® SpeedStep® Technology is pretty clear about two things:

"Frequency selection is software controlled by writing to processor MSRs."

"The voltage is optimized based on the selected frequency and the number of active processor cores."

"All active processor cores share the same frequency and voltage. In a multi- core processor, the highest frequency P-state requested amongst all active cores is selected."

"The processor controls voltage ramp rates internally to ensure glitch-free transitions."

This explains why my experiment – using 0 for the frequency and power fields – worked. We don't seem to need it. The CPU will do this.

Are all declared P-States showing up already?

DSDT for Asus P8P67-M PRO

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