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DSDT: trick retail drivers by changing "device-id" (e.g USB)


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#141
mitch_de

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Sorry for the flood!

another slightly blond moment :P i dint' use DropSSDT=y when I took dmesg dump with voodoo.


Hi
i want to add my P-States into my dsdt.dsl , not in an extra ssdt-x. aml.
The changes(adds) in the DSDT cpu part are no problem, but i have a few questions around adding P-State tables in the CPU part of dsdt.dsl.

I use PC EFI bootloader 10.1 (or 10.2) for my 10.5.8 and also SL partitions.
Do i need that DropSSDT=yes option if i have pstates included in my dsdt.aml or is that only needed for users which have an extra ssdt-x.aml ?
I needed, does PC EFI 10.1 boot (rest is chameleon 2 RC1) support DropSSDT=yes ?

I can use IORegistry explorer and see in ACPI my DSDT/SSDT Entries (in HEX) ans all others.
Where can i check in the IORegistry explorer if the changed part of dsdt.aml (the added Pstates) is used ?
I have extracted my SSDT-0 (i only have one ).
Do i need some information out of there and add it toor my P-States adding in dsdt.dsl ?
Here the adding in general (not my needed psstates, i have my own values already):

_PSS, Package (0x03)
{
Package (0x06)// P-State 0
{
3104, // f in MHz
75000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x00000820, // value written to PERF_CTL; fid=8, vid=32
0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
},

Package (0x06)// P-State 1
{
2716, // f in MHz
65000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000071C, // value written to PERF_CTL; fid=7, vid=28
0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
},

Package (0x06)// P-State 2
{
2328, // f in MHz
60000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000061A, // value written to PERF_CTL; fid=6, vid=26
0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
},
})
}

Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06) {

Name (_PPC, 0x00)

Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},

ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})

Name (_PSS, Package (0x03)
{
Package (0x06)// P-State 0
{
3104, // f in MHz
75000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x00000820, // value written to PERF_CTL; fid=8, vid=32
0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
},

Package (0x06)// P-State 1
{
2716, // f in MHz
65000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000071C, // value written to PERF_CTL; fid=7, vid=28
0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
},

Package (0x06)// P-State 2
{
2328, // f in MHz
60000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000061A, // value written to PERF_CTL; fid=6, vid=26
0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
},
})
}


Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06) {

Name (_PPC, 0x00)

Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},

ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})

Name (_PSS, Package (0x03)
{
Package (0x06)// P-State 0
{
3104, // f in MHz
75000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x00000820, // value written to PERF_CTL; fid=8, vid=32
0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
},

Package (0x06)// P-State 1
{
2716, // f in MHz
65000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000071C, // value written to PERF_CTL; fid=7, vid=28
0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
},

Package (0x06)// P-State 2
{
2328, // f in MHz
60000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000061A, // value written to PERF_CTL; fid=6, vid=26
0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
},
})
}
..... same for all other CPUx
_linenums:0'>Scope (\_PR){ Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) { Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (<strong class='bbc'>_PSS</strong>, Package (0x03) { Package (0x06)// <strong class='bbc'>P-State 0</strong> { 3104, // f in MHz 75000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000820, // value written to PERF_CTL; fid=8, vid=32 0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32 }, Package (0x06)// <strong class='bbc'>P-State 1</strong> { 2716, // f in MHz 65000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000071C, // value written to PERF_CTL; fid=7, vid=28 0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28 }, Package (0x06)// P-State 2 { 2328, // f in MHz 60000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000061A, // value written to PERF_CTL; fid=6, vid=26 0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26 }, }) } Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06) { Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x03) { Package (0x06)// P-State 0 { 3104, // f in MHz 75000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000820, // value written to PERF_CTL; fid=8, vid=32 0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32 }, Package (0x06)// P-State 1 { 2716, // f in MHz 65000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000071C, // value written to PERF_CTL; fid=7, vid=28 0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28 }, Package (0x06)// P-State 2 { 2328, // f in MHz 60000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000061A, // value written to PERF_CTL; fid=6, vid=26 0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26 }, }) } Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06) { Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x03) { Package (0x06)// P-State 0 { 3104, // f in MHz 75000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000820, // value written to PERF_CTL; fid=8, vid=32 0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32 }, Package (0x06)// P-State 1 { 2716, // f in MHz 65000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000071C, // value written to PERF_CTL; fid=7, vid=28 0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28 }, Package (0x06)// P-State 2 { 2328, // f in MHz 60000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000061A, // value written to PERF_CTL; fid=6, vid=26 0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26 }, }) }..... same for all other CPUx

There are no _PSS entries in my ssdt-0, because my BIOS (GA-EP35-DS3) hasnt them included , thats the reason i will add them.

Thanks

For users who want to help i attached my extracted ssdt-0 (only one ssdt in my bios!).

Attached Files



#142
ApexDE

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@ kdawg

@ formerlyknownas

Regarding the problem of EHCI Ports not sleeping: I managed to make a DSDT Patch which allows EHCI Ports to sleep properly! http://www.insanelym...p...t&p=1240686

#143
kdawg

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@ kdawg

@ formerlyknownas

Regarding the problem of EHCI Ports not sleeping: I managed to make a DSDT Patch which allows EHCI Ports to sleep properly! http://www.insanelym...p...t&p=1240686



YOU ROCK!!!! Was it just trial and error? I feel like I should pay you money or something. :(

Anyway I tried it out and it works on my GA-EP45-UD3P. No need for Slice's kext! Thanks ApedDE.

#144
Ianxxx

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My code looks different where do I put the device id etc?




Device (USB0)
			 {
				 Name (_ADR, 0x001D0000)
				 Method (_S3D, 0, NotSerialized)
 
				 {
					 If (LEqual (OSFL, 0x02))
					 {
						 Return (0x02)
					 }
 
					 Return (0x03)
				 }
 
				 Name (_PRW, Package (0x02)
				 {
					 0x03, 
					 One
				 })
			 }



Problem solved!

#145
ApexDE

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Is there a SSDT Thread already? I couldn't find one. I would like to dip a bit deeper into this, as i need to run AppleIntelCPUPowermanagement.kext for proper Sleep (SleepEnabler doesn't work good for me cause my DVD Drive {censored} around)

#146
kdawg

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Is there a SSDT Thread already? I couldn't find one. I would like to dip a bit deeper into this, as i need to run AppleIntelCPUPowermanagement.kext for proper Sleep (SleepEnabler doesn't work good for me cause my DVD Drive {censored} around)


I tried starting one in the xLabs but there aren't a lot of DSDT'ers there. Mostly speedstepping via kexts/kernels.

Try these:
http://www.insanelym...p?showforum=163
http://www.insanelym...howtopic=145792

Good references:
http://s2.enemy.org/...edstep8.04.html
http://www.ztex.de/m...c2ctl.e.html#c1

FormerlyKnownAs and I have spent a lot of time trying to achieve this via DSDT. SpeedStepping is doable but c-states are another thing.

#147
ApexDE

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@ kdawg

Thanks for the heads-up ;) I would be rather more interested in working C-States, as they are much more powersaving than Speedstepping IMHO. No one managed to get C-State-Control working?

#148
kdawg

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@ kdawg

Thanks for the heads-up -_- I would be rather more interested in working C-States, as they are much more powersaving than Speedstepping IMHO. No one managed to get C-State-Control working?



Not via DSTD alone. I have a Dell Mini 9 I was working on and I have to use VoodooPower. FKA and I are unable to retrieve working c-states from our boards, believing they don't exist. I'm sure it's possible we just haven't figured it out yet.

Mine and FKA DSDTs are in this thread somewhere. Take a peek to see where we ended up.

#149
tuxianer

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id doesn't work for my EP35-DS3: http://redirectingat.....com/f72848271

#150
kdawg

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id doesn't work for my EP35-DS3: http://redirectingat.....com/f72848271


That's because you have a EP35(ICH9) board which isn't natively supported by Apple. So you might as well use Slice's IOUSBFamily.kext

#151
tuxianer

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Oh sorry I have misunderstood the totorial and inserted my device-ids correctly. But I have to fake them. The problem is that I have 8 devices in ioregestry Explorer.

So I have to change:

1A: 2937 ----> 3A37
1D: 2934 ----> 3A34
1D,1: 2935 --> 3A35
1D,2: 2936 --> 3A36
1A,1: 2938 --> 3A38
1A,2: 2939 --> 3A39

Thes ones are not named in the first post so tried this but they don't work. USB Bus is regcognized correct as integrated. But the USB High Speed Bus is still expansion slot.:
1D,7: 293A --> 3A3A
1A,7: 293C --> 3A3C

And is 10.5.7 really necessary?I have attached my DSDT for USB and the fixed one.

Attached Files



#152
ApexDE

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@ P35 Mainboard Users

It seems that P35 Users need to patch the USB-Device-IDs too (see first post in this thread). If you have issues with the EHCI Sleep-Fix, check if you patched the USB Device-IDs too. P45 Users just need the EHCI-Fix as they already have the correct USB Device-IDs. Wake with USB Mouse should work for P35 Users too, after applying the USB Device-ID Patches.

Good Luck, and report back here!


EDIT: Combining both Patches (device-id and ehci fix) is a bit tricky, so i post the USBE and USE2 sections here:

USBE:
Device (USBE)
			{
				Name (_ADR, 0x001D0007)
				Method (_S3D, 0, NotSerialized)
				{
					If (LEqual (OSFL, 0x02))
					{
						Return (0x02)
					}

					Return (0x03)
				}

				Name (_PRW, Package (0x02)
				{
					0x0D, 
					One
				})

				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x06)
						{
							"device-id",
							Buffer (0x04)
							{
								0x3A, 0x3A, 0x00, 0x00
							},
								 "AAPL,clock-id",
								 Buffer (0x01)
								 {
									 0x01
								 },
								 "device_type",
								 Buffer (0x05)
								 {
									"EHCI"
								 }

						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
 
			}


USE2:
Device (USE2)
			{
				Name (_ADR, 0x001A0007)
				Method (_S3D, 0, NotSerialized)
				{
					If (LEqual (OSFL, 0x02))
					{
						Return (0x02)
					}

					Return (0x03)
				}

				Name (_PRW, Package (0x02)
				{
					0x0D, 
					One
				})

				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x06)
						{
							"device-id",
							Buffer (0x04)
							{
								0x3C, 0x3A, 0x00, 0x00
							},
								 "AAPL,clock-id",
								 Buffer (0x01)
								 {
									 0x02
								 },
								 "device_type",
								 Buffer (0x05)
								 {
									"EHCI"
								 }

						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}

			}




Untested, as i have no EP35 Board :D Someone test and report back.

#153
Cathul

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@ P35 Mainboard Users

It seems that P35 Users need to patch the USB-Device-IDs too (see first post in this thread). If you have issues with the EHCI Sleep-Fix, check if you patched the USB Device-IDs too. P45 Users just need the EHCI-Fix as they already have the correct USB Device-IDs. Wake with USB Mouse should work for P35 Users too, after applying the USB Device-ID Patches.

Good Luck, and report back here!


I have a Gigabyte GA-P35-DS3 Rev. 1.0 with a patched DSDT.aml. All USB ports are reported as internal, but i think i have to switch on the bios flag for wake up by mouse.
Will test it as soon as i'm back home again from work.

edit: nope, didn't work with my USB mouse and keyboard.

#154
tuxianer

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what is the advantage in patching the sata ports in dsdt?

#155
FKA

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Hi
i want to add my P-States into my dsdt.dsl , not in an extra ssdt-x. aml.
The changes(adds) in the DSDT cpu part are no problem, but i have a few questions around adding P-State tables in the CPU part of dsdt.dsl.

my extracted ssdt-0 (only one ssdt in my bios!).


Hi mitch_de

Firstly I think you will find 4 other SSDT tables if you extract in Windows using Everest or in linux with acpidump (apologies if you have already done this.)

There are two ways to add the p-states to DSDT. You can add them to PR part of DSDT like so:

/* * Intel ACPI Component Architecture * AML Disassembler version 20080926 * * Disassembly of /Users/Dave/Documents/EP35DS4 OSX Install Files/DSDT Files/DSDT.aml,  * * * Original Table Header: *     Signature        "DSDT" *     Length           0x00004D8D (19853) *     Revision         0x01 **** ACPI 1.0, no 64-bit math support *     Checksum         0x1D *     OEM ID           "GBT   " *     OEM Table ID     "GBTUACPI" *     OEM Revision     0x00001000 (4096) *     Compiler ID      "INTL" *     Compiler Version 0x20080926 (537397542) */DefinitionBlock ("/UX Install Files/DSDT Files/DSDT.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000){    Scope (_PR)    {        Processor (CPU0, 0x00, 0x00000410, 0x06)        {            Name (_PPC, Zero)            Name (_PCT, Package (0x02)            {                ResourceTemplate ()                {                    Register (FFixedHW,                         0x10,               // Bit Width                        0x00,               // Bit Offset                        0x0000000000000199, // Address                        ,)                },                 ResourceTemplate ()                {                    Register (FFixedHW,                         0x10,               // Bit Width                        0x00,               // Bit Offset                        0x0000000000000198, // Address                        ,)                }            })            Name (_PSS, Package (0x03)            {                Package (0x06)                {                    0x0C20,                     0x000124F8,                     0x0A,                     0x0A,                     0x0820,                     0x0820                },                 Package (0x06)                {                    0x0A9C,                     0xFDE8,                     0x0A,                     0x0A,                     0x071C,                     0x071C                },                 Package (0x06)                {                    0x0918,                     0xEA60,                     0x0A,                     0x0A,                     0x061A,                     0x061A                }            })        }etc........

Or if you find PSS in SSDT tables (the 4 i believe you are missing.) you can add all 5 SSDT tables to the end of DSDT as described here then amend NPSS and SPSS values to suite you.

I went with the second method because I wanted to add CST tables from MP3,1 SSDT and for the life of me I couldn't manage to incorporate the MP3,1 CST and get the DSDT.dsl to compile with my PSS values at the beginning of my DSDT.

I have to addmit I don't know where to see p-state info in ioreg.

Here are two DSDT examples

Just p-state data added to DSDT Attached File  DSDT_P_state_only.dsl.zip   14.13KB   20 downloads

SSDT appended to end of DSDT Attached File  DSDT01_09_09.dsl.zip   15.37KB   22 downloads

I hope this helps.


**EDIT**
Here are my SSDT tables:
Attached File  GA_EP35_DS4_SSDT.zip   5.82KB   22 downloads

D.

#156
kdawg

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Hi mitch_de

Firstly I think you will find 4 other SSDT tables if you extract in Windows using Everest or in linux with acpidump (apologies if you have already done this.)

There are two ways to add the p-states to DSDT. You can add them to PR part of DSDT like so:

/* * Intel ACPI Component Architecture * AML Disassembler version 20080926 * * Disassembly of /Users/Dave/Documents/EP35DS4 OSX Install Files/DSDT Files/DSDT.aml,  * * * Original Table Header: *     Signature        "DSDT" *     Length           0x00004D8D (19853) *     Revision         0x01 **** ACPI 1.0, no 64-bit math support *     Checksum         0x1D *     OEM ID           "GBT   " *     OEM Table ID     "GBTUACPI" *     OEM Revision     0x00001000 (4096) *     Compiler ID      "INTL" *     Compiler Version 0x20080926 (537397542) */DefinitionBlock ("/UX Install Files/DSDT Files/DSDT.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000){    Scope (_PR)    {        Processor (CPU0, 0x00, 0x00000410, 0x06)        {            Name (_PPC, Zero)            Name (_PCT, Package (0x02)            {                ResourceTemplate ()                {                    Register (FFixedHW,                         0x10,               // Bit Width                        0x00,               // Bit Offset                        0x0000000000000199, // Address                        ,)                },                 ResourceTemplate ()                {                    Register (FFixedHW,                         0x10,               // Bit Width                        0x00,               // Bit Offset                        0x0000000000000198, // Address                        ,)                }            })            Name (_PSS, Package (0x03)            {                Package (0x06)                {                    0x0C20,                     0x000124F8,                     0x0A,                     0x0A,                     0x0820,                     0x0820                },                 Package (0x06)                {                    0x0A9C,                     0xFDE8,                     0x0A,                     0x0A,                     0x071C,                     0x071C                },                 Package (0x06)                {                    0x0918,                     0xEA60,                     0x0A,                     0x0A,                     0x061A,                     0x061A                }            })        }etc........

Or if you find PSS in SSDT tables (the 4 i believe you are missing.) you can add all 5 SSDT tables to the end of DSDT as described here then amend NPSS and SPSS values to suite you.

I went with the second method because I wanted to add CST tables from MP3,1 SSDT and for the life of me I couldn't manage to incorporate the MP3,1 CST and get the DSDT.dsl to compile with my PSS values at the beginning of my DSDT.

I have to addmit I don't know where to see p-state info in ioreg.

Here are two DSDT examples

Just p-state data added to DSDT Attached File  DSDT_P_state_only.dsl.zip   14.13KB   20 downloads

SSDT appended to end of DSDT Attached File  DSDT01_09_09.dsl.zip   15.37KB   22 downloads

I hope this helps.


**EDIT**
Here are my SSDT tables:
Attached File  GA_EP35_DS4_SSDT.zip   5.82KB   22 downloads

D.



In case anyone was interested where the DSDT SSDT info lives in the ioreg.

Attached File  SSDT_ioreg.jpg   121.49KB   112 downloads

#157
tuxianer

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does anyone has a working wake up by keyboard with a P35 board?

#158
ApexDE

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OK, the "EHCI-controller-unload" fix does work on P35 Boards, if the device-ids of the UHCI Devices are patched to ICH10, check post #1. Sleep and Wake via Mouse does work (Mouse directly on Mainboard USB Port)

Confirmed and working on a P35 Board :thumbsup_anim:


NOCHMAL:

If you are using a P35 Board: the UHCI Devices MUST be patched using the method described in post #1. Then change the USBE and USE2 like this http://www.insanelym...p...t&p=1247462


If you have a P45 Board, you just need the USBE and USE2 Fixes WITHOUT device-id injection.

#159
tuxianer

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OK, the "EHCI-controller-unload" fix does work on P35 Boards, if the device-ids of the UHCI Devices are patched to ICH10, check post #1. Sleep and Wake via Mouse does work (Mouse directly on Mainboard USB Port)

Confirmed and working on a P35 Board :)


NOCHMAL:

If you are using a P35 Board: the UHCI Devices MUST be patched using the method described in post #1. Then change the USBE and USE2 like this http://www.insanelym...p...t&p=1247462


If you have a P45 Board, you just need the USBE and USE2 Fixes WITHOUT device-id injection.


Wake up via mous or keyboard doesn't work for me. When the pc turns into sleep the mous led switches out and when I click it turns on again. But no wake up.

#160
FKA

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Wake up via mous or keyboard doesn't work for me. When the pc turns into sleep the mous led switches out and when I click it turns on again. But no wake up.


Hi Apex

Many thanks for this.
It does get rid of the AppleUSBEHCI[0x6838800]::CheckSleepCapability - controller will be unloaded across sleep message

but I still need slice's USB kext for deep sleep.

D





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