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GA-EX58 and GA-X58A DSDT native power management modifications, lower CPU temperatures, turbo plus one clock ratio, sleep, etcetera
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This guide applies to both the GA-EX58 and GA-X58A series of Gigabyte MBs.
Differences are noted in Audio (item 14) and Network (item 18).

I've made my Gigabyte GA-EX58-UD5 functionally as close to a single processor MacPro4,1 as possible, and in some ways it's better than the Apple hardware that can't be over clocked, has only four memory slots instead of six, has only one analog line out instead of four, and lacks external SATA ports.
My 4 Ghz Geekbench score of 14124 is higher than that of the 2.26 GHz dual processor Apple hardware MacPro4,1.

Using a DSDT.aml can bring you closer to actual Apple hardware functionality;
- No CMOS reset after reboot without ElliottForceLegacyRTC.kext or similar
- Audio without additional kexts (Realtek ALC889A only)
- Sleep using native power management without SleepEnabler.kext
- Lower CPU temperatures using native power management without NullCPUPowerManagement.kext
- Turbo plus one clock ratio
- Shutdown without EvOreboot.kext or similar
- Enable the power button to sleep and wake the computer

Native power management will be seen in kernel.log during boot;
kernel[0]: AppleIntelCPUPowerManagementClient: ready
kernel[0]: AppleIntelCPUPowerManagement: Turbo Ratios 1112
kernel[0]: AppleIntelCPUPowerManagement: initialization complete

What `Turbo Ratios 1112' means is that one core will clock to BCLK times 22, when the other three cores aren't being utilized.
For a 2.66 GHz i7 920 or Xeon W3520 the multiplier for turbo is 21, and this will give BCLK times 22.
Page three of Gigabyte's corei7_x58_bios_guide.pdf alludes to this functionality.

MSR Tools can be used to see the CPU speed fluctuations (32 bit).
Use it with caution, as there is a chance that it will lock up and cause a system hang if force quit.
The following example is with an i7 920 or Xeon W3520 CPU, BCLK frequency changed from 133 to 185, and CPU clock ratio set to the standard 20 with turbo enabled.
x20;
Max Frequency: 3.70 GHz
Actual Frequency: 3.70 GHz (100%)
x21;
Max Frequency: 3.70 GHz
Actual Frequency: 3.89 GHz (105%)
x22;
Max Frequency: 3.70 GHz
Actual Frequency: 4.07 GHz (110%)

The mark-i application can also be used (32 and 64 bit), see post 692;
http://www.insanelymac.com/forum/index.php...6771&st=691

Speed step;

This will reduce clock speed as low as a x12 multiplier under idle conditions.
Enabling native power management with DSDT modifications will bring lower CPU temperatures, and speed step will go even lower, but only if using the Dynamic Vcore (DVID) feature of the BIOS.
DVID was added in version F9m of the GA-EX58-UD5 BIOS, check the Gigabyte BIOS beta thread for when it was added in the other models.

10.6.0 and 10.6.1:
Use MP41SpeedStepFix.kext.

10.6.0 through 10.6.3:
Save a copy of /System/Library/Extensions/IOPlatformPluginFamily.kext, add the PLimitDict and StepDataDict sections from /System/Library/Extensions/IOPlatformPluginFamily.kext/Contents/PlugIns/ACPI_SMC_PlatformPlugin.kext/Contents/Resources/MacPro3_1.plist to the same location in MacPro4_1.plist, and change the two key values from MacPro3,1 to MacPro4,1.
Watch the OS update it's extensions cache and any helper partitions in system.log and restart.

10.6.3 with Mac Pro Audio Update 1.1 and 10.6.4:
Apple has enabled speed step in an updated MacPro4_1.plist.

Idle temperature comparison:
Idle CPU temperatures at 4.3 GHz (turbo disabled) and 19 C ambient; 42-46 C
Idle CPU temperatures at 4.3 GHz (turbo disabled) with a speed step MacPro4_1.plist, and 19 C ambient; 42-46 C
Idle CPU temperatures at 4.3 GHz (turbo disabled) with a speed step MacPro4_1.plist, DVID, and 19 C ambient; 35-39 C

Unbuffered ECC memory;

If you have a Xeon CPU, you can use unbuffered error correcting code (ECC) memory, just like the Apple hardware uses.
Gigabyte doesn't list this as supported, but it works fine.

Create a Memtest86+ boot CD and it will show the following with a Xeon CPU and unbuffered ECC memory;
Chipset : NHM IMC (ECC : Detect / Correct) Scrub+

It will show the following with a Xeon or i7 CPU and non ECC memory;
Chipset : NHM IMC (ECC : Disabled)

Set the following in /System/Library/SystemProfiler/SPMemoryReporter.spreporter/Contents/Resources/English.lproj/Localizable.strings to correct the cosmetic misreporting of ECC as disabled in System Profiler:Hardware:Memory;
"dimm_type" = "Type";"DDR3"="DDR3 ECC";
"ecc_disabled" = "Disabled";"Disabled"="Enabled";

For confirmation that it's working, here's what you'll see in kernel.log if a cosmic ray flips a bit, or if you've over clocked your memory improperly;
Aug 13 18:23:06 mac05 kernel[0]: AppleTyMCEDriver ReadCorrectable : Detected 1 errors on channel 2 dimm 1 package 0
Aug 13 18:23:16 mac05 kernel[0]: AppleTyMCEDriver ReadCorrectable : Detected 1 errors on channel 1 dimm 0 package 0
Aug 13 18:23:19 mac05 kernel[0]: AppleTyMCEDriver ReadCorrectable : Detected 1 errors on channel 1 dimm 0 package 0

Here's what you'll see in System Profiler:Hardware:Memory;
CODE

Memory Slots:

ECC: Enabled

Bank0/1/A0:

Size: 2 GB
Type: DDR3 ECC
Speed: 1640 MHz
Status: OK
Manufacturer: Kingston
Part Number: 9905413-009.A00LF
Serial Number: 0x66cceebc

Bank2/3/A1:

Size: 2 GB
Type: DDR3 ECC
Speed: 1640 MHz
Status: OK
Manufacturer: Kingston
Part Number: 9905413-009.A00LF
Serial Number: 0x6accadbc

Bank4/5/A2:

Size: 2 GB
Type: DDR3 ECC
Speed: 1640 MHz
Status: OK
Manufacturer: Kingston
Part Number: 9905413-009.A00LF
Serial Number: 0x66cc91bc

Bank6/7/A3:

Size: 2 GB
Type: DDR3 ECC
Speed: 1640 MHz
Status: ECC Errors
ECC Correctable Errors: 2
Manufacturer: Kingston
Part Number: 9905413-009.A00LF
Serial Number: 0x6acc64bc

Bank8/9/A4:

Size: 2 GB
Type: DDR3 ECC
Speed: 1640 MHz
Status: ECC Errors
ECC Correctable Errors: 1
Manufacturer: Kingston
Part Number: 9905413-009.A00LF
Serial Number: 0x69ccecbc

Bank10/11/A5:

Size: 2 GB
Type: DDR3 ECC
Speed: 1640 MHz
Status: OK
Manufacturer: Kingston
Part Number: 9905413-009.A00LF
Serial Number: 0x66cce8bc

DSDT modifications;

The easiest way to create a DSDT.aml is to reboot without a DSDT.aml, using fakesmc.kext, NullCPUPowerManagement.kext to not KP, ElliottForceLegacyRTC.kext to not reset the CMOS, and then use the DSDTSE application to extract the dsdt.dsl, edit it and compile it into dsdt.aml.
Another way is to reboot without a DSDT.aml, with the three kexts, and get an unmodified dsdt.dat by running getDSDT.sh.
Run `./iasl -d dsdt.dat', edit dsdt.dsl with vi or similar, then get dsdt.aml from running `./iasl -ta dsdt.dsl'.
Either way, copy dsdt.aml to the bootloader's Extra folder as DSDT.aml.
The compiler changes 0x00 to Zero, 0x01 to One, removes some comments, shortens some hex, etc., so you will see differences when comparing dsdt.dsl and it's dsdt.aml in DSDTSE.

Save the clean dsdt.dsl derived from each BIOS that you use.
If the clean dsdt.dsl derived from the new BIOS is the same, then no modification to your original modified dsdt.dsl is needed.
GA-EX58-UD5 BIOS F9e added support for CPUs with more than four cores, and F9m added DVID.
Both resulted in additional code in the dsdt.dsl derived from them.
Also keep in mind that a BIOS setting could change the derived dsdt.dsl.
However, I've only seen the sleep setting do this so far.
When you derive dsdt.dsl from a BIOS set to S1(POS) sleep you get;
Name (\_S1, Package (0x04)
and
Name (\SS3, Package (0x04)
and
...
When you derive dsdt.dsl from a BIOS set to S3(STR) sleep you get;
Name (\SS1, Package (0x04)
and
Name (\_S3, Package (0x04)
and
...

If you have a GA-EX58-UD5 with an i7 920 or Xeon W3520, i7 930 or Xeon W3530, i7 950 or Xeon W3550, or i7 975 or Xeon W3580, you can use BIOS F9m through F12 and the attached DSDT.aml files (do 6 and 7).
or
If you have a GA-EX58-UD5 and you are using the Chameleon-Mozodojo bootloader you can use BIOS F9m through F12 and the attached standard PR scope DSDT.aml files (don't do 6, do 7 and 20).
or
Make your own if have a different GA-EX58 or GA-X58A MB.

Is it possible to use a DSDT.aml created from a dsdt.dsl from a different MB?
No, because there are significant differences in the unmodified dsdt.dsl file from each GA-EX58 model.
GA-X58A-UD7 rev 1.0 and GA-X58A-UD3R rev 1.0 differ only in the address base in `Device (PCI0.EXPL)'.
GA-X58A-UD3R rev 2.0 is significantly different from rev 1.0.
GA-X58A-UD5 rev 2.0 is significantly different from rev 1.0.
GA-X58A-UD3R rev 2.0 is significantly different from GA-X58A-UD5 rev 2.0.
I'm looking for an unmodified dsdt.dsl from the following boards (*);
GA-EX58-EXTREME *
GA-EX58-UD5
GA-EX58-UD4P
GA-EX58-UD4 *
GA-EX58-DS4 *
GA-EX58-UD3R revision 1.7 *
GA-EX58-UD3R revision 1.6
GA-EX58-UD3R revision 1.0
GA-EX58-UD3R-SLI *
GA-X58A-UD9 *
GA-X58A-UD7 revision 2.0 *
GA-X58A-UD7 revision 1.0
GA-X58A-UD5 revision 2.0
GA-X58A-UD5 revision 1.0
GA-X58A-UD3R revision 2.0
GA-X58A-UD3R revision 1.0

The code in the following code boxes may loose their formatting with copy and paste.
The attached DSDT archives have both dsdt.dsl and DSDT.aml files.
Open the dsdt.dsl (or do `./iasl -d DSDT.aml' to get dsdt.dsl), then copy and paste from that.

1. To fix the Local0 compile error, add quotation marks to the `Scope (\_SI)' section.
The dsdt.dsl won't compile without this modification.

original:
CODE

Scope (\_SI)
{
Method (_MSG, 1, NotSerialized)
{
Store (Local0, Local0)
}

Method (_SST, 1, NotSerialized)
{
Store (Local0, Local0)
}
}
modified:
CODE

Scope (\_SI)
{
Method (_MSG, 1, NotSerialized)
{
Store ("Local0", Local0)
}

Method (_SST, 1, NotSerialized)
{
Store ("Local0", Local0)
}
}

2. To fix the _WAK compile warning, add to the end of the `Method (\_WAK, 1, NotSerialized)' section.

original:
CODE

Notify (\_SB.PCI0.USB0, 0x00)
Notify (\_SB.PCI0.USB1, 0x00)
Notify (\_SB.PCI0.USB2, 0x00)
Notify (\_SB.PCI0.USB3, 0x00)
Notify (\_SB.PCI0.USB4, 0x00)
Notify (\_SB.PCI0.USB5, 0x00)
}
modified:
CODE

Notify (\_SB.PCI0.USB0, 0x00)
Notify (\_SB.PCI0.USB1, 0x00)
Notify (\_SB.PCI0.USB2, 0x00)
Notify (\_SB.PCI0.USB3, 0x00)
Notify (\_SB.PCI0.USB4, 0x00)
Notify (\_SB.PCI0.USB5, 0x00)
Return (Package (0x02)
{
Zero,
Zero
})
}

3. To solve the CMOS issue that resets the BIOS back to default, in `Device (RTC)' change the the two instances of 0x04 to 0x02.
RTC stands for Real Time Clock.
There's a good explanation of why the IO segment's length needs to be reduced at netkas's site.
The ACPI (Advanced Configuration & Power Interface) specifications are at http://www.acpi.info/.
I'd suggest looking at ACPIspec40.pdf, although Gigabyte seems to be 1.0 in DSDT;
* Revision 0x01 **** ACPI 1.0, no 64-bit math support
There's also some good information at http://www.acpica.org/documentation/.

original:
CODE

Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (ATT0, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x04, // Length
)
IRQNoFlags ()
{8}
})
Name (ATT1, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x04, // Length
)
})
modified:
CODE

Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (ATT0, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x02, // Length
)
IRQNoFlags ()
{8}
})
Name (ATT1, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x00, // Alignment
0x02, // Length
)
})

4. To allow layout-id, etc. insertion modifications to DSDT, add the following before the `Method (\_WAK, 1, NotSerialized)' section.

CODE

Method (DTGP, 5, NotSerialized)
{
If (LEqual (Arg0, Buffer (0x10)
{
/* 0000 */ 0xC6, 0xB7, 0xB5, 0xA0, 0x18, 0x13, 0x1C, 0x44,
/* 0008 */ 0xB0, 0xC9, 0xFE, 0x69, 0x5E, 0xAF, 0x94, 0x9B
}))
{
If (LEqual (Arg1, One))
{
If (LEqual (Arg2, Zero))
{
Store (Buffer (One)
{
0x03
}, Arg4)
Return (One)
}

If (LEqual (Arg2, One))
{
Return (One)
}
}
}

Store (Buffer (One)
{
0x00
}, Arg4)
Return (Zero)
}

5. The BIOS has capability for up to 16 threads, but only 8 and 12 thread CPUs have been released to date.
For CPU0 through CPU7 for the 8 thread CPUs, or CPU0 through CPUB for the 12 thread i7 980 or Xeon W3680, make changes to pass the CStates to OS X.
This is only needed when clocked over a certain point (148x20 or 2.96 GHz for a i7 920 or Xeon W3520 CPU), as the OS doesn't see the CStates available to it, even with all energy saving options enabled in the BIOS's Advanced CPU Features section.
If you convert the hexadecimal you will find that the PStates represent the default clock of your CPU, but it won't down clock your CPU if over clocked, and is what the BIOS makes available to the OS at default or over clock.

Note:
Don't add this section if you are using the Chameleon-Mozodojo bootloader as it will make CStates available to the OS (don't do 6, do 7 and 20).

If you have a different CPU your specific PStates can be obtained from running getSSDT5.sh to get SSDT-0.dsl, or from using DSDTSE.
Do this after rebooting at default clock with fakesmc.kext, NullCPUPowerManagement.kext to not KP, ElliottForceLegacyRTC.kext to not reset the CMOS, EIST, C1E and C3/C6/C7 States enabled, and no DSDT.aml.

I'm looking for an SSDT-0.dsl from the following CPUs (*);
2.66 GHz: i7 920 or Xeon W3520
2.80 GHz: i7 930 or Xeon W3530
2.93 GHz: i7 940 or Xeon W3540 *
3.06 GHz: i7 950 or Xeon W3550
3.20 GHz: i7 960 or Xeon W3565
3.20 GHz: i7 965 or Xeon W3570 *
3.33 GHz: i7 975 or Xeon W3580
3.33 GHz: i7 980 or Xeon W3680

original:
CODE

Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06) {}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06) {}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06) {}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06) {}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06) {}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06) {}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06) {}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 10 PState i7 920 and Xeon W3520:
CODE

Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},

0x03,
0x0060,
0x0000015E
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},

0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},

ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0A)
{
Package (0x06)
{
0x00000A65,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},

Package (0x06)
{
0x00000A64,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},

Package (0x06)
{
0x000009DF,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},

Package (0x06)
{
0x0000095A,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},

Package (0x06)
{
0x000008D5,
0x00014438,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},

Package (0x06)
{
0x00000850,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},

Package (0x06)
{
0x000007CB,
0x0000F618,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},

Package (0x06)
{
0x00000746,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},

Package (0x06)
{
0x000006C1,
0x0000B798,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},

Package (0x06)
{
0x0000063C,
0x0000A7F8,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 11 PState i7 930 and Xeon W3530 (added 20100425):
CODE

Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},

0x03,
0x0060,
0x0000015E
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},

0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},

ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0B)
{
Package (0x06)
{
0x00000AEA,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},

Package (0x06)
{
0x00000AE9,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},

Package (0x06)
{
0x00000A64,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},

Package (0x06)
{
0x000009DF,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},

Package (0x06)
{
0x0000095A,
0x00014438,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},

Package (0x06)
{
0x000008D5,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},

Package (0x06)
{
0x00000850,
0x0000F618,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},

Package (0x06)
{
0x000007CB,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},

Package (0x06)
{
0x00000746,
0x0000CB20,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},

Package (0x06)
{
0x000006C1,
0x0000A7F8,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},

Package (0x06)
{
0x0000063C,
0x00009C40,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 13 PState i7 950 and Xeon W3550 (added 20091222):
CODE

Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},

0x03,
0x0060,
0x0000015E
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},

0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},

ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0D)
{
Package (0x06)
{
0x00000BF4,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000018,
0x00000018
},

Package (0x06)
{
0x00000BF3,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000017,
0x00000017
},

Package (0x06)
{
0x00000B6E,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},

Package (0x06)
{
0x00000AE9,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},

Package (0x06)
{
0x00000A64,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},

Package (0x06)
{
0x000009DF,
0x00014438,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},

Package (0x06)
{
0x0000095A,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},

Package (0x06)
{
0x000008D5,
0x00010D88,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},

Package (0x06)
{
0x00000850,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},

Package (0x06)
{
0x000007CB,
0x0000CB20,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},

Package (0x06)
{
0x00000746,
0x0000B798,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},

Package (0x06)
{
0x000006C1,
0x00009C40,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},

Package (0x06)
{
0x0000063C,
0x00008CA0,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 15 PState i7 975 and Xeon W3580 (added 20100109):
CODE

Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},

0x03,
0x0060,
0x0000015E
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},

0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},

ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0F)
{
Package (0x06)
{
0x00000CFE,
0x000493E0,
0x0000000A,
0x0000000A,
0x0000001A,
0x0000001A
},

Package (0x06)
{
0x00000CFD,
0x000493E0,
0x0000000A,
0x0000000A,
0x00000019,
0x00000019
},

Package (0x06)
{
0x00000C78,
0x0003C4D8,
0x0000000A,
0x0000000A,
0x00000018,
0x00000018
},

Package (0x06)
{
0x00000BF3,
0x00036B00,
0x0000000A,
0x0000000A,
0x00000017,
0x00000017
},

Package (0x06)
{
0x00000B6E,
0x00031510,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},

Package (0x06)
{
0x00000AE9,
0x0002C6F0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},

Package (0x06)
{
0x00000A64,
0x00027CB8,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},

Package (0x06)
{
0x000009DF,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},

Package (0x06)
{
0x0000095A,
0x0001C520,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},

Package (0x06)
{
0x000008D5,
0x00018E70,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},

Package (0x06)
{
0x00000850,
0x00016378,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},

Package (0x06)
{
0x000007CB,
0x00013880,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},

Package (0x06)
{
0x00000746,
0x0000F230,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},

Package (0x06)
{
0x000006C1,
0x0000D6D8,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},

Package (0x06)
{
0x0000063C,
0x0000BB80,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06) {}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06) {}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06) {}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06) {}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}
modified for 15 PState i7 980 and Xeon W3680 (added 20100523):
Note;
10.6.3: Not fully supported by the OS, start with sasta's post 701;
http://www.insanelymac.com/forum/index.php...6771&st=700
10.6.4: Supported by the OS, but bootloader needs modification to prevent fast RTC;
http://www.tonymacx86.com/viewtopic.php?f=...de2487086daac8c
CODE

Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},

0x03,
0x0060,
0x0000015E
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},

0x01,
0x0001,
0x000003E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
0x0040,
0x000001F4
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},

0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},

ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0F)
{
Package (0x06)
{
0x00000CFE,
0x000493E0,
0x0000000A,
0x0000000A,
0x0000001A,
0x0000001A
},

Package (0x06)
{
0x00000CFD,
0x000493E0,
0x0000000A,
0x0000000A,
0x00000019,
0x00000019
},

Package (0x06)
{
0x00000C78,
0x0003C4D8,
0x0000000A,
0x0000000A,
0x00000018,
0x00000018
},

Package (0x06)
{
0x00000BF3,
0x00036B00,
0x0000000A,
0x0000000A,
0x00000017,
0x00000017
},

Package (0x06)
{
0x00000B6E,
0x00031510,
0x0000000A,
0x0000000A,
0x00000016,
0x00000016
},

Package (0x06)
{
0x00000AE9,
0x0002C6F0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},

Package (0x06)
{
0x00000A64,
0x00027CB8,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},

Package (0x06)
{
0x000009DF,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},

Package (0x06)
{
0x0000095A,
0x0001C520,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},

Package (0x06)
{
0x000008D5,
0x00018E70,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},

Package (0x06)
{
0x00000850,
0x00016378,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},

Package (0x06)
{
0x000007CB,
0x00013880,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},

Package (0x06)
{
0x00000746,
0x0000F230,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},

Package (0x06)
{
0x000006C1,
0x0000D6D8,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},

Package (0x06)
{
0x0000063C,
0x0000BB80,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU8, 0x08, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU9, 0x09, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPUA, 0x0A, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPUB, 0x0B, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPUC, 0x0C, 0x00000410, 0x06) {}
Processor (\_PR.CPUD, 0x0D, 0x00000410, 0x06) {}
Processor (\_PR.CPUE, 0x0E, 0x00000410, 0x06) {}
Processor (\_PR.CPUF, 0x0F, 0x00000410, 0x06) {}

6. To make the CPU changes work correctly, add the following to com.apple.Boot.plist (don't add if using the Chameleon-Mozodojo bootloader);

<key>DropSSDT</key>
<string>yes</string>

7. Identify your machine as MacPro4,1 in smbios.plist.
If you have updated to 10.6.4 your NVIDIA GPU performance has severely decreased, use MacPro3,1 instead as a workaround (start with post 865);
http://www.insanelymac.com/forum/index.php...6771&st=864

<key>SMproductname</key>
<string>MacPro4,1</string>

8. Use OrangeIconFix.kext to fix the orange drives seen in the Finder, and to make the drives show correctly as Intel ICH10 AHCI in System Profiler's Serial-ATA section, add the following to the `Device (IDE1)' section (put above `Device (PRIM)').

CODE

Method (_DSM, 4, NotSerialized)
{
Store (Package (0x02)
{
"device-id",
Buffer (0x04)
{
0x22, 0x3A, 0x00, 0x00
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}

9. Modify the `Device (PX40)' section so that AppleLPC.kext loads.
This is needed for native power management, and for the `Start up automatically after a power failure' option to appear in Energy Saver.
This must be checked or sleep will shut the computer down instead, unless 17 is also done.

The following is seen from running `OSX86 Tools Utility:View PCI Device/Vendor ID' on GA-EX58-UD5.
00:1f.0 ISA bridge [0601]: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller [8086:3a16]

The device-id should be one that's in /System/Library/Extensions/AppleLPC.kext/Contents/Info.plist (<string>pci8086,3a18</string>).

original:
CODE

Device (PX40)
{
Name (_ADR, 0x001F0000)
OperationRegion (PREV, PCI_Config, 0x08, 0x01)
Scope (\)
modified:
CODE

Device (PX40)
{
Name (_ADR, 0x001F0000)
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x02)
{
"device-id",
Buffer (0x04)
{
0x18, 0x3A, 0x00, 0x00
}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
OperationRegion (PREV, PCI_Config, 0x08, 0x01)
Scope (\)

10. Modify the `Device (HPET)' section so that AppleHPET.kext loads.
The AppleHPET kext needs to load so that the AppleIntelCPUPowerManagement and AppleIntelCPUPowerManagementClient kexts can load without KP.

original:
CODE

Device (HPET)
{
Name (_HID, EisaId ("PNP0103"))
Name (ATT3, ResourceTemplate ()
{
IRQNoFlags ()
{0}
IRQNoFlags ()
{8}
Memory32Fixed (ReadWrite,
0xFED00000, // Address Base
0x00000400, // Address Length
)
})
Name (ATT4, ResourceTemplate ()
{
})
Method (_STA, 0, NotSerialized)
{
If (LGreaterEqual (OSFX, 0x03))
{
If (HPTF)
{
Return (0x0F)
}
Else
{
Return (0x00)
}
}
Else
{
Return (0x00)
}
}

Method (_CRS, 0, NotSerialized)
{
If (LGreaterEqual (OSFX, 0x03))
{
If (HPTF)
{
Return (ATT3)
}
Else
{
Return (ATT4)
}
}
Else
{
Return (ATT4)
}
}
}
modified:
CODE

Device (HPET)
{
Name (_HID, EisaId ("PNP0103"))
Name (ATT3, ResourceTemplate ()
{
IRQNoFlags ()
{0}
IRQNoFlags ()
{8}
Memory32Fixed (ReadWrite,
0xFED00000, // Address Base
0x00000400, // Address Length
)
})
Name (ATT4, ResourceTemplate ()
{
})
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}

Method (_CRS, 0, NotSerialized)
{
Return (ATT3)
}
}

11. Remove the IRQ from the PIC and TMR devices to solve the audio stuttering problem.

original:
CODE

Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0020, // Range Minimum
0x0020, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IO (Decode16,
0x00A0, // Range Minimum
0x00A0, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IRQNoFlags ()
{2}
})
}
modified:
CODE

Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0020, // Range Minimum
0x0020, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IO (Decode16,
0x00A0, // Range Minimum
0x00A0, // Range Maximum
0x01, // Alignment
0x02, // Length
)
})
}
and
original:
CODE

Device (TMR)
{
Name (_HID, EisaId ("PNP0100"))
Name (ATT5, ResourceTemplate ()
{
IO (Decode16,
0x0040, // Range Minimum
0x0040, // Range Maximum
0x00, // Alignment
0x04, // Length
)
IRQNoFlags ()
{0}
})
modified;
CODE

Device (TMR)
{
Name (_HID, EisaId ("PNP0100"))
Name (ATT5, ResourceTemplate ()
{
IO (Decode16,
0x0040, // Range Minimum
0x0040, // Range Maximum
0x00, // Alignment
0x04, // Length
)
})

12. Change HID to CID in the `Device (PWRB)' section to enable the power button to sleep and wake the computer.
In BIOS set `ACPI Suspend Type' to `S3(STR)', this is the lower power suspend to RAM state.
Also set `Soft-Off by PWR-BTTN' to `Delay 4 Sec.', so less than four seconds will sleep (S3) or wake, and more than four seconds will shut down (S5).
`Allow power button to put the computer to sleep' must also be checked in Energy Saver.

original:
CODE

Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
Method (_STA, 0, NotSerialized)
{
Return (0x0B)
}
}
modified:
CODE

Device (PWRB)
{
Name (_CID, EisaId ("PNP0C0C"))
Method (_STA, 0, NotSerialized)
{
Return (0x0B)
}
}

13. Modify fakesmc.kext/Contents/Info.plist in two places with MacPro4,1 specific information (1.30f3 and smc-napa changed to 1.39f5 and smc-thurley).

original:
CODE

<key>REV </key>
<data>
ATAPAAAD
</data>
</dict>
<key>smc-compatible</key>
<string>smc-napa</string>
modified:
CODE

<key>REV </key>
<data>
ATkPAAAF
</data>
</dict>
<key>smc-compatible</key>
<string>smc-thurley</string>

14. Audio options.

VoodooHDA for all GA-X58A and GA-EX58 models;
http://forum.voodooprojects.org/index.php/board,10.0.html
and
http://forum.voodooprojects.org/index.php/board,13.0.html

GA-EX58-UD3R, GA-EX58-UD3R-SLI, GA-EX58-UD4 and GA-EX58-DS4 (Realtek ALC888);
10.6.0 through 10.6.2 (post 12):
http://www.insanelymac.com/forum/index.php...40941&st=11
10.6.3 and 10.6.4:
Use How_to_patch_AppleHDA.zip:
http://www.insanelymac.com/forum/index.php?showtopic=140941
or
Use already patched AppleHDA (for 10.6.4, post 850):
http://www.insanelymac.com/forum/index.php...6771&st=849
and
Use HDAEnabler.kext in Extensions.mkext:
http://www.insanelymac.com/forum/index.php?showtopic=213808
and
original:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
and
original:
CODE

Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
CODE

Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}

Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x03, 0x00, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}

GA-X58A-UD3R, GA-X58A-UD5, GA-X58A-UD7 and GA-X58A-UD9 (Realtek ALC889);
10.6.0 through 10.6.2 (post 677):
http://www.insanelymac.com/forum/index.php...0941&st=676
10.6.3 and 10.6.4:
Use How_to_patch_AppleHDA.zip:
http://www.insanelymac.com/forum/index.php?showtopic=140941
or
Use already patched AppleHDA (for 10.6.4, post 850):
http://www.insanelymac.com/forum/index.php...6771&st=849
and
Use Legacy889HDA.kext in Extensions.mkext (post 815):
http://www.insanelymac.com/forum/index.php...6771&st=814
and
original:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
and
original:
CODE

Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
CODE

Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}

Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x79, 0x03, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}

GA-EX58-UD4P, GA-EX58-UD5 and GA-EX58-EXTREME (Realtek ALC889A);
A outputs analog 2.0.
B outputs analog 2.0 and digital 5.1.
C outputs analog and digital 5.1.
D outputs analog 7.1
There are less sound assertion messages in kernel.log with B and C, and none with D.

A. To have 2.0 audio without any additional kext, make modifications to the `Method (_L0D, 0, NotSerialized)' section and the `Device (AZAL)' section.
Output is the green jack.
The layout-id 66 in hex is 0x42.

original:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
and
original:
CODE

Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
CODE

Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}

Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x42, 0x00, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}

or

B. Thanks to aschar1 for the 2.0 ALC889a.kext.

For 10.6.0 and 10.6.1 (post 388);
http://www.insanelymac.com/forum/index.php...0941&st=387

For 10.6.2 through 10.6.4 (post 457);
http://www.insanelymac.com/forum/index.php...6771&st=456

Updated DSDT modification to reduce the popping noise after wake, and eliminate it at boot (post 548);
http://www.insanelymac.com/forum/index.php...6771&st=547

To use ALC889a.kext in Extensions.mkext, make modifications to the `Method (_L0D, 0, NotSerialized)' section and the `Device (AZAL)' section.
Output is the green jack.
The layout-id 12 in hex is 0x0C.

original:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.AZAL, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
modified:
CODE

Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.USBE, 0x02)
Notify (\_SB.PCI0.USE2, 0x02)
Notify (\_SB.PWRB, 0x02)
Notify (\_SB.PCI0.HDEF, 0x02)
Notify (\_SB.PCI0.IGBE, 0x02)
}
and
original:
CODE

Device (AZAL)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}
}
modified:
CODE

Device (HDEF)
{
Name (_ADR, 0x001B0000)
Method (_PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x0D,
0x05
})
}

Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"layout-id",
Buffer (0x04)
{
0x0C, 0x00, 0x00, 0x00
},
"PinConfigurations",
Buffer (Zero) {}
}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}

or

C. Thanks to ANARCHiNTOSH for the AppleHDA 5.1 patcher (post 497);
http://www.insanelymac.com/forum/index.php...6771&st=496

or

D. Thanks to x.di for the 7.1 LegacyHDA.kext (post 511);
http://www.insanelymac.com/forum/index.php...6771&st=510

Update (post 686);
http://www.insanelymac.com/forum/index.php...6771&st=685

15. Having the driver for Temperature Monitor installed prevents idle sleep.
Setting `Avoid accessing drive sensors if user inactive:' in Temperature Monitor:Preferences:General:Disk Saver to a value greater than the `Computer sleep' value in Energy Saver doesn't change the behavior.
Thanks to kdawg for noting that iStat can be used instead, and that it doesn't prevent idle sleep if `Monitor S.M.A.R.T drive temps' is unchecked in the sensor section.
Various DVD drives prevent idle sleep, the solution may be to either uncheck `Put the hard disk(s) to sleep when possible' in Energy Saver, or to leave a DVD in the drive.
Another solution is to add the PenntNeu-script RIP.app in Accounts:<user>:Login Items.
To make this work I had to change main.scpt, although this has worked for others unmodified.

original:
CODE

if idleTime > systemSleepDelay then
tell application "System Events"
key code 58
end tell
tell application "System Events" to sleep
end if
modified:
CODE

if idleTime > systemSleepDelay then
do shell script "pmset sleepnow"
end if

16. (added 20091223) Thanks to mm67 for a modification that enables shutdown, so that EvOreboot.kext or similar isn't needed;
http://www.insanelymac.com/forum/index.php...2518&st=743 (start with post 744)

A kext would still be needed if you want restart functionality, unless you use Duvel300's patched boot, Asere's bootloader, or the Chameleon-Mozodojo bootloader;
http://www.insanelymac.com/forum/index.php...2518&st=870 (start with post 871)

Add the following before `OperationRegion (\AGPS, SystemIO, 0x0438, 0x04)'.
CODE

OperationRegion (PMRS, SystemIO, 0x0430, 0x01)
Field (PMRS, ByteAcc, NoLock, Preserve)
{
, 4,
SLPE, 1
}

and
In `Method (\_PTS, 1, NotSerialized)' change the following.

original:
CODE

If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
}
modified:
CODE

If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
Store (Zero, SLPE)
Sleep (0x10)
}


17. (added 20100103) Thanks to sr2, AudiSport, mm67, blackosx and [Master Chief|Unsubscribe Me|TheChief] for a modification that doesn't require `Allow power button to put the computer to sleep' to be checked for 9;
http://www.insanelymac.com/forum/index.php...6771&st=171 (post 172)
and
http://www.insanelymac.com/forum/index.php...2518&st=609 (start with post 610)

Add the following before `OperationRegion (PREV, PCI_Config, 0x08, 0x01)'.
CODE

OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
Field (LPC0, ByteAcc, NoLock, Preserve)
{
AG3E, 1
}

and
Change `Method (\_PTS, 1, NotSerialized)'.

original:
CODE

Method (\_PTS, 1, NotSerialized)
{
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG1)
OSTP ()
If (LEqual (Arg0, 0x01)) {}
If (LEqual (Arg0, 0x03)) {}
If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
}

If (LEqual (Arg0, 0x04))
{
If (LNot (PICF))
{
Sleep (0x64)
}
}
}
modified (includes 16):
CODE

Method (\_PTS, 1, NotSerialized)
{
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG1)
OSTP ()
If (LEqual (Arg0, 0x05))
{
Store (0x99, SMIP)
Store (One, \_SB.PCI0.PX40.AG3E)
Store (Zero, SLPE)
Sleep (0x10)
}
Else
{
Store (Zero, \_SB.PCI0.PX40.AG3E)
}
}


18. Network options.

All GA-EX58 and GA-X58A models;
Intel Gigabit CT Desktop Adapter - network adapter, Mfg. Part: EXPI9301CT.
It's $40 or less and uses Apple's IONetworkingFamily.kext/Contents/PlugIns/Intel82574L.kext.

GA-EX58-UD3R rev. 1.6 and 1.7 (Realtek RTL8111C);
The Realtek RTL8111C is recognized by Apple's IONetworkingFamily.kext/Contents/PlugIns/AppleRTL8169Ethernet.kext, and also as IOBuiltin=Yes.

GA-X58A-UD3R rev. 2.0, GA-X58A-UD5 rev. 2.0, GA-X58A-UD7 rev. 2.0 and GA-X58A-UD9 (Realtek RTL8111E);
The site doesn't list it, but running the RTGMac_v2.0.4 installer shows support for 10.6.
It updates Apple's IONetworkingFamily.kext/Contents/PlugIns/AppleRTL8169Ethernet.kext with a 32 bit only version that adds support for the Realtek RTL8111E;
http://www.realtek.com.tw/DOWNLOADS/downlo...p;GetDown=false

GA-EX58-UD3R rev. 1.0, GA-EX58-UD3R-SLI, GA-EX58-UD4, GA-EX58-DS4, GA-EX58-UD4P, GA-EX58-UD5, GA-EX58-UD7, GA-X58A-UD3R rev. 1.0, GA-X58A-UD5 rev. 1.0 and GA-X58A-UD7 rev 1.0 (Realtek RTL8111D);
The Realtek RTL8111D isn't recognized by the kexts supplied with the OS, but Bit Shoveler's RealtekR1000SL.kext can be used.
It's Bonjour and WOL enabled, even though womp won't be seen with pmset, and `Wake for Ethernet network access' won't be seen in Energy Saver.
Some applications need en0 to be recognized as IOBuiltin=Yes, and there are at least four ways to fix this.
The second, third and fourth also eliminate the need for using PlatformUUID.kext to stop the `unable to determine UUID for host. Error: 35' errors from continuing after boot, for those still using C2RC3.
C2RC4 doesn't require PlatformUUID.kext.

A. Add the following in com.apple.Boot.plist for C2RC4;
<key>PciRoot</key>
<string>1</string>
<key>EthernetBuiltIn</key>
<string>yes</string>

or

B. Thanks to Rudy Pedraza, modify Bit Shoveler's RealtekR1000SL.cpp source file and compile.

original:
CODE

if (pciDev != NULL)
{
pciDev->close(this);
}
modified:
CODE

if (pciDev != NULL)
{
pciDev->setProperty("built-in",1);
pciDev->close(this);
}

or

C. Add the following within `Device (PEX4)'.
CODE
Device (LAN0)
{
Name (_ADR, 0x00)
Name (_PRW, Package (0x02)
{
0x0B,
0x04
})
Method (_DSM, 4, NotSerialized)
{
Store (Package (0x04)
{
"built-in",
Buffer (0x01)
{
0x01
},
"device_type",
Buffer (0x09)
{
"ethernet"
}

}, Local0)
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}

or

D. Add an ethernet EFI string that contains the built-in key with a value of 1 to com.apple.Boot.plist, see ~pcwiz's topic at http://www.insanelymac.com/forum/index.php?showtopic=114349.
However, you will need to run `gfxutil -f pex4' instead of `gfxutil -f ethernet' in Terminal to determine DevicePath.

19. (added 20100426) Video options.

A. Video is most simply enabled in com.apple.Boot.plist.

For C2RC4;
<key>PciRoot</key>
<string>1</string>
<key>GraphicsEnabler</key>
<string>yes</string>

For ABLN1.1.x;
<key>GraphicsEnabler</key>
<string>yes</string>

or

B. Thanks to aschar1 for a modification to instead enable one or more video cards directly in DSDT (start with post 659);
http://www.insanelymac.com/forum/index.php...6771&st=658

20. (added 20100726) Add the following to com.apple.Boot.plist if you're using the Chameleon-Mozodojo bootloader;

<key>GenerateCStates</key>
<string>yes</string>

Over clocking;

These are my settings for a 2.66 GHz Xeon W3520 with 6x2GB 1333 MHz memory.
Up to 3.7 GHz all voltages can be left at auto.
`About This Mac' only goes up to 4.3 GHz, edit /System/Library/CoreServices/loginwindow.app/Contents/Resources/English.lproj/AboutThisMac.strings if you want it to show over that;
//"ABOUT_BOX_SINGLE_PROCESSOR_FIELD_FORMAT" = "%@";
"ABOUT_BOX_SINGLE_PROCESSOR_FIELD_FORMAT" = "4.4 GHz Quad-Core Intel Xeon";

At 4 GHz maximum Geekbench score is 14124 with memory x8 at maximum stable speed of 1600 MHz:
CODE

Advanced CPU Features:
CPU Clock Ratio ................................ [20x]
Intel® Turbo Boost Tech .................. [Enabled]
CPU Cores Enabled ............................ [All]
CPU Multi Threading .......................... [Enabled]
CPU Enhanced Halt (C1E) ................... [Enabled]
C3/C6/C7 State Support .................... [Disabled] enabled
CPU Thermal Monitor ......................... [Enabled]
CPU EIST Function ............................ [Enabled]
Bi-Directional PROCHOT ..................... [Enabled]
Virtualization Technology ................... [Enabled]

Uncore & QPI Features:
QPI Link Speed .............................. [x36] (7.2 GHz)
Uncore Frequency .......................... (must be 2x System Memory Multiplier) x17 (3200 MHz)
Isonchronous Frequency ..................[Enabled]

Standard Clock Control:
Base Clock (BCLK) Control ................ [Enabled] enabled
BCLK Frequency (MHz) ..................... [133] 200
PCI Express Frequency (MHz) ........... [100]
C.I.A.2 [Disabled]

Advanced Clock Control:
CPU Clock Drive ................... [800mV]
PCI Express Clock Drive ................... [900mV]
CPU Clock Skew ............................. [0ps]
IOH Clock Skew ............................. [0ps]

Advanced DRAM Features:
Performance Enhance ...................... [Turbo] standard
Extreme Memory Profile (X.M.P) ......... [Disabled]
System Memory Multiplier (SPD) ........ [Auto] x8 (1600 MHz)
DRAM Timing Selectable (SPD) .......... [Auto] manual

Channel A + B + C

Channel A Timing Settings:
##Channel A Standard Timing Control##
CAS Latency Time ...................... [Auto] 11
tRCD ....................................... [Auto] 15
tRP ......................................... [Auto] 15
tRAS ....................................... [Auto] 31
Command Rate (CMD) ......................... [Auto] 2

##Channel A Advanced Timing Control##
tRC ........................................ (Should be = tRAS + tRP or above for stability)
tRRD .......................................
tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4)
tWR ........................................
tWTP ....................................... (tWTP Must = tWR + tWL + 4)
tWL ........................................ (tWL Must be CAS Latency -1)
tRFC .......................................
tRTP .......................................
tFAW ......................................
Command Rate (CMD) ................

##Channel A Misc Timing Control##
Round Trip Latency ...................

Advanced Voltage Control:

CPU
Load Line Calibration ................. [Disabled] enabled
CPU Vcore 1.2375v ................. [Auto] normal
Dynamic Vcore (DVID) ............ [Auto] +0.24375
QPI/VTT Voltage 1.2v ............ [Auto] 1.58
CPU PLL 1.800v ....................... [Auto] 1.88

MCH/ICH
PCIE 1.500v ........................... [Auto]
QPI PLL 1.100v ....................... [Auto] 1.4
IOH Core 1.100v ..................... [Auto] 1.3
ICH I/O 1.500v ....................... [Auto]
ICH Core 1.1v ........................ [Auto]

DRAM
DRAM Voltage 1.500v .............. [Auto] 1.54
DRAM Termination 0.750v [Auto] .77
Ch-A Data VRef. 0.750v [Auto] .77
Ch-B Data VRef. 0.750v [Auto] .77
Ch-C Data VRef. 0.750v [Auto] .77
Ch-A Address VRef. 0.750v [Auto] .77
Ch-B Address VRef. 0.750v [Auto] .77
Ch-C Address VRef. 0.750v [Auto] .77

At 4.1 GHz disabled turbo because of KPs, with memory x6 at 1230 MHz;
CODE

Advanced CPU Features:
CPU Clock Ratio ................................ [20x]
Intel® Turbo Boost Tech .................. [Enabled] disabled
CPU Cores Enabled ............................ [All]
CPU Multi Threading .......................... [Enabled]
CPU Enhanced Halt (C1E) ................... [Enabled]
C3/C6/C7 State Support .................... [Disabled] enabled
CPU Thermal Monitor ......................... [Enabled]
CPU EIST Function ............................ [Enabled]
Bi-Directional PROCHOT ..................... [Enabled]
Virtualization Technology ................... [Enabled]

Uncore & QPI Features:
QPI Link Speed .............................. [x36] (7.38 GHz)
Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2665 MHz)
Isonchronous Frequency ..................[Enabled]

Standard Clock Control:
Base Clock (BCLK) Control ................ [Enabled] enabled
BCLK Frequency (MHz) ..................... [133] 205
PCI Express Frequency (MHz) ........... [100]
C.I.A.2 [Disabled]

Advanced Clock Control:
CPU Clock Drive ................... [800mV]
PCI Express Clock Drive ................... [900mV]
CPU Clock Skew ............................. [0ps]
IOH Clock Skew ............................. [0ps]

Advanced DRAM Features:
Performance Enhance ...................... [Turbo] standard
Extreme Memory Profile (X.M.P) ......... [Disabled]
System Memory Multiplier (SPD) ........ [Auto] x6 (1230 MHz)
DRAM Timing Selectable (SPD) .......... [Auto]

Channel A + B + C

Channel A Timing Settings:
##Channel A Standard Timing Control##
CAS Latency Time ...................... [Auto]
tRCD ....................................... [Auto]
tRP ......................................... [Auto]
tRAS ....................................... [Auto]
Command Rate (CMD) ......................... [Auto]

##Channel A Advanced Timing Control##
tRC ........................................ (Should be = tRAS + tRP or above for stability)
tRRD .......................................
tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4)
tWR ........................................
tWTP ....................................... (tWTP Must = tWR + tWL + 4)
tWL ........................................ (tWL Must be CAS Latency -1)
tRFC .......................................
tRTP .......................................
tFAW ......................................
Command Rate (CMD) ................

##Channel A Misc Timing Control##
Round Trip Latency ...................

Advanced Voltage Control:

CPU
Load Line Calibration ................. [Disabled] enabled
CPU Vcore 1.2375v ................. [Auto] normal
Dynamic Vcore (DVID) ............ [Auto] +0.2125
QPI/VTT Voltage 1.2v ............ [Auto] 1.52
CPU PLL 1.800v ....................... [Auto] 1.88

MCH/ICH
PCIE 1.500v ........................... [Auto]
QPI PLL 1.100v ....................... [Auto] 1.3
IOH Core 1.100v ..................... [Auto] 1.3
ICH I/O 1.500v ....................... [Auto]
ICH Core 1.1v ........................ [Auto]

DRAM
DRAM Voltage 1.500v .............. [Auto] 1.54
DRAM Termination 0.750v [Auto]
Ch-A Data VRef. 0.750v [Auto]
Ch-B Data VRef. 0.750v [Auto]
Ch-C Data VRef. 0.750v [Auto]
Ch-A Address VRef. 0.750v [Auto]
Ch-B Address VRef. 0.750v [Auto]
Ch-C Address VRef. 0.750v [Auto]

At 4.2 GHz with memory x6 at 1260 MHz:
CODE

Advanced CPU Features:
CPU Clock Ratio ................................ [20x]
Intel® Turbo Boost Tech .................. [Enabled] disabled
CPU Cores Enabled ............................ [All]
CPU Multi Threading .......................... [Enabled]
CPU Enhanced Halt (C1E) ................... [Enabled]
C3/C6/C7 State Support .................... [Disabled] enabled
CPU Thermal Monitor ......................... [Enabled]
CPU EIST Function ............................ [Enabled]
Bi-Directional PROCHOT ..................... [Enabled]
Virtualization Technology ................... [Enabled]

Uncore & QPI Features:
QPI Link Speed .............................. [x36] (7.56 GHz)
Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2730 MHz)
Isonchronous Frequency ..................[Enabled]

Standard Clock Control:
Base Clock (BCLK) Control ................ [Enabled] enabled
BCLK Frequency (MHz) ..................... [133] 210
PCI Express Frequency (MHz) ........... [100]
C.I.A.2 [Disabled]

Advanced Clock Control:
CPU Clock Drive ................... [800mV]
PCI Express Clock Drive ................... [900mV]
CPU Clock Skew ............................. [0ps]
IOH Clock Skew ............................. [0ps]

Advanced DRAM Features:
Performance Enhance ...................... [Turbo] standard
Extreme Memory Profile (X.M.P) ......... [Disabled]
System Memory Multiplier (SPD) ........ [Auto] x6 (1260 MHz)
DRAM Timing Selectable (SPD) .......... [Auto]

Channel A + B + C

Channel A Timing Settings:
##Channel A Standard Timing Control##
CAS Latency Time ...................... [Auto]
tRCD ....................................... [Auto]
tRP ......................................... [Auto]
tRAS ....................................... [Auto]
Command Rate (CMD) ......................... [Auto]

##Channel A Advanced Timing Control##
tRC ........................................ (Should be = tRAS + tRP or above for stability)
tRRD .......................................
tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4)
tWR ........................................
tWTP ....................................... (tWTP Must = tWR + tWL + 4)
tWL ........................................ (tWL Must be CAS Latency -1)
tRFC .......................................
tRTP .......................................
tFAW ......................................
Command Rate (CMD) ................

##Channel A Misc Timing Control##
Round Trip Latency ...................

Advanced Voltage Control:

CPU
Load Line Calibration ................. [Disabled] enabled
CPU Vcore 1.2375v ................. [Auto] normal
Dynamic Vcore (DVID) ............ [Auto] +0.225
QPI/VTT Voltage 1.2v ............ [Auto] 1.52
CPU PLL 1.800v ....................... [Auto] 1.88

MCH/ICH
PCIE 1.500v ........................... [Auto]
QPI PLL 1.100v ....................... [Auto] 1.3
IOH Core 1.100v ..................... [Auto] 1.3
ICH I/O 1.500v ....................... [Auto]
ICH Core 1.1v ........................ [Auto]

DRAM
DRAM Voltage 1.500v .............. [Auto] 1.54
DRAM Termination 0.750v [Auto]
Ch-A Data VRef. 0.750v [Auto]
Ch-B Data VRef. 0.750v [Auto]
Ch-C Data VRef. 0.750v [Auto]
Ch-A Address VRef. 0.750v [Auto]
Ch-B Address VRef. 0.750v [Auto]
Ch-C Address VRef. 0.750v [Auto]

At 4.3 GHz disabled DVID because resume from S3 sleep doesn't work above +0.225, and maximum Geekbench score is 14104 with memory x6 at 1290 MHz:
CODE

Advanced CPU Features:
CPU Clock Ratio ................................ [20x]
Intel® Turbo Boost Tech .................. [Enabled] disabled
CPU Cores Enabled ............................ [All]
CPU Multi Threading .......................... [Enabled]
CPU Enhanced Halt (C1E) ................... [Enabled]
C3/C6/C7 State Support .................... [Disabled] enabled
CPU Thermal Monitor ......................... [Enabled]
CPU EIST Function ............................ [Enabled]
Bi-Directional PROCHOT ..................... [Enabled]
Virtualization Technology ................... [Enabled]

Uncore & QPI Features:
QPI Link Speed .............................. [x36] (7.74 GHz)
Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2795 MHz)
Isonchronous Frequency ..................[Enabled]

Standard Clock Control:
Base Clock (BCLK) Control ................ [Enabled] enabled
BCLK Frequency (MHz) ..................... [133] 215
PCI Express Frequency (MHz) ........... [100]
C.I.A.2 [Disabled]

Advanced Clock Control:
CPU Clock Drive ................... [800mV]
PCI Express Clock Drive ................... [900mV]
CPU Clock Skew ............................. [0ps]
IOH Clock Skew ............................. [0ps]

Advanced DRAM Features:
Performance Enhance ...................... [Turbo] standard
Extreme Memory Profile (X.M.P) ......... [Disabled]
System Memory Multiplier (SPD) ........ [Auto] x6 (1290 MHz)
DRAM Timing Selectable (SPD) .......... [Auto]

Channel A + B + C

Channel A Timing Settings:
##Channel A Standard Timing Control##
CAS Latency Time ...................... [Auto]
tRCD ....................................... [Auto]
tRP ......................................... [Auto]
tRAS ....................................... [Auto]
Command Rate (CMD) ......................... [Auto]

##Channel A Advanced Timing Control##
tRC ........................................ (Should be = tRAS + tRP or above for stability)
tRRD .......................................
tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4)
tWR ........................................
tWTP ....................................... (tWTP Must = tWR + tWL + 4)
tWL ........................................ (tWL Must be CAS Latency -1)
tRFC .......................................
tRTP .......................................
tFAW ......................................
Command Rate (CMD) ................

##Channel A Misc Timing Control##
Round Trip Latency ...................

Advanced Voltage Control:

CPU
Load Line Calibration ................. [Disabled] enabled
CPU Vcore 1.2375v ................. [Auto] 1.46875
Dynamic Vcore (DVID) ............ [Auto] +0.00000
QPI/VTT Voltage 1.2v ............ [Auto] 1.56
CPU PLL 1.800v ....................... [Auto] 1.88

MCH/ICH
PCIE 1.500v ........................... [Auto]
QPI PLL 1.100v ....................... [Auto] 1.38
IOH Core 1.100v ..................... [Auto] 1.3
ICH I/O 1.500v ....................... [Auto]
ICH Core 1.1v ........................ [Auto]

DRAM
DRAM Voltage 1.500v .............. [Auto] 1.54
DRAM Termination 0.750v [Auto]
Ch-A Data VRef. 0.750v [Auto]
Ch-B Data VRef. 0.750v [Auto]
Ch-C Data VRef. 0.750v [Auto]
Ch-A Address VRef. 0.750v [Auto]
Ch-B Address VRef. 0.750v [Auto]
Ch-C Address VRef. 0.750v [Auto]

At 4.4 GHz maximum Geekbench score is 14309 with memory x6 at 1320 MHz:
CODE

Advanced CPU Features:
CPU Clock Ratio ................................ [20x]
Intel® Turbo Boost Tech .................. [Enabled] disabled
CPU Cores Enabled ............................ [All]
CPU Multi Threading .......................... [Enabled]
CPU Enhanced Halt (C1E) ................... [Enabled]
C3/C6/C7 State Support .................... [Disabled] enabled
CPU Thermal Monitor ......................... [Enabled]
CPU EIST Function ............................ [Enabled]
Bi-Directional PROCHOT ..................... [Enabled]
Virtualization Technology ................... [Enabled]

Uncore & QPI Features:
QPI Link Speed .............................. [x36] (7.92 GHz)
Uncore Frequency .......................... (must be 2x System Memory Multiplier +1) x13 (2860 MHz)
Isonchronous Frequency ..................[Enabled]

Standard Clock Control:
Base Clock (BCLK) Control ................ [Enabled] enabled
BCLK Frequency (MHz) ..................... [133] 220
PCI Express Frequency (MHz) ........... [100]
C.I.A.2 [Disabled]

Advanced Clock Control:
CPU Clock Drive ................... [800mV]
PCI Express Clock Drive ................... [900mV]
CPU Clock Skew ............................. [0ps]
IOH Clock Skew ............................. [0ps]

Advanced DRAM Features:
Performance Enhance ...................... [Turbo] standard
Extreme Memory Profile (X.M.P) ......... [Disabled]
System Memory Multiplier (SPD) ........ [Auto] x6 (1320 MHz)
DRAM Timing Selectable (SPD) .......... [Auto]

Channel A + B + C

Channel A Timing Settings:
##Channel A Standard Timing Control##
CAS Latency Time ...................... [Auto]
tRCD ....................................... [Auto]
tRP ......................................... [Auto]
tRAS ....................................... [Auto]
Command Rate (CMD) ......................... [Auto]

##Channel A Advanced Timing Control##
tRC ........................................ (Should be = tRAS + tRP or above for stability)
tRRD .......................................
tWTR ...................................... (Must be Write to Read Delay/Same Rank - (tWL + 4)
tWR ........................................
tWTP ....................................... (tWTP Must = tWR + tWL + 4)
tWL ........................................ (tWL Must be CAS Latency -1)
tRFC .......................................
tRTP .......................................
tFAW ......................................
Command Rate (CMD) ................

##Channel A Misc Timing Control##
Round Trip Latency ...................

Advanced Voltage Control:

CPU
Load Line Calibration ................. [Disabled] enabled
CPU Vcore 1.2375v ................. [Auto] 1.58125
Dynamic Vcore (DVID) ............ [Auto] +0.00000
QPI/VTT Voltage 1.2v ............ [Auto] 1.58
CPU PLL 1.800v ....................... [Auto] 1.88

MCH/ICH
PCIE 1.500v ........................... [Auto]
QPI PLL 1.100v ....................... [Auto] 1.4
IOH Core 1.100v ..................... [Auto] 1.3
ICH I/O 1.500v ....................... [Auto]
ICH Core 1.1v ........................ [Auto]

DRAM
DRAM Voltage 1.500v .............. [Auto] 1.54
DRAM Termination 0.750v [Auto]
Ch-A Data VRef. 0.750v [Auto]
Ch-B Data VRef. 0.750v [Auto]
Ch-C Data VRef. 0.750v [Auto]
Ch-A Address VRef. 0.750v [Auto]
Ch-B Address VRef. 0.750v [Auto]
Ch-C Address VRef. 0.750v [Auto]


This guide's configuration has been tested on GA-EX58-UD5;
BIOS F9e (added CPU8-F) and F9h with 10.6.0 through 10.6.2 in 32 bit mode using Chameleon-2.0-RC3-r658 and boot_v10.5
BIOS F9h, F9m (added DVID), F9p, F9 and F10 with 10.6.2 in 32 and 64 bit mode using Chameleon-2.0-RC4-r684
BIOS F10 through F12 with 10.6.2 in 64 bit mode using Chameleon-2.0-RC4-r684 and Booter_AsereBLN_v1.1.8.
BIOS F12 with 10.6.3 and 10.6.4 in 64 bit mode using Chameleon-2.0-RC4-r684 and Booter_AsereBLN_v1.1.8.
BIOS F12 with 10.6.4 in 64 bit mode using Chameleon-Mozodojo-262.

There's a Gigabyte bug that can cause a network port to cease functioning.
Shut the machine down, turn off the power supply, press and hold the CMOS button until the light goes out.
Start the machine, press the tab key at the logo screen, then the delete key at the post screen, then in the main menu press the F12 key to select your saved BIOS settings.

Here's how to tell if a kext is both 32 bit (i386) and 64 bit (x86_64);
[mac05:~] me% file RealtekR1000SL/Contents/MacOS/RealtekR1000SL
RealtekR1000SL.kext/Contents/MacOS/RealtekR1000SL: Mach-O universal binary with 2 architectures
RealtekR1000SL.kext/Contents/MacOS/RealtekR1000SL (for architecture x86_64): Mach-O 64-bit kext bundle x86_64
RealtekR1000SL.kext/Contents/MacOS/RealtekR1000SL (for architecture i386): Mach-O object i386
[mac05:~] me%

Kexts in my Extensions.mkext;
LegacyHDA.kext
OrangeIconFix.kext
fakesmc.kext

Added RealtekR1000SL.kext to my /System/Library/Extensions/IONetworkingFamily.kext/Contents/PlugIns/ folder.

Links;
digital_dreamer's Retail Snow Leopard Install Guide: http://www.insanelymac.com/forum/index.php?showtopic=185097
Gigabyte's corei7_x58_bios_guide.pdf: http://www.gigabyte-usa.com/FileList/NewTe..._bios_guide.pdf
Chrysaor's MSR Tools (32 bit only, post 89): http://www.insanelymac.com/forum/index.php...81631&st=88
THe KiNG's MP41SpeedStepFix.kext (for 10.6.0 and 10.6.1): google for the link
demong1's MacPro4_1.plist (see warning at bottom): located in the same forum site and topic as MP41SpeedStepFix.kext
David F. Elliott's NullCPUPowerManagement.kext: http://tgwbd.org/darwin/extensions.html
David F. Elliott's ElliottForceLegacyRTC.kext: http://stellarola.tumblr.com/post/165429070/prepare-yourself
EvOSX86 Team's DSDTSE: http://www.osx86.es/?p=610
fassl's getDSDT.sh: http://www.insanelymac.com/forum/index.php?showtopic=133683
ab___73's getSSDT5.sh: http://www.insanelymac.com/forum/index.php?showtopic=145792
cVad's iasl: http://www.insanelymac.com/forum/index.php?showtopic=189272
THe KiNG's OrangeIconFix.kext: google for the link
netkas's fakesmc.kext: google for the link
KWS's PenntNeu-script: http://www.insanelymac.com/forum/index.php?showtopic=182535
VoodooLabs's Chameleon-2.0-RC4-r684: google for the link
netkas's boot_v10.5: google for the link
Asere's Booter_AsereBLN_v1.1.9: google for the link
Chameleon-Mozodojo bootloader:
http://www.projectosx.com/forum/index.php?showtopic=1337
http://forge.voodooprojects.org/p/chameleo...anches/mozodojo
Bit Shoveler's RealtekR1000SL.kext (post 631): http://www.insanelymac.com/forum/index.php...9436&st=630
superhai's PlatformUUID.kext: google for link
OSX86 Tools Utility: http://code.google.com/p/osx86tools/
EvOSX86 Team's EvOreboot.kext: google for link
Gigabyte BIOS beta: http://forums.tweaktown.com/f69/gigabyte-latest-bios-28441
Gigabyte OC thread: http://www.xtremesystems.org/forums/showthread.php?t=209013
Marcel Bresink's Temperature Monitor: http://www.bresink.com/osx/TemperatureMonitor.html
mprime: http://mersenne.org/freesoft/
Geekbench: http://www.primatelabs.ca/geekbench/

Warning: Using demong1's modified MacPro4_1.plist, then applying an Apple Software Update like Bonjour Update 2010-001 can break things so that you have no mouse or keyboard control at the login GUI.
I traced the problem to the use of tabs instead of spaces, this can be seen with running `cat -vet MacPro4_1.plist' in Terminal.
In kernel.log, the `Kext com.apple.driver.ACPI_SMC_PlatformPlugin failed to load' error was seen with Root set for the OSBundleRequired in the Info.plist for ACPI_SMC_PlatformPlugin.kext and IOPlatformPluginFamily.kext, and `virtual bool IOHIDEventSystemUserClient::initWithTask(task*, void*, UInt32): Client task not privileged to open IOHIDSystem for mapping memory' was seen with Safe-Boot (default) set for OSBundleRequired.
10.6.0 through 10.6.3;
Use my instructions at the top of the post to get a working modified MacPro4_1.plist.
10.6.3 with Mac Pro Audio Update 1.1, and 10.6.4;
Apple has enabled speed step in an updated MacPro4_1.plist.

Warning: 10.6.4 will severely decrease NVIDIA GPU performance.
Don't update, or read item 7 for a workaround.

Note: Some corrections were made to the CStates of the CPU section of the instructions and DSDT attachments as of F9m, and this solves the issue of 32 bit boot and KP after wake when starting some non Apple applications.

Attachments;
DSDT.aml and dsdt.dsl for i7 920 and Xeon W3520, derived from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep, fixes (doesn't include 18 and 19) and audio option B: DSDT_GA_EX58_UD5_F9m_S3_920_W3520_v2.zip
DSDT.aml and dsdt.dsl for i7 950 and Xeon W3550, derived from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep, fixes (doesn't include 18 and 19) and audio option B: DSDT_GA_EX58_UD5_F9m_S3_950_W3550_v2.zip
DSDT.aml and dsdt.dsl for i7 975 and Xeon W3580, derived from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep, fixes (doesn't include 18 and 19) and audio option B: DSDT_GA_EX58_UD5_F9m_S3_975_W3580_v2.zip
Unmodified dsdt.dsl from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep: dsdt_ga_ex58_ud5_f9m_s3.dsl.zip
DSDT.aml and dsdt.dsl for i7 930 and Xeon W3530, derived from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep, fixes (doesn't include 18 and 19) and audio option B: DSDT_GA_EX58_UD5_F9m_S3_930_W3530_v2.zip
DSDT.aml and dsdt.dsl for any CPU using the Chameleon-Mozodojo bootloader, derived from GA-EX58-UD5 and BIOS F9m through F12, with S3 sleep, fixes (doesn't include 18 and 19) and audio option D: DSDT_GA_EX58_UD5_F9m_S3_Chameleon-Mozodojo_v4.zip

.
Attached File(s)
Attached File  DSDT_GA_EX58_UD5_F9m_S3_920_W3520_v2.zip ( 20.23K ) Number of downloads: 915
Attached File  DSDT_GA_EX58_UD5_F9m_S3_950_W3550_v2.zip ( 20.32K ) Number of downloads: 91
Attached File  DSDT_GA_EX58_UD5_F9m_S3_975_W3580_v2.zip ( 20.39K ) Number of downloads: 93
Attached File  dsdt_ga_ex58_ud5_f9m_s3.dsl.zip ( 11.86K ) Number of downloads: 145
Attached File  DSDT_GA_EX58_UD5_F9m_S3_930_W3530_v2.zip ( 21.1K ) Number of downloads: 130
Attached File  DSDT_GA_EX58_UD5_F9m_S3_Chameleon_Mozodojo_v4.zip ( 19.66K ) Number of downloads: 14
 
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Posts in this topic
- d00d   GA-EX58 and GA-X58A DSDT native power management modifications   Nov 9 2009, 10:03 PM
- - The Real Deal   Will you graciously release like you did for the F...   Feb 4 2010, 03:54 AM
|- - d00d   QUOTE (The Real Deal @ Feb 3 2010, 10:54 ...   Feb 4 2010, 02:46 PM
|- - The Real Deal   QUOTE (d00d @ Feb 4 2010, 03:39 PM) I upd...   Feb 4 2010, 02:47 PM
|- - apple_core   QUOTE (d00d @ Feb 4 2010, 07:46 AM) Thank...   Feb 15 2010, 08:10 PM
|- - d00d   QUOTE (apple_core @ Feb 15 2010, 03:10 PM...   Feb 16 2010, 12:10 AM
|- - apple_core   QUOTE (d00d @ Feb 15 2010, 05:10 PM) Eith...   Feb 16 2010, 02:02 AM
- - Lyle M   QUOTE (d00d @ Nov 9 2009, 05:03 PM) I...   Feb 4 2010, 04:01 AM
- - callumj09   I made a few changes to my system yesterday which ...   Feb 4 2010, 11:24 AM
|- - d00d   QUOTE (callumj09 @ Feb 4 2010, 06:24 AM) ...   Feb 9 2010, 01:09 AM
|- - aikidoka25   QUOTE (d00d @ Feb 8 2010, 08:09 PM) I tri...   Feb 9 2010, 04:47 AM
||- - The Real Deal   QUOTE (aikidoka25 @ Feb 9 2010, 05:47 AM)...   Feb 10 2010, 06:37 PM
||- - LocusOfControl   QUOTE (The Real Deal @ Feb 10 2010, 06:37...   Feb 10 2010, 08:28 PM
|- - LocusOfControl   QUOTE (d00d @ Feb 9 2010, 01:09 AM) I tri...   Feb 9 2010, 09:57 AM
||- - d00d   QUOTE (LocusOfControl @ Feb 9 2010, 04:57...   Feb 9 2010, 01:28 PM
|- - callumj09   QUOTE (d00d @ Feb 9 2010, 01:09 AM) I tri...   Feb 10 2010, 10:01 AM
|- - d00d   QUOTE (callumj09 @ Feb 10 2010, 05:01 AM)...   Feb 10 2010, 12:35 PM
|- - Cosmin Petre   QUOTE If you have a GA-EX58-UD5 with an i7 920 or ...   Feb 10 2010, 03:46 PM
|- - d00d   QUOTE (Cosmin Petre @ Feb 10 2010, 10:46 ...   Feb 10 2010, 03:51 PM
|- - Cosmin Petre   QUOTE (d00d @ Feb 10 2010, 03:51 PM) You...   Feb 10 2010, 04:14 PM
- - ryansimms   I keep getting "couldn't find en0" e...   Feb 5 2010, 04:41 AM
|- - d00d   QUOTE (ryansimms @ Feb 4 2010, 11:41 PM) ...   Feb 5 2010, 01:25 PM
- - raymondh   I have a gigabyte ud5 i7 920 with a geforce gts250...   Feb 5 2010, 06:02 AM
- - The Real Deal   I installed the magic mouse today. A bit tricky to...   Feb 5 2010, 05:34 PM
|- - LocusOfControl   QUOTE (The Real Deal @ Feb 5 2010, 05:34 ...   Feb 5 2010, 11:42 PM
- - tsunoo   I don't know if this link may help in a near f...   Feb 5 2010, 09:04 PM
- - The Real Deal   I was wondering if some of you, use a wifi connect...   Feb 5 2010, 11:21 PM
|- - HawgGuy   QUOTE (The Real Deal @ Feb 5 2010, 11:21 ...   Feb 7 2010, 04:55 PM
- - The Real Deal   My two ethernet ports are shown as: ethernet ethe...   Feb 6 2010, 04:42 AM
- - MowgliBook   Here is my DSDT for EX58-UD4P + i7 920. Perfectly ...   Feb 6 2010, 10:13 PM
- - swtos   Soft Raid configuration, Ga-EX58-UD5 with Bios rev...   Feb 7 2010, 10:16 AM
- - The Real Deal   haha, thanks. I have ordered a Dell 1490+MP2W, hop...   Feb 7 2010, 04:59 PM
- - The Real Deal   i am currently modding the IOPlatformPlugin to dow...   Feb 8 2010, 03:02 AM
|- - The Real Deal   QUOTE (The Real Deal @ Feb 8 2010, 04:02 ...   Feb 17 2010, 04:07 AM
|- - d00d   QUOTE (The Real Deal @ Feb 16 2010, 11:07...   Feb 17 2010, 12:44 PM
|- - The Real Deal   QUOTE (d00d @ Feb 17 2010, 01:44 PM) Yes,...   Feb 17 2010, 08:08 PM
- - FUT1L1TY   d00d, Please let us know if there are any DSDT ch...   Feb 8 2010, 05:40 PM
|- - d00d   QUOTE (FUT1L1TY @ Feb 8 2010, 12:40 PM) d...   Feb 8 2010, 06:06 PM
- - The Real Deal   BIOS F10 is only two days old... thanks for your h...   Feb 8 2010, 09:19 PM
- - callumj09   Just a quick question at #14, it says: QUOTE To ge...   Feb 10 2010, 12:22 AM
|- - d00d   QUOTE (callumj09 @ Feb 9 2010, 07:22 PM) ...   Feb 10 2010, 12:39 AM
|- - ryansimms   QUOTE (callumj09 @ Feb 9 2010, 07:22 PM) ...   Feb 11 2010, 04:27 AM
|- - d00d   QUOTE (ryansimms @ Feb 10 2010, 11:27 PM)...   Feb 11 2010, 04:40 PM
|- - ryansimms   QUOTE (d00d @ Feb 11 2010, 11:40 AM) What...   Feb 11 2010, 05:43 PM
|- - d00d   QUOTE (ryansimms @ Feb 11 2010, 12:43 PM)...   Feb 11 2010, 07:09 PM
|- - ryansimms   QUOTE (d00d @ Feb 11 2010, 02:09 PM) Does...   Feb 11 2010, 08:40 PM
|- - d00d   QUOTE (ryansimms @ Feb 11 2010, 03:40 PM)...   Feb 11 2010, 10:46 PM
- - callumj09   I have just tried the above solution with my DSDT ...   Feb 11 2010, 09:34 PM
|- - ryansimms   QUOTE (callumj09 @ Feb 11 2010, 04:34 PM)...   Feb 12 2010, 04:17 AM
|- - ryansimms   QUOTE (ryansimms @ Feb 11 2010, 11:17 PM)...   Feb 12 2010, 05:58 AM
|- - d00d   QUOTE (ryansimms @ Feb 12 2010, 12:58 AM)...   Feb 12 2010, 01:43 PM
|- - ryansimms   QUOTE (d00d @ Feb 12 2010, 08:43 AM) You ...   Feb 13 2010, 05:58 AM
- - voll@   Hi dood! put the update, the sound disappeare...   Feb 13 2010, 01:30 AM
- - voll@   I use Legacy RealtekALC888.kextCODEDevice (HDEF) ...   Feb 13 2010, 06:41 AM
|- - ryansimms   QUOTE (voll@ @ Feb 13 2010, 01:41 AM) I u...   Feb 13 2010, 04:41 PM
|- - d00d   QUOTE (voll@ @ Feb 13 2010, 01:41 AM) I u...   Feb 13 2010, 06:28 PM
- - star-affinity   I need help. It sucks being such a n00b, but what ...   Feb 14 2010, 12:22 AM
|- - d00d   QUOTE (star-affinity @ Feb 13 2010, 07...   Feb 15 2010, 10:56 PM
|- - star-affinity   QUOTE (d00d @ Feb 15 2010, 11:56 PM) Look...   Feb 17 2010, 04:54 PM
- - atlee   d00d thankyou for all your DSDT edits, I'm suc...   Feb 14 2010, 11:19 AM
- - aschar1   The Mac Pro Audio Update will break sound for all ...   Feb 15 2010, 09:01 AM
|- - star-affinity   QUOTE (aschar1 @ Feb 15 2010, 10:01 AM) T...   Feb 15 2010, 07:05 PM
- - aschar1   Guys we need your help! Prasys and i am tryi...   Feb 16 2010, 09:37 AM
|- - d00d   QUOTE (aschar1 @ Feb 16 2010, 04:37 AM) G...   Feb 16 2010, 04:07 PM
- - The Real Deal   thanks aschar, it sounds great.   Feb 16 2010, 09:02 PM
- - callumj09   I have an unmodified DSDT for rev 1.0 of the GA-EX...   Feb 16 2010, 10:57 PM
|- - d00d   QUOTE (callumj09 @ Feb 16 2010, 05:57 PM)...   Feb 17 2010, 12:36 AM
- - star-affinity   When booting things stop at �€�systemShutd...   Feb 19 2010, 08:14 PM
|- - d00d   QUOTE (star-affinity @ Feb 19 2010, 03...   Feb 19 2010, 10:58 PM
|- - star-affinity   QUOTE (d00d @ Feb 19 2010, 11:58 PM) The ...   Feb 20 2010, 03:34 PM
|- - Swhay   QUOTE (star-affinity @ Feb 20 2010, 04...   Feb 23 2010, 03:52 PM
|- - star-affinity   QUOTE (Swhay @ Feb 23 2010, 04:52 PM) I h...   Feb 24 2010, 11:19 AM
- - smc13   D00d, Thanks for the information. I am running an...   Feb 20 2010, 04:26 AM
|- - d00d   QUOTE (smc13 @ Feb 19 2010, 11:26 PM) D00...   Feb 20 2010, 02:25 PM
|- - KariNeko   QUOTE (d00d @ Feb 20 2010, 12:25 PM) Beca...   Feb 20 2010, 03:22 PM
|- - smc13   QUOTE (d00d @ Feb 20 2010, 09:25 AM) You ...   Feb 20 2010, 03:56 PM
|- - LocusOfControl   QUOTE (smc13 @ Feb 20 2010, 03:56 PM) It...   Feb 20 2010, 04:31 PM
|- - smc13   QUOTE (LocusOfControl @ Feb 20 2010, 11:3...   Feb 20 2010, 06:22 PM
- - KariNeko   Hi dood, I don't have a Gigabyte X58 based boa...   Feb 20 2010, 12:09 PM
- - The Real Deal   The mod plist makes my computer a little bit laggy...   Feb 20 2010, 12:53 PM
- - smc13   Hello D00d, Thanks for your help. I put the chang...   Feb 21 2010, 06:43 PM
|- - smc13   QUOTE (smc13 @ Feb 21 2010, 01:43 PM) Hel...   Feb 22 2010, 01:31 AM
|- - d00d   QUOTE (smc13 @ Feb 21 2010, 08:31 PM) Wel...   Feb 22 2010, 03:29 AM
|- - star-affinity   QUOTE (d00d @ Feb 22 2010, 04:29 AM) Yes,...   Feb 22 2010, 12:27 PM
||- - smc13   QUOTE (star-affinity @ Feb 22 2010, 07...   Feb 22 2010, 06:26 PM
||- - CruiSAr   QUOTE (star-affinity @ Feb 22 2010, 01...   Feb 23 2010, 11:06 AM
|- - smc13   QUOTE (d00d @ Feb 21 2010, 10:29 PM) Did ...   Feb 22 2010, 03:50 PM
|- - smc13   QUOTE (smc13 @ Feb 22 2010, 10:50 AM) I t...   Feb 23 2010, 01:41 AM
- - Dathenous   There are so many super smart people on this forum...   Feb 22 2010, 03:47 PM
|- - d00d   QUOTE (Dathenous @ Feb 22 2010, 10:47 AM)...   Feb 22 2010, 06:04 PM
- - The Real Deal   BIOS F11 available   Feb 23 2010, 02:31 AM
- - star-affinity   QUOTE (smc13 @ Feb 22 2010, 07:26 PM) The...   Feb 23 2010, 03:13 PM
- - ANARCHiNTOSH   d00d, your dsdt is brilliant and negates many of t...   Feb 23 2010, 10:52 PM
- - voll@   Why the file is called ALC889a_AppleHDA_5.1_Patche...   Feb 24 2010, 10:05 AM
- - ANARCHiNTOSH   QUOTE (voll@ @ Feb 24 2010, 10:05 AM) Why...   Feb 24 2010, 10:40 AM
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