P5K PRO - Snow Leopard installation... Options

[Master Chief]

I am going to waste spent some time today trying to change this code snippet:

CODE

Name (PRWP, Package (0x02)
{
Zero,
Zero
})
Method (GPRW, 2, NotSerialized)
{
Store (Arg0, Index (PRWP, Zero))
Store (ShiftLeft (SS1, One), Local0)
Or (Local0, ShiftLeft (SS2, 0x02), Local0)
Or (Local0, ShiftLeft (SS3, 0x03), Local0)
Or (Local0, ShiftLeft (SS4, 0x04), Local0)

If (And (ShiftLeft (One, Arg1), Local0))
{
Store (Arg1, Index (PRWP, One))
}
Else
{
ShiftRight (Local0, One, Local0)
FindSetLeftBit (Local0, Index (PRWP, One))
}

Return (PRWP)
}

One of the reasons is that I looked at it a couple of times, and I keep wondering about the red line. I mean S2 isn't even supported on our Asus board so what is it doing there? Why add something when you, as developer, know that it is useless? A contractor getting payed by the line maybe?

Not to mention that this code is called up to 16 times at boot time (UHC[1-6], P0P[2-9], PCIB, EHCI and UHCI). 14 times minimum (without EHCI and UHCI). And all this bit shifting can be done with one single line. I think. What if I make it static? I mean it sure isn't going to change at run time. Does it? Nah. No way. Yeah. Let me give it a try. I like to burn my fingers on other peoples code...

This should work:

CODE

Field (BIOS, ByteAcc, NoLock, Preserve)
{
SLPM, 8,
}

Name (SLPS, Zero)
Name (PRWP, Package (0x02)
{
Zero,
Zero
})

Method (GPRW, 2, NotSerialized)
{
Store (Arg0, Index (PRWP, Zero))

If (And (ShiftLeft (One, Arg1), SLPS))
{
Store (Arg1, Index (PRWP, One))
}
Else
{
FindSetLeftBit (SLPM, Index (PRWP, One))
}

Return (PRWP)
}

At least it compiles. ACPI CA Debugger started... Oops. I forgot to add ShiftLeft (SLPM, One, SLPS) Method _PIC is my temporarily target for it. And now it works. I think. Testing... Done. It works.

Uhg. A mere four bytes smaller. Not exactly what I hoped for, but it wasn't my main concern. Boot speed is

And the names might change. Probably. Already done. BTW: The new Field (BIOS... should be put under your current one. Do not replace it with the new one! It's an addition to the current one, to get the byte value of the sleep state bits.

Note: This is an Asus specific change. Do not add Method (GPRW) when you don't already have one. However, every BIOS with Power Management (and sleep) settings should have something like this.

This change will also be part of DSDT V3.2

Right. Kids are home from school so daddy is going to have some quality time now. Later folks.

And as always... Happy Hacking!

[DB1]

And now it works. I think. Testing... Done. It works.

Works ok for me, thanks. V3.2 must be near.

Enjoy the QT.

[Master Chief]

Works ok for me, thanks. V3.2 must be near.

Enjoy the QT.

Thanks, and you are right. We're going to release DSDT V3.2 Saturday (in a few hours).

[Master Chief]

DSDT V3.2 has been released today – see attachments in post #3

The size of our previous update was:
dsdt.dsl 111.179 bytes
dsdt.aml 10.690 bytes

And todays update:
dsdt.dsl 95.260 bytes
dsdt.aml 7.957 bytes

A massive 25% off. Which makes it a rather significant update. With lots of new comments. Making the code reduction of dsdt.dsl even more impressive, since I have been adding so much spaces/text. Let's have a look at a few examples:

CODE

Device (UHC1) // Renamed from: USB0
{
Name (_ADR, 0x001D0000)
Name (_PRW, Package (0x02) // Power Resources for Wake (ACPIspec30a.pdf / 7.2.10 / page 259).
{
0x03,
0x04
})
Name (_S3D, 0x02) // S3 Device State (ACPIspec30a.pdf / 7.2.15 / page 262).

OperationRegion (BAR0, PCI_Config, 0xC4, One) // Newly added: USB_RES—USB Resume Enable Register (ICH9R-3169722.pdf /16.1.24 / page 642).
Field (BAR0, ByteAcc, NoLock, Preserve)
{
USBW, 2, Offset (0x01)
}

Method (_PSW, 1, NotSerialized) // Power State Wake (ACPIspec30a.pdf / 7.2.11 / page 260).
{
Multiply (0x03, Arg0, USBW) // Set bit 0-1 based on Arg0 (0 disable- or 1 enable wake capabilities).
}

Method (_DSM, 4, NotSerialized) // Device Specific Method (ACPIspec30a.pdf / 9.15.1 / page 321).
{
Return (MCID (Arg2, 0x3A34))
}
}

And this one:

CODE

Device (P0P4) // PCI Express Port 1
{
Name (_ADR, 0x001C0000)
Name (_PRT, Package (0x04) // PCI Routing Table AR04 (ACPIspec30a.pdf / 6.2.11 / page 204).
{
Package (0x04) { 0xFFFF, Zero, Zero, 0x10 },
Package (0x04) { 0xFFFF, One, Zero, 0x11 },
Package (0x04) { 0xFFFF, 0x02, Zero, 0x12 },
Package (0x04) { 0xFFFF, 0x03, Zero, 0x13 }
})
Name (_PRW, Package (0x02) // Power Resources for Wake (ACPIspec30a.pdf / 7.2.10 / page 259).
{
0x09,
0x04
})
}

Again highly optimized – without going back in terms of readability – to squeeze out even the very last byte. And not a single change was done by 'trial and error' but after doing a lot more, additional, reading of the ACPI specification. Quite a few hours to be honest – I don't go change anything anymore without first knowing what it does / how it works.

And while I was working on code reduction of GPRW, which I have eliminated with this update, I realized to have made an error. That is why I moved the buffers out of Methods MCID and MCBN into the global name space, because this way we reduce the memory footprint. Yup. Learned something new again.

I also know that this update might be a little too much for some. A judgment error. Which is entirely my fault. And if DB1 hadn't mentioned a new release... it might have been Christmas by now. Yeah, I should have released an update earlier, but I didn't realize what I had done since V3.1. Well, just hang in, and feel free to ask for help. As long as it's you doing most of the work

Well. I think this covers it. And as always; Happy Hacking!

@julia24 & blackosx: Thank you!

[julia24]

Thank you!!!

[blackosx]

DSDT V3.2 has been released today – see attachments in post #3

Thanks MasterChief. I always use your latest DSDT's for reference to help with my learning

[BlackCH]

DSDT V3.2 has been released today – see attachments in post #3

Thanks man!; I apreciate the work you're doing!
I brought my P5K-VM dsdt to match yours; everything seems to work good for me, except sleep-wake-restart sequence (which hangs at the point you should see the BIOS boot screen).
I got a question about:

CODE

Method (_QCD, 0, NotSerialized) // Event CD.
                    {
                        If (CDIN)
                        {
                            Notify (\_SB.PCI0.SATA.PRT2, 0x81)
                        }
                        Else
                        {
                            Notify (\_SB.PCI0.SATA.PRT2, 0x82)
                        }
                    }

As I understand, this is to be able to auto-sleep your CD-DVD drive, isnt it? If so, would be possible to use the same kind of code to work in a drive hooked to the Jmicron IDE connector (present on the P5K-VM)?

I've tryed something like this:

CODE

Notify (\_SB.PCI0.P0P4.JMB0.IDE0, 0x81)

But didnt work so far...


A note for the P5K-VM:
One could delete the code for P0P devices addressed at 0x001C0001-3 as they dont appear in the IOReg, and probably they dont exist phisically either:
 Screenshot_2009_11_21_at_11.56.34_AM.jpg ( 21.02K ) Number of downloads: 6


Thanks again Chief. Awesome work!

[kdawg]

@MC

In your C-states shouldn't this be 0x02?

CODE

Name (_CST, Package (0x04)
{
0x03,
Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x00,)},0x01,0x01,0x03E8},
Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000814, ,)},0x03,0x01,0x01F4}, //<-- 0x02??
Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000815, ,)},0x03,0x55,0xFA}
})